Codebase list binutils-riscv64-unknown-elf / 2e4876a
Rediff patches Add 0001-RISC-V-Fix-minor-issues-with-FP-csr-instructions.patch: upstream bugfix Add 0002-RISC-V-Fix-lui-relax-failure-with-relro.patch: upstream bugfix Add 0003-Add-support-for-SiFive-CLIC-CSRs.patch: include SiFive extension Keith Packard 4 years ago
4 changed file(s) with 351 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
+198
-0
debian/patches/0001-RISC-V-Fix-minor-issues-with-FP-csr-instructions.patch less more
0 From: Jim Wilson <jimw@sifive.com>
1 Date: Tue, 30 Jul 2019 14:42:16 -0700
2 Subject: RISC-V: Fix minor issues with FP csr instructions.
3
4 Mel Chen <mel.chen@sifive.com>
5 gas/
6 * testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
7 alias instructions.
8 * testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
9 -Mno-aliases.
10 * testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
11 * testsuite/gas/riscv/priv-reg.d: Update.
12 opcodes/
13 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
14 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
15 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
16 fscsr.
17 ---
18 gas/ChangeLog | 10 ++++++++++
19 gas/testsuite/gas/riscv/alias-csr.d | 23 +++++++++++++++++++++++
20 gas/testsuite/gas/riscv/alias-csr.s | 14 ++++++++++++++
21 gas/testsuite/gas/riscv/no-aliases-csr.d | 23 +++++++++++++++++++++++
22 gas/testsuite/gas/riscv/priv-reg.d | 2 +-
23 opcodes/ChangeLog | 8 ++++++++
24 opcodes/riscv-opc.c | 32 ++++++++++++++++----------------
25 7 files changed, 95 insertions(+), 17 deletions(-)
26 create mode 100644 gas/testsuite/gas/riscv/alias-csr.d
27 create mode 100644 gas/testsuite/gas/riscv/alias-csr.s
28 create mode 100644 gas/testsuite/gas/riscv/no-aliases-csr.d
29
30 diff --git a/gas/ChangeLog b/gas/ChangeLog
31 index 085ad19..1228205 100644
32 --- a/gas/ChangeLog
33 +++ b/gas/ChangeLog
34 @@ -1,3 +1,13 @@
35 +2019-07-30 Mel Chen <mel.chen@sifive.com>
36 +
37 + * testsuite/gas/riscv/alias-csr.s: Add testcase for CSR-access
38 + alias instructions.
39 + * testsuite/gas/riscv/no-aliases-csr.d: Run testcase alias-csr.s with
40 + -Mno-aliases.
41 +
42 + * testsuite/gas/riscv/alias-csr.d: Run testcase alias-csr.s.
43 + * testsuite/gas/riscv/priv-reg.d: Update.
44 +
45 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
46
47 * doc/c-riscv.texi (Instruction Formats): Add r4 type.
48 diff --git a/gas/testsuite/gas/riscv/alias-csr.d b/gas/testsuite/gas/riscv/alias-csr.d
49 new file mode 100644
50 index 0000000..af5c591
51 --- /dev/null
52 +++ b/gas/testsuite/gas/riscv/alias-csr.d
53 @@ -0,0 +1,23 @@
54 +#source: alias-csr.s
55 +#as: -march=rv64if
56 +#objdump: -dr
57 +
58 +.*:[ ]+file format .*
59 +
60 +
61 +Disassembly of section .text:
62 +
63 +0+000 <alias_csr>:
64 +[ ]+0:[ ]+003022f3[ ]+frcsr[ ]+t0
65 +[ ]+4:[ ]+003392f3[ ]+fscsr[ ]+t0,t2
66 +[ ]+8:[ ]+00339073[ ]+fscsr[ ]+t2
67 +[ ]+c:[ ]+002022f3[ ]+frrm[ ]+t0
68 +[ ]+10:[ ]+002312f3[ ]+fsrm[ ]+t0,t1
69 +[ ]+14:[ ]+00231073[ ]+fsrm[ ]+t1
70 +[ ]+18:[ ]+002fd2f3[ ]+fsrmi[ ]+t0,31
71 +[ ]+1c:[ ]+002fd073[ ]+fsrmi[ ]+zero,31
72 +[ ]+20:[ ]+001022f3[ ]+frflags[ ]+t0
73 +[ ]+24:[ ]+001312f3[ ]+fsflags[ ]+t0,t1
74 +[ ]+28:[ ]+00131073[ ]+fsflags[ ]+t1
75 +[ ]+2c:[ ]+001fd2f3[ ]+fsflagsi[ ]+t0,31
76 +[ ]+30:[ ]+001fd073[ ]+fsflagsi[ ]+zero,31
77 diff --git a/gas/testsuite/gas/riscv/alias-csr.s b/gas/testsuite/gas/riscv/alias-csr.s
78 new file mode 100644
79 index 0000000..8577de1
80 --- /dev/null
81 +++ b/gas/testsuite/gas/riscv/alias-csr.s
82 @@ -0,0 +1,14 @@
83 +alias_csr:
84 + frcsr t0
85 + fscsr t0, t2
86 + fscsr t2
87 + frrm t0
88 + fsrm t0, t1
89 + fsrm t1
90 + fsrmi t0, 31
91 + fsrmi 31
92 + frflags t0
93 + fsflags t0, t1
94 + fsflags t1
95 + fsflagsi t0, 31
96 + fsflagsi 31
97 diff --git a/gas/testsuite/gas/riscv/no-aliases-csr.d b/gas/testsuite/gas/riscv/no-aliases-csr.d
98 new file mode 100644
99 index 0000000..2275330
100 --- /dev/null
101 +++ b/gas/testsuite/gas/riscv/no-aliases-csr.d
102 @@ -0,0 +1,23 @@
103 +#source: alias-csr.s
104 +#as: -march=rv64if
105 +#objdump: -dr -Mno-aliases
106 +
107 +.*:[ ]+file format .*
108 +
109 +
110 +Disassembly of section .text:
111 +
112 +0+000 <alias_csr>:
113 +[ ]+0:[ ]+003022f3[ ]+csrrs[ ]+t0,fcsr,zero
114 +[ ]+4:[ ]+003392f3[ ]+csrrw[ ]+t0,fcsr,t2
115 +[ ]+8:[ ]+00339073[ ]+csrrw[ ]+zero,fcsr,t2
116 +[ ]+c:[ ]+002022f3[ ]+csrrs[ ]+t0,frm,zero
117 +[ ]+10:[ ]+002312f3[ ]+csrrw[ ]+t0,frm,t1
118 +[ ]+14:[ ]+00231073[ ]+csrrw[ ]+zero,frm,t1
119 +[ ]+18:[ ]+002fd2f3[ ]+csrrwi[ ]+t0,frm,31
120 +[ ]+1c:[ ]+002fd073[ ]+csrrwi[ ]+zero,frm,31
121 +[ ]+20:[ ]+001022f3[ ]+csrrs[ ]+t0,fflags,zero
122 +[ ]+24:[ ]+001312f3[ ]+csrrw[ ]+t0,fflags,t1
123 +[ ]+28:[ ]+00131073[ ]+csrrw[ ]+zero,fflags,t1
124 +[ ]+2c:[ ]+001fd2f3[ ]+csrrwi[ ]+t0,fflags,31
125 +[ ]+30:[ ]+001fd073[ ]+csrrwi[ ]+zero,fflags,31
126 diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
127 index 9ec5d97..d8ec868 100644
128 --- a/gas/testsuite/gas/riscv/priv-reg.d
129 +++ b/gas/testsuite/gas/riscv/priv-reg.d
130 @@ -17,7 +17,7 @@ Disassembly of section .text:
131 [ ]+1c:[ ]+04402573[ ]+csrr[ ]+a0,uip
132 [ ]+20:[ ]+00102573[ ]+frflags[ ]+a0
133 [ ]+24:[ ]+00202573[ ]+frrm[ ]+a0
134 -[ ]+28:[ ]+00302573[ ]+frsr[ ]+a0
135 +[ ]+28:[ ]+00302573[ ]+frcsr[ ]+a0
136 [ ]+2c:[ ]+c0002573[ ]+rdcycle[ ]+a0
137 [ ]+30:[ ]+c0102573[ ]+rdtime[ ]+a0
138 [ ]+34:[ ]+c0202573[ ]+rdinstret[ ]+a0
139 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
140 index cde37cf..1a1a9ee 100644
141 --- a/opcodes/ChangeLog
142 +++ b/opcodes/ChangeLog
143 @@ -1,3 +1,11 @@
144 +2019-07-30 Mel Chen <mel.chen@sifive.com>
145 +
146 + * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
147 + fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
148 +
149 + * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
150 + fscsr.
151 +
152 2019-07-05 Kito Cheng <kito.cheng@sifive.com>
153
154 * riscv-opc.c (riscv_insn_types): Add r4 type.
155 diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
156 index 113d1a5..b7e8d79 100644
157 --- a/opcodes/riscv-opc.c
158 +++ b/opcodes/riscv-opc.c
159 @@ -496,22 +496,22 @@ const struct riscv_opcode riscv_opcodes[] =
160 {"remuw", 64, {"M", 0}, "d,s,t", MATCH_REMUW, MASK_REMUW, match_opcode, 0 },
161
162 /* Single-precision floating-point instruction subset */
163 -{"frsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
164 -{"fssr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
165 -{"fssr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
166 -{"frcsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, 0 },
167 -{"fscsr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, 0 },
168 -{"fscsr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, 0 },
169 -{"frrm", 0, {"F", 0}, "d", MATCH_FRRM, MASK_FRRM, match_opcode, 0 },
170 -{"fsrm", 0, {"F", 0}, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, 0 },
171 -{"fsrm", 0, {"F", 0}, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, 0 },
172 -{"fsrmi", 0, {"F", 0}, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, 0 },
173 -{"fsrmi", 0, {"F", 0}, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, 0 },
174 -{"frflags", 0, {"F", 0}, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, 0 },
175 -{"fsflags", 0, {"F", 0}, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, 0 },
176 -{"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, 0 },
177 -{"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, 0 },
178 -{"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, 0 },
179 +{"frcsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
180 +{"frsr", 0, {"F", 0}, "d", MATCH_FRCSR, MASK_FRCSR, match_opcode, INSN_ALIAS },
181 +{"fscsr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
182 +{"fscsr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
183 +{"fssr", 0, {"F", 0}, "s", MATCH_FSCSR, MASK_FSCSR | MASK_RD, match_opcode, INSN_ALIAS },
184 +{"fssr", 0, {"F", 0}, "d,s", MATCH_FSCSR, MASK_FSCSR, match_opcode, INSN_ALIAS },
185 +{"frrm", 0, {"F", 0}, "d", MATCH_FRRM, MASK_FRRM, match_opcode, INSN_ALIAS },
186 +{"fsrm", 0, {"F", 0}, "s", MATCH_FSRM, MASK_FSRM | MASK_RD, match_opcode, INSN_ALIAS },
187 +{"fsrm", 0, {"F", 0}, "d,s", MATCH_FSRM, MASK_FSRM, match_opcode, INSN_ALIAS },
188 +{"fsrmi", 0, {"F", 0}, "d,Z", MATCH_FSRMI, MASK_FSRMI, match_opcode, INSN_ALIAS },
189 +{"fsrmi", 0, {"F", 0}, "Z", MATCH_FSRMI, MASK_FSRMI | MASK_RD, match_opcode, INSN_ALIAS },
190 +{"frflags", 0, {"F", 0}, "d", MATCH_FRFLAGS, MASK_FRFLAGS, match_opcode, INSN_ALIAS },
191 +{"fsflags", 0, {"F", 0}, "s", MATCH_FSFLAGS, MASK_FSFLAGS | MASK_RD, match_opcode, INSN_ALIAS },
192 +{"fsflags", 0, {"F", 0}, "d,s", MATCH_FSFLAGS, MASK_FSFLAGS, match_opcode, INSN_ALIAS },
193 +{"fsflagsi", 0, {"F", 0}, "d,Z", MATCH_FSFLAGSI, MASK_FSFLAGSI, match_opcode, INSN_ALIAS },
194 +{"fsflagsi", 0, {"F", 0}, "Z", MATCH_FSFLAGSI, MASK_FSFLAGSI | MASK_RD, match_opcode, INSN_ALIAS },
195 {"flw", 32, {"F", "C", 0}, "D,Cm(Cc)", MATCH_C_FLWSP, MASK_C_FLWSP, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
196 {"flw", 32, {"F", "C", 0}, "CD,Ck(Cs)", MATCH_C_FLW, MASK_C_FLW, match_opcode, INSN_ALIAS|INSN_DREF|INSN_4_BYTE },
197 {"flw", 0, {"F", 0}, "D,o(s)", MATCH_FLW, MASK_FLW, match_opcode, INSN_DREF|INSN_4_BYTE },
+49
-0
debian/patches/0002-RISC-V-Fix-lui-relax-failure-with-relro.patch less more
0 From: Jim Wilson <jimw@sifive.com>
1 Date: Thu, 1 Aug 2019 16:40:15 -0700
2 Subject: RISC-V: Fix lui relax failure with relro.
3
4 bfd/ChangeLog
5 Ilia Diachkov <ilia.diachkov@optimitech.com>
6 * elfnn-riscv.c (_bfd_riscv_relax_lui): Set lui relax safety area to
7 two pages in relro presence.
8 ---
9 bfd/ChangeLog | 5 +++++
10 bfd/elfnn-riscv.c | 9 +++++++--
11 2 files changed, 12 insertions(+), 2 deletions(-)
12
13 diff --git a/bfd/ChangeLog b/bfd/ChangeLog
14 index 1bf8d42..3584bfe 100644
15 --- a/bfd/ChangeLog
16 +++ b/bfd/ChangeLog
17 @@ -1,3 +1,8 @@
18 +2019-08-01 Ilia Diachkov <ilia.diachkov@optimitech.com>
19 +
20 + * elfnn-riscv.c (_bfd_riscv_relax_lui): Set lui relax safety area to
21 + two pages in relro presence.
22 +
23 2019-06-24 Ilia Diachkov <ilia.diachkov@optimitech.com>
24
25 * elfnn-riscv.c (_bfd_riscv_relax_lui): Delete early exit when
26 diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
27 index 188017d..abf0f6c 100644
28 --- a/bfd/elfnn-riscv.c
29 +++ b/bfd/elfnn-riscv.c
30 @@ -3562,11 +3562,16 @@ _bfd_riscv_relax_lui (bfd *abfd,
31 }
32
33 /* Can we relax LUI to C.LUI? Alignment might move the section forward;
34 - account for this assuming page alignment at worst. */
35 + account for this assuming page alignment at worst. In the presence of
36 + RELRO segment the linker aligns it by one page size, therefore sections
37 + after the segment can be moved more than one page. */
38 +
39 if (use_rvc
40 && ELFNN_R_TYPE (rel->r_info) == R_RISCV_HI20
41 && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval))
42 - && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval + ELF_MAXPAGESIZE)))
43 + && VALID_RVC_LUI_IMM (RISCV_CONST_HIGH_PART (symval)
44 + + (link_info->relro ? 2 * ELF_MAXPAGESIZE
45 + : ELF_MAXPAGESIZE)))
46 {
47 /* Replace LUI with C.LUI if legal (i.e., rd != x0 and rd != x2/sp). */
48 bfd_vma lui = bfd_get_32 (abfd, contents + rel->r_offset);
+101
-0
debian/patches/0003-Add-support-for-SiFive-CLIC-CSRs.patch less more
0 From: Jim Wilson <jimw@sifive.com>
1 Date: Thu, 21 Feb 2019 19:21:23 -0800
2 Subject: Add support for SiFive CLIC CSRs.
3
4 ---
5 gas/testsuite/gas/riscv/priv-reg.d | 4 ++++
6 gas/testsuite/gas/riscv/priv-reg.s | 6 ++++++
7 include/opcode/riscv-opc.h | 19 +++++++++++++++++++
8 3 files changed, 29 insertions(+)
9
10 diff --git a/gas/testsuite/gas/riscv/priv-reg.d b/gas/testsuite/gas/riscv/priv-reg.d
11 index d8ec868..4be85da 100644
12 --- a/gas/testsuite/gas/riscv/priv-reg.d
13 +++ b/gas/testsuite/gas/riscv/priv-reg.d
14 @@ -251,3 +251,7 @@ Disassembly of section .text:
15 [ ]+3c4:[ ]+3bd02573[ ]+csrr[ ]+a0,pmpaddr13
16 [ ]+3c8:[ ]+3be02573[ ]+csrr[ ]+a0,pmpaddr14
17 [ ]+3cc:[ ]+3bf02573[ ]+csrr[ ]+a0,pmpaddr15
18 +[ ]+3d0:[ ]+30702573[ ]+csrr[ ]+a0,mtvt
19 +[ ]+3d4:[ ]+34502573[ ]+csrr[ ]+a0,mnxti
20 +[ ]+3d8:[ ]+34602573[ ]+csrr[ ]+a0,mintstatus
21 +[ ]+3dc:[ ]+34811173[ ]+csrrw[ ]+sp,mscratchcsw,sp
22 diff --git a/gas/testsuite/gas/riscv/priv-reg.s b/gas/testsuite/gas/riscv/priv-reg.s
23 index 72d97f9..76e743c 100644
24 --- a/gas/testsuite/gas/riscv/priv-reg.s
25 +++ b/gas/testsuite/gas/riscv/priv-reg.s
26 @@ -267,3 +267,9 @@
27 csr pmpaddr13
28 csr pmpaddr14
29 csr pmpaddr15
30 +
31 +# CLIC registers
32 + csr mtvt
33 + csr mnxti
34 + csr mintstatus
35 + csrrw sp,mscratchcsw,sp
36 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
37 index f09200c..b5b98f8 100644
38 --- a/include/opcode/riscv-opc.h
39 +++ b/include/opcode/riscv-opc.h
40 @@ -575,6 +575,8 @@
41 #define MASK_CUSTOM3_RD_RS1 0x707f
42 #define MATCH_CUSTOM3_RD_RS1_RS2 0x707b
43 #define MASK_CUSTOM3_RD_RS1_RS2 0x707f
44 +
45 +/* These registers are in priv spec 1.10. */
46 #define CSR_USTATUS 0x0
47 #define CSR_UIE 0x4
48 #define CSR_UTVEC 0x5
49 @@ -796,6 +798,13 @@
50 #define CSR_DCSR 0x7b0
51 #define CSR_DPC 0x7b1
52 #define CSR_DSCRATCH 0x7b2
53 +
54 +/* CLIC registers. */
55 +#define CSR_MTVT 0x307
56 +#define CSR_MNXTI 0x345
57 +#define CSR_MINTSTATUS 0x346
58 +#define CSR_MSCRATCHCSW 0x348
59 +
60 /* These registers are present in priv spec 1.9.1, dropped in 1.10. */
61 #define CSR_HSTATUS 0x200
62 #define CSR_HEDELEG 0x202
63 @@ -1116,6 +1125,7 @@ DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1)
64 DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, MASK_CUSTOM3_RD_RS1_RS2)
65 #endif
66 #ifdef DECLARE_CSR
67 +/* These registers are in priv spec 1.10. */
68 DECLARE_CSR(ustatus, CSR_USTATUS)
69 DECLARE_CSR(uie, CSR_UIE)
70 DECLARE_CSR(utvec, CSR_UTVEC)
71 @@ -1337,6 +1347,13 @@ DECLARE_CSR(tdata3, CSR_TDATA3)
72 DECLARE_CSR(dcsr, CSR_DCSR)
73 DECLARE_CSR(dpc, CSR_DPC)
74 DECLARE_CSR(dscratch, CSR_DSCRATCH)
75 +
76 +/* These registers were added by the fast interrupt path spec. */
77 +DECLARE_CSR(mtvt, CSR_MTVT)
78 +DECLARE_CSR(mnxti, CSR_MNXTI)
79 +DECLARE_CSR(mintstatus, CSR_MINTSTATUS)
80 +DECLARE_CSR(mscratchcsw, CSR_MSCRATCHCSW)
81 +
82 /* These registers are present in priv spec 1.9.1, dropped in 1.10. */
83 DECLARE_CSR(hstatus, CSR_HSTATUS)
84 DECLARE_CSR(hedeleg, CSR_HEDELEG)
85 @@ -1358,6 +1375,7 @@ DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
86 DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
87 DECLARE_CSR(mhcounteren, CSR_MHCOUNTEREN)
88 #endif
89 +
90 #ifdef DECLARE_CSR_ALIAS
91 /* Ubadaddr is 0x043 in 1.9.1, but 0x043 is utval in 1.10. */
92 DECLARE_CSR_ALIAS(ubadaddr, CSR_UTVAL)
93 @@ -1368,6 +1386,7 @@ DECLARE_CSR_ALIAS(sptbr, CSR_SATP)
94 /* Mbadaddr is 0x343 in 1.9.1, but 0x343 is mtval in 1.10. */
95 DECLARE_CSR_ALIAS(mbadaddr, CSR_MTVAL)
96 #endif
97 +
98 #ifdef DECLARE_CAUSE
99 DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
100 DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
+3
-0
debian/patches/series less more
0 0001-RISC-V-Fix-minor-issues-with-FP-csr-instructions.patch
1 0002-RISC-V-Fix-lui-relax-failure-with-relro.patch
2 0003-Add-support-for-SiFive-CLIC-CSRs.patch