Codebase list cpuid / f780b2a
New upstream release. Debian Janitor a year ago
7 changed file(s) with 636 addition(s) and 304 deletion(s). Raw diff Collapse all Expand all
+124
-1
ChangeLog less more
0 Tue Mar 6 2023 Todd Allen <todd.allen@etallen.com>
0 Thu May 5 2023 Todd Allen <todd.allen@etallen.com>
1 * Made new release.
2
3 Fri May 5 2023 Todd Allen <todd.allen@etallen.com>
4 * cpuid.c: Fixed bug in (multi-processing synth) in the recently
5 rewritten decode_mp_synth(). The CPU counts for higher levels were
6 not dividing out counts from lower levels. This is analogous to the
7 way print_apic_synth() subtracts out bit widths from lower levels.
8
9 Fri May 5 2023 Todd Allen <todd.allen@etallen.com>
10 * cpuid.c: Differentiate Core i3-N300 N-Series from ordinary N-Series.
11 (They appear to differ only in branding.)
12
13 Fri Apr 28 2023 Todd Allen <todd.allen@etallen.com>
14 * cpuid.c: Added hypervisor+4/eax bit 21: use hypercalls for MMIO config
15 space I/O, based on LX* (Michael Kelley PCI pass-thru patches). Not
16 documented by Microsoft yet.
17
18 Tue Apr 25 2023 Todd Allen <todd.allen@etallen.com>
19 * cpuid.c: In real_setup(), make inability to switch to CPU 0 no longer
20 a fatal error. It is allowable for CPU 0 to be offlined, just like any
21 other.
22
23 Tue Apr 18 2023 Todd Allen <todd.allen@etallen.com>
24 * cpuid.c: Added (synth) decoding for (0,6),(8,15) Xeon W version of
25 Sapphire Rapids, from instlatx64 sample.
26 * cpuid.c: Corrected (synth) & (uarch synth) for Sapphire Rapids:
27 family is Golden Cove, not Sunny Cove.
28 * cpuid.c: Added (synth) & (uarch synth) Emerald Rapids family:
29 Raptor Cove.
30 * cpuid.c: Added (synth) & (uarch synth) Granite Rapids family:
31 Redwood Cove.
32 * cpuid.c: In decode_uarch_intel, mark Sapphire Rapids, Emerald Rapids
33 & Granite Rapids with core_is_uarch to avoid replicating the name in
34 (synth).
35
36 Sun Apr 16 2023 Todd Allen <todd.allen@etallen.com>
37 * cpuid.c: Added (synth) decoding for (0,6),(10,10),2 Meteor Lake-M B0
38 from Coreboot*.
39
40 Thu Apr 6 2023 Todd Allen <todd.allen@etallen.com>
41 * Made new release.
42
43 Thu Apr 6 2023 Todd Allen <todd.allen@etallen.com>
44 * cpuid.c: Fixed bug in print_apic_synth() when interpreting leaf 0xb
45 and 0x1f bit widths: In fact, they are bit *offsets*, different from
46 the *widths* of leaf 4! So the (APIC width synth) often has been off
47 by 1, and the (APIC synth) PKG_ID & CORE_ID values often have been
48 shifted incorrectly.
49 * cpuid.c: For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of
50 level & previous levels" to reflect this definition.
51 * cpuid.c: In print_apic_synth(), decode_mp_synth(), and
52 print_mp_synth(), support APIC bit fields for the newest 4 topology
53 layers: module, tile, die, die group. And for the mp version, also
54 the older cu & pkg levels.
55 * cpuid.c: In print_apic_synth(), use the extended APIC ID's when
56 available in a variety of leaves.
57 * cpuid.c: In print_apic_synth() & decode_mp_synth(), support leaf 0xb
58 method for AMD/Hygon.
59 * cpuid.c: In decode_mp_synth(), for the 1/0x80000008 method, use the
60 same family-specific technique to differentiate CU's from cores, or
61 cores from threads as in print_apic_synth().
62
63 Tue Apr 4 2023 Todd Allen <todd.allen@etallen.com>
64 * cpuid.c: Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS.
65
66 Fri Mar 31 2023 Todd Allen <todd.allen@etallen.com>
67 * cpuid.c: Added 7/1/edx AMX-COMPLEX instructions.
68 * cpuid.c: Added 7/2/edx UC-lock disable.
69 * cpuid.c: Added 0x10/n/ecx non-contiguous 1s value supported.
70 * cpuid.c: Added 0x1c/ecx event logging supported bitmap.
71 * cpuid.c: Added 0x23/0/ebx decoding.
72
73 Tue Mar 28 2023 Todd Allen <todd.allen@etallen.com>
74 * cpuid.c: Decode 0x80000026/1/ebx core type & native model.
75
76 Tue Mar 28 2023 Todd Allen <todd.allen@etallen.com>
77 * cpuid.c: For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match
78 Intel versions in 7/1/eax.
79 * cpuid.c: For 0x80000022/ecx, shorten description, show bitmask only in
80 hex.
81
82 Tue Mar 28 2023 Smita Koralahalli Channabasappa <Smita.KoralahalliChannabasappa@amd.com>
83 * cpuid.c: Update CPUID utility with new feature bits as documented in
84 the AMD Processor Programming Reference for Family 19h and Model 11h:
85 0x8000000a/edx extended LVT offset fault change
86 0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC,
87 FsGsKernelGsBaseNonSerializing
88 0x80000022/ebx number of available UMC PMCs
89 0x80000022/ecx bitmask representing active UMCs
90
91 Tue Mar 28 2023 Todd Allen <todd.allen@etallen.com>
92 * cpuid.c: Differentiate preliminary (uarch synth) for (0,6),(10,10);
93 (0,6),(10,11); (0,6),(10,12); and (0,6),(11,5) Crestmont Atom cores
94 from their Redwood Cove counterparts.
95 * cpuid.c: Add preliminary (synth) & (uarch synth) for (0,6),(12,6)
96 Lion Cove & Skymont, from LX*.
97
98 Sat Mar 25 2023 Todd Allen <todd.allen@etallen.com>
99 * cpuid.c: Added 12/0/eax SGX ENCLS EUPDATESVN bit.
100 * cpuid.c: Added 0x1f/*/ecx level type value "die group (6)".
101
102 Mon Mar 20 2023 Todd Allen <todd.allen@etallen.com>
103 * cpuid.c: Added (synth) decoding for (0,6),(8,15) Sapphire Rapids D &
104 E0 steppings from coreboot*.
105 * cpuid.c: Improved (synth) decoding for (0,6),(6,10) Scalable 3rd Gen
106 Xeons to Ice Lake-SP. Also, improved decoding for engr samples where
107 the brand string omits Xeon & Bronze/Silver/Gold/Platinum.
108
109 Fri Mar 17 2023 Todd Allen <todd.allen@etallen.com>
110 * cpuid.c: Improved (synth) decoding for (0,6),(11,14) Intel N-Series.
111 * cpuid.c: Differentiate (synth) & (uarch synth) for (0,6),(11,14)
112 Alder Lake-N based on core type, much like for other Alder Lake models.
113 This corrects the cores to Gracemont. As for Golden Cove, perhaps
114 P-cores never will exist for this model but, if they do, they should
115 now be decoded correctly.
116 * cpuid.man: Added 759603: Intel Processor and Intel Core i3 N-Series
117 Datasheet, Volume 1 of 2.
118 * cpuid.c: Updated (synth) decoding for (0,6),(11,15),5 with
119 Raptor Lake-S/HX/P.
120 * cpuid.c: Updated (synth) decoding for (0,6),(11,10) with
121 Raptor Lake-H/U/P.
122
123 Mon Mar 6 2023 Todd Allen <todd.allen@etallen.com>
1124 * Made new release.
2125
3126 Sun Mar 5 2023 Todd Allen <todd.allen@etallen.com>
+9
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FAMILY.NOTES less more
5252 12000 Series : Golden Cove : new architecture (Alder Lake) (Intel 7) LGA 1700 4th Sapphire Rapids Eagle Stream LGA 4677
5353 13000 Series : Raptor Cove : modified Golden Cove (Raptor Lake) (Intel 7) LGA 1700 5th Emerald Rapids (H2'23) Eagle Stream LGA 4677
5454 ? 14000 Series : Redwood Cove : modified Raptor Cove (Meteor Lake) (Intel 4) (H2'23) 6th Granite Rapids (2024) Birch Stream LGA 7529
55 ---------------------------------------------------------------------------------------------------------------------------------------------------------------- vvv Royal Core ? vvv
5556 ? 15000 Series : Lion Cove : (Arrow Lake (Intel 20A)) (H2'24) <--???--> 7th Diamond Rapids (2025) Mountain Stream
56 ---------------------------------------------------------------------------------------------------------------------------------------------------------------- vvv Royal Core ? vvv
57 ? 16000 Series : ? : (Lunar Lake (Intel 18A)) (2024+)
58 ----------------------------------------------------------------------------------------------------------------------------------------------------------------
59 ? : Panther Cove : (Panther Lake (Intel 18A)) (2026)
60 ? : Panther Cove : (Nova Lake (Intel 18A)) (2026)
57 ? 16000 Series : ? : (Lunar Lake (Intel ???)) (2024+)
58 ----------------------------------------------------------------------------------------------------------------------------------------------------------------
59 ? : Panther Cove : (Panther Lake (Intel ???)) (2026)
60 ? : Panther Cove : (Nova Lake (Intel ???)) (2026)
6161 ----------------------------------------------------------------------------------------------------------------------------------------------------------------
6262
6363 * = I'm not treating this as a distinct uarch, but just as a core within its
6464 parent uarch, Kaby Lake
65
66 UNCERTAINTY: Sometimes Redwood Cove is called Ocean Cove.
6765
6866 Alder Lake variants: -S desktop, -P = mobile, -M = low-power, -L = atom replacement, -N educational
6967
248246 Zen 2 (7nm) 3000: Castle Peak 2nd Gen: Rome V2000: Grey Hawk
249247 (update) 3000: Matisse 4000: Renoir
250248 5000: Lucienne
251 Van Gogh (?)
252249 7000: Mendocino
250 Van Gogh
253251 Zen 3 (7nm) 5000: Vermeer 5000: Chagall 5000: Cezanne/Barcelo 3rd Gen: Milan
254252 6000: Rembrandt
255253 Trento (Frontier super)
259257 ------------------------------------------------------------------------------------------------------------------------------------------------------------------
260258 Siena(edge)
261259 Zen 4c (5nm) Bergamo(cloud)
262 Zen 5 Granite Ridge Turin (>= late 2023)
260 Zen 5 Granite Ridge Turin (>= H1'2024)
261 Sorano(edge)
262 Zen 6 Venice (>= 2025)
263263 ------------------------------------------------------------------------------------------------------------------------------------------------------------------
264264
265265 Bobcat-Puma(2014):
+1
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Makefile less more
77 INSTALL_STRIP=-s
88
99 PACKAGE=cpuid
10 VERSION=20230306
10 VERSION=20230505
1111 RELEASE=1
1212
1313 PROG=$(PACKAGE)
+493
-287
cpuid.c less more
368368 #define FALLBACK(...) \
369369 else __VA_ARGS__
370370
371 // This enum combines the topological layers from both Intel & AMD.
372 enum Cotopo {
373 Smt,
374 Core,
375 Cu,
376 Module,
377 Tile,
378 Die,
379 DieGrp,
380 Pkg,
381 NumCotopos,
382 Invalid = NumCotopos,
383 };
384
385 #define V2_TOPO_NUM 7
386
387 static unsigned int v2TopoToCotopo[V2_TOPO_NUM]
388 = { /* invalid (0) => */ Invalid,
389 /* thread (1) => */ Smt,
390 /* core (2) => */ Core,
391 /* module (3) => */ Module,
392 /* tile (4) => */ Tile,
393 /* die (5) => */ Die,
394 /* die group (6) => */ DieGrp };
395
371396 typedef struct {
372397 vendor_t vendor;
373398 boolean saw_4;
374399 boolean saw_b;
375400 boolean saw_1f;
401 boolean saw_8000001e;
376402 unsigned int val_0_eax;
377403 unsigned int val_1_eax;
378404 unsigned int val_1_ebx;
381407 unsigned int val_4_eax;
382408 unsigned int val_b_eax[2];
383409 unsigned int val_b_ebx[2];
410 unsigned int val_b_edx;
384411 unsigned int val_1a_0_eax;
385 unsigned int val_1f_eax[6];
386 unsigned int val_1f_ebx[6];
387 unsigned int val_1f_ecx[6];
412 unsigned int val_1f_eax[V2_TOPO_NUM];
413 unsigned int val_1f_ebx[V2_TOPO_NUM];
414 unsigned int val_1f_ecx[V2_TOPO_NUM];
415 unsigned int val_1f_edx;
388416 unsigned int val_80000001_eax;
389417 unsigned int val_80000001_ebx;
390418 unsigned int val_80000001_ecx;
391419 unsigned int val_80000001_edx;
392420 unsigned int val_80000008_ecx;
421 unsigned int val_8000001e_eax;
393422 unsigned int val_8000001e_ebx;
394423 unsigned int transmeta_proc_rev;
395424 char brand[48+1];
400429
401430 struct mp {
402431 const char* method;
403 unsigned int cores;
404 unsigned int hyperthreads;
432 unsigned int count[NumCotopos];
405433 } mp;
406434
407435 struct br {
504532 } code_stash_t;
505533
506534 #define NIL_STASH { VENDOR_UNKNOWN, \
507 FALSE, FALSE, FALSE, \
535 FALSE, FALSE, FALSE, FALSE, \
508536 0, 0, 0, 0, 0, 0, \
509537 { 0, 0 }, \
510538 { 0, 0 }, \
511539 0, \
512 { 0, 0, 0, 0, 0, 0 }, \
513 { 0, 0, 0, 0, 0, 0 }, \
514 { 0, 0, 0, 0, 0, 0 }, \
515 0, 0, 0, 0, 0, 0, 0, \
540 0, \
541 { 0, 0, 0, 0, 0, 0, 0 }, \
542 { 0, 0, 0, 0, 0, 0, 0 }, \
543 { 0, 0, 0, 0, 0, 0, 0 }, \
544 0, \
545 0, 0, 0, 0, 0, 0, 0, 0, \
516546 "", "", "", "", \
517547 HYPERVISOR_UNKNOWN, \
518 { NULL, -1, -1 }, \
548 { NULL, { 0, 0, 0, 0, 0, 0, 0, 0 } }, \
519549 { FALSE, \
520550 { FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \
521551 FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \
17671797 /* Dual-Core Xeon Processor 5100 (Woodcrest B1) pre-production,
17681798 distinguished from Core 2 Duo (Conroe B1) */
17691799 #define QW (dG && stash->br.generic \
1770 && (stash->mp.cores == 4 \
1771 || (stash->mp.cores == 2 && stash->mp.hyperthreads == 2)))
1800 && (stash->mp.count[Core] == 4 \
1801 || (stash->mp.count[Core] == 2 && stash->mp.count[Smt] == 2)))
17721802 /* Core Duo (Yonah), distinguished from Core Solo (Yonah) */
1773 #define DG (dG && stash->mp.cores == 2)
1803 #define DG (dG && stash->mp.count[Core] == 2)
17741804 /* Core 2 Quad, distinguished from Core 2 Duo */
1775 #define Qc (dc && stash->mp.cores == 4)
1805 #define Qc (dc && stash->mp.count[Core] == 4)
17761806 /* Core 2 Extreme (Conroe B1), distinguished from Core 2 Duo (Conroe B1) */
17771807 #define XE (dc && strstr(stash->brand, " E6800") != NULL)
17781808 /* Quad-Core Xeon, distinguished from Xeon; and
17791809 Xeon Processor 3300, distinguished from Xeon Processor 3100 */
1780 #define sQ (sX && stash->mp.cores == 4)
1810 #define sQ (sX && stash->mp.count[Core] == 4)
17811811 /* Xeon Processor 7000, distinguished from Xeon */
17821812 #define IS_VMX(val_1_ecx) (BIT_EXTRACT_LE((val_1_ecx), 5, 6))
17831813 #define s7 (sX && IS_VMX(stash->val_1_ecx))
18041834 #define Hz (is_intel && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x00)
18051835 #define Ha (is_intel && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x20)
18061836 #define Hc (is_intel && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x40)
1837 /* Hybrid special cases where "Core" implies a different branding than usual,
1838 such as the Core i3 N-Series */
1839 #define Ia (is_intel && stash->br.core && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x20)
1840 #define Ic (is_intel && stash->br.core && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x40)
18071841
18081842 /*
18091843 ** AMD major queries:
20912125 //
20922126
20932127 START;
2094 F ( 0, 4, *f = "i486"); // *p depends on core
2095 FM ( 0, 5, 0, 0, *f = "P5", *p = ".8um");
2096 FM ( 0, 5, 0, 1, *f = "P5", *p = ".8um");
2128 F ( 0, 4, *f = "i486"); // *p depends on core
2129 FM ( 0, 5, 0, 0, *f = "P5", *p = ".8um");
2130 FM ( 0, 5, 0, 1, *f = "P5", *p = ".8um");
20972131 FM ( 0, 5, 0, 2, *f = "P5");
2098 FM ( 0, 5, 0, 3, *f = "P5", *p = ".6um");
2132 FM ( 0, 5, 0, 3, *f = "P5", *p = ".6um");
20992133 FM ( 0, 5, 0, 4, *f = "P5 MMX");
21002134 FM ( 0, 5, 0, 7, *f = "P5 MMX");
2101 FM ( 0, 5, 0, 8, *f = "P5 MMX", *p = ".25um");
2135 FM ( 0, 5, 0, 8, *f = "P5 MMX", *p = ".25um");
21022136 FM ( 0, 5, 0, 9, *f = "P5 MMX");
21032137 FM ( 0, 6, 0, 0, *f = "P6 Pentium II");
2104 FM ( 0, 6, 0, 1, *f = "P6 Pentium II"); // *p depends on core
2138 FM ( 0, 6, 0, 1, *f = "P6 Pentium II"); // *p depends on core
21052139 FM ( 0, 6, 0, 2, *f = "P6 Pentium II");
2106 FM ( 0, 6, 0, 3, *f = "P6 Pentium II", *p = ".35um");
2140 FM ( 0, 6, 0, 3, *f = "P6 Pentium II", *p = ".35um");
21072141 FM ( 0, 6, 0, 4, *f = "P6 Pentium II");
2108 FM ( 0, 6, 0, 5, *f = "P6 Pentium II", *p = ".25um");
2109 FM ( 0, 6, 0, 6, *f = "P6 Pentium II", *p = "L2 cache");
2110 FM ( 0, 6, 0, 7, *f = "P6 Pentium III", *p = ".25um");
2111 FM ( 0, 6, 0, 8, *f = "P6 Pentium III", *p = ".18um");
2112 FM ( 0, 6, 0, 9, *f = "P6 Pentium M", *p = ".13um");
2113 FM ( 0, 6, 0,10, *f = "P6 Pentium III", *p = ".18um");
2114 FM ( 0, 6, 0,11, *f = "P6 Pentium III", *p = ".13um");
2115 FM ( 0, 6, 0,13, *u = "Dothan", *f = "P6 Pentium M"); // *p depends on core
2116 FM ( 0, 6, 0,14, *u = "Yonah", *f = "P6 Pentium M", *p = "65nm");
2117 FM ( 0, 6, 0,15, *u = "Merom", *f = "Core", *p = "65nm");
2118 FM ( 0, 6, 1, 5, *u = "Dothan", *f = "P6 Pentium M", *p = "90nm");
2119 FM ( 0, 6, 1, 6, *u = "Merom", *f = "Core", *p = "65nm");
2120 FM ( 0, 6, 1, 7, *u = "Penryn", *f = "Core", *p = "45nm");
2121 FM ( 0, 6, 1,10, *u = "Nehalem", *f = "Nehalem", *p = "45nm");
2122 FM ( 0, 6, 1,12, *u = "Bonnell", *p = "45nm");
2123 FM ( 0, 6, 1,13, *u = "Penryn", *f = "Core", *p = "45nm");
2124 FM ( 0, 6, 1,14, *u = "Nehalem", *f = "Nehalem", *p = "45nm");
2125 FM ( 0, 6, 1,15, *u = "Nehalem", *f = "Nehalem", *p = "45nm");
2126 FM ( 0, 6, 2, 5, *u = "Westmere", *f = "shrink of Nehalem", *p = "32nm");
2127 FM ( 0, 6, 2, 6, *u = "Bonnell", *p = "45nm");
2128 FM ( 0, 6, 2, 7, *u = "Saltwell", *p = "32nm");
2129 FM ( 0, 6, 2,10, *u = "Sandy Bridge", *ciu = TRUE, *f = "Sandy Bridge", *p = "32nm");
2130 FM ( 0, 6, 2,12, *u = "Westmere", *f = "shrink of Nehalem", *p = "32nm");
2131 FM ( 0, 6, 2,13, *u = "Sandy Bridge", *ciu = TRUE, *f = "Sandy Bridge", *p = "32nm");
2132 FM ( 0, 6, 2,14, *u = "Nehalem", *f = "Nehalem", *p = "45nm");
2133 FM ( 0, 6, 2,15, *u = "Westmere", *f = "shrink of Nehalem", *p = "32nm");
2134 FM ( 0, 6, 3, 5, *u = "Saltwell", *p = "14nm");
2135 FM ( 0, 6, 3, 6, *u = "Saltwell", *p = "32nm");
2136 FM ( 0, 6, 3, 7, *u = "Silvermont", *p = "22nm");
2137 FM ( 0, 6, 3,10, *u = "Ivy Bridge", *ciu = TRUE, *f = "shrink of Sandy Bridge", *p = "22nm");
2138 FM ( 0, 6, 3,12, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm");
2139 FM ( 0, 6, 3,13, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm");
2140 FM ( 0, 6, 3,14, *u = "Ivy Bridge", *ciu = TRUE, *f = "shrink of Sandy Bridge", *p = "22nm");
2141 FM ( 0, 6, 3,15, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm");
2142 FM ( 0, 6, 4, 5, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm");
2143 FM ( 0, 6, 4, 6, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm");
2144 FM ( 0, 6, 4, 7, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm");
2145 FM ( 0, 6, 4,10, *u = "Silvermont", *p = "22nm"); // no docs, but /proc/cpuinfo seen in wild
2146 FM ( 0, 6, 4,12, *u = "Airmont", *p = "14nm");
2147 FM ( 0, 6, 4,13, *u = "Silvermont", *p = "22nm");
2148 FMS ( 0, 6, 4,14, 8, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+");
2149 FM ( 0, 6, 4,14, *u = "Skylake", *ciu = TRUE, *f = "Skylake", *p = "14nm");
2150 FM ( 0, 6, 4,15, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm");
2151 FMQ ( 0, 6, 5, 5, iM, *u = "Jintide Gen1", *ciu = TRUE); // undocumented; only instlatx64 example
2152 FMS ( 0, 6, 5, 5, 6, *u = "Cascade Lake", *ciu = TRUE, *f = "optim of Skylake", *p = "14nm++"); // no docs, but example from Greg Stewart
2153 FMS ( 0, 6, 5, 5, 7, *u = "Cascade Lake", *ciu = TRUE, *f = "optim of Skylake", *p = "14nm++");
2154 FMS ( 0, 6, 5, 5, 10, *u = "Cooper Lake", *ciu = TRUE, *f = "optim of Cascade Lake, optim of Skylake", *p = "14nm++");
2155 FM ( 0, 6, 5, 5, *u = "Skylake", *ciu = TRUE, *f = "Skylake", *p = "14nm");
2156 FM ( 0, 6, 5, 6, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm");
2157 FM ( 0, 6, 5, 7, *u = "Knights Landing", *ciu = TRUE, *p = "14nm");
2158 FM ( 0, 6, 5,10, *u = "Silvermont", *p = "22nm"); // no spec update; only MSR_CPUID_table* so far
2159 FM ( 0, 6, 5,12, *u = "Goldmont", *p = "14nm"); // no spec update for Atom; only MSR_CPUID_table* so far
2160 FM ( 0, 6, 5,13, *u = "Silvermont", *p = "22nm"); // no spec update; only MSR_CPUID_table* so far
2161 FMS ( 0, 6, 5,14, 8, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+");
2162 FM ( 0, 6, 5,14, *u = "Skylake", *ciu = TRUE, *f = "Skylake", *p = "14nm");
2163 FM ( 0, 6, 5,15, *u = "Goldmont", *p = "14nm");
2164 FM ( 0, 6, 6, 6, *u = "Palm Cove", *f = "Palm Cove", *p = "10nm"); // no spec update; only MSR_CPUID_table* so far
2165 FM ( 0, 6, 6, 7, *u = "Palm Cove", *f = "Palm Cove", *p = "10nm"); // DPTF*
2166 FM ( 0, 6, 6,10, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+");
2167 FM ( 0, 6, 6,12, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // no spec update; only MSR_CPUID_table* so far; DPTF* claims this is Meteor Lake S => Redwood Cove
2168 FM ( 0, 6, 6,14, *u = "Airmont", *p = "14nm"); // no spec update; only Intel's "Retpoline: A Branch Target Injection Mitigation"
2169 FM ( 0, 6, 7, 5, *u = "Airmont", *p = "14nm"); // no spec update; whispers & rumors
2170 FM ( 0, 6, 7,10, *u = "Goldmont Plus", *p = "14nm");
2171 FM ( 0, 6, 7,13, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // no spec update; only MSR_CPUID_table* so far
2172 FM ( 0, 6, 7,14, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+");
2173 FM ( 0, 6, 8, 5, *u = "Knights Mill", *ciu = TRUE, *p = "14nm"); // no spec update; only MSR_CPUID_table* so far
2174 FM ( 0, 6, 8, 6, *u = "Tremont", *p = "10nm"); // LX*
2175 FMQ ( 0, 6, 8,10, Ha, *u = "Tremont", *p = "10nm"); // no spec update; LX*
2176 FMQ ( 0, 6, 8,10, Hc, *u = "Sunny Cove", *p = "10nm"); // no spec update; LX*
2177 FM ( 0, 6, 8,12, *u = "Willow Cove", *f = "optim of Sunny Cove", *p = "10nm++"); // no spec update; only MSR_CPUID_table* so far
2178 FM ( 0, 6, 8,13, *u = "Willow Cove", *f = "optim of Sunny Cove", *p = "10nm++"); // no spec update; only MSR_CPUID_table* so far
2179 FM ( 0, 6, 8,14, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+/14nm++");
2180 FM ( 0, 6, 8,15, *u = "Sapphire Rapids", *f = "Sunny Cove", *p = "10nm+"); // LX*
2181 FM ( 0, 6, 9, 6, *u = "Tremont", *p = "10nm"); // LX*
2182 FMQ ( 0, 6, 9, 7, Ha, *u = "Gracemont", *p = "Intel 7");
2183 FMQ ( 0, 6, 9, 7, Hc, *u = "Golden Cove", *p = "Intel 7");
2184 FMQ ( 0, 6, 9, 7, Hz, *u = "Golden Cove", *p = "Intel 7");
2185 FMQ ( 0, 6, 9,10, Ha, *u = "Gracemont", *p = "Intel 7"); // Coreboot*
2186 FMQ ( 0, 6, 9,10, Hc, *u = "Golden Cove", *p = "Intel 7"); // Coreboot*
2187 FM ( 0, 6, 9,12, *u = "Tremont", *p = "10nm"); // LX*
2188 FM ( 0, 6, 9,13, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // LX*
2189 FMS ( 0, 6, 9,14, 9, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+");
2190 FMS ( 0, 6, 9,14, 10, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++");
2191 FMS ( 0, 6, 9,14, 11, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++");
2192 FMS ( 0, 6, 9,14, 12, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++");
2193 FMS ( 0, 6, 9,14, 13, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++");
2194 FM ( 0, 6, 9,14, *u = "Kaby Lake / Coffee Lake", *f = "optim of Skylake", *p = "14nm+/14nm++");
2195 FM ( 0, 6, 9,15, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA
2196 FM ( 0, 6, 10, 5, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+++"); // LX*
2197 FM ( 0, 6, 10, 6, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+++"); // no spec update; only instlatx64 example
2198 FM ( 0, 6, 10, 7, *u = "Cypress Cove", *f = "backport of Sunny Cove", *p = "14nm+++"); // LX*
2199 FM ( 0, 6, 10, 8, *u = "Cypress Cove", *f = "backport of Sunny Cove", *p = "14nm+++"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA
2200 FM ( 0, 6, 10,10, *u = "Redwood Cove", *f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; DPTF*, LX* (but -L); (engr?) sample via instlatx64 from Komachi_ENSAKA
2201 FM ( 0, 6, 10,11, *u = "Redwood Cove", *f = "Golden Cove", *p = "Intel 4"); // DPTF*
2202 FM ( 0, 6, 10,12, *u = "Redwood Cove", *f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA
2203 FM ( 0, 6, 10,13, *u = "Granite Rapids", *f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA
2204 FM ( 0, 6, 10,14, *u = "Granite Rapids", *f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; LX*
2205 FM ( 0, 6, 10,15, *u = "Sierra Forest"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA
2206 FM ( 0, 6, 11, 5, *u = "Redwood Cove", *f = "Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*
2207 FM ( 0, 6, 11, 6, *u = "Crestmont", *p = "Intel 7"); // MSR_CPUID_table*; LX*; (although assumption that Grand Ridge is Crestmont)
2208 FMQ ( 0, 6, 11, 7, Ha, *u = "Gracemont", *p = "Intel 7"); // MSR_CPUID_table*; LX*; DPTF*
2209 FMQ ( 0, 6, 11, 7, Hc, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*; LX*; DPTF*
2210 FMQ ( 0, 6, 11,10, Ha, *u = "Gracemont", *p = "Intel 7"); // DPTF*; Coreboot*
2211 FMQ ( 0, 6, 11,10, Hc, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // DPTF*; Coreboot*
2212 // (0,6),(11,13) is reserved for whatever not-yet-named uarch underpins
2213 // Lunar Lake
2214 FM ( 0, 6, 11,14, *u = "Golden Cove", *p = "Intel 7"); // Coreboot*, PDTF*
2215 FMQ ( 0, 6, 11,15, Ha, *u = "Gracemont", *p = "Intel 7"); // MSR_CPUID_table*
2216 FMQ ( 0, 6, 11,15, Hc, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*
2217 FM ( 0, 6, 12,15, *u = "Emerald Rapids", *p = "Intel 7"); // MSR_CPUID_table*; LX*
2142 FM ( 0, 6, 0, 5, *f = "P6 Pentium II", *p = ".25um");
2143 FM ( 0, 6, 0, 6, *f = "P6 Pentium II", *p = "L2 cache");
2144 FM ( 0, 6, 0, 7, *f = "P6 Pentium III", *p = ".25um");
2145 FM ( 0, 6, 0, 8, *f = "P6 Pentium III", *p = ".18um");
2146 FM ( 0, 6, 0, 9, *f = "P6 Pentium M", *p = ".13um");
2147 FM ( 0, 6, 0,10, *f = "P6 Pentium III", *p = ".18um");
2148 FM ( 0, 6, 0,11, *f = "P6 Pentium III", *p = ".13um");
2149 FM ( 0, 6, 0,13, *u = "Dothan", *f = "P6 Pentium M"); // *p depends on core
2150 FM ( 0, 6, 0,14, *u = "Yonah", *f = "P6 Pentium M", *p = "65nm");
2151 FM ( 0, 6, 0,15, *u = "Merom", *f = "Core", *p = "65nm");
2152 FM ( 0, 6, 1, 5, *u = "Dothan", *f = "P6 Pentium M", *p = "90nm");
2153 FM ( 0, 6, 1, 6, *u = "Merom", *f = "Core", *p = "65nm");
2154 FM ( 0, 6, 1, 7, *u = "Penryn", *f = "Core", *p = "45nm");
2155 FM ( 0, 6, 1,10, *u = "Nehalem", *f = "Nehalem", *p = "45nm");
2156 FM ( 0, 6, 1,12, *u = "Bonnell", *p = "45nm");
2157 FM ( 0, 6, 1,13, *u = "Penryn", *f = "Core", *p = "45nm");
2158 FM ( 0, 6, 1,14, *u = "Nehalem", *f = "Nehalem", *p = "45nm");
2159 FM ( 0, 6, 1,15, *u = "Nehalem", *f = "Nehalem", *p = "45nm");
2160 FM ( 0, 6, 2, 5, *u = "Westmere", *f = "shrink of Nehalem", *p = "32nm");
2161 FM ( 0, 6, 2, 6, *u = "Bonnell", *p = "45nm");
2162 FM ( 0, 6, 2, 7, *u = "Saltwell", *p = "32nm");
2163 FM ( 0, 6, 2,10, *u = "Sandy Bridge", *ciu = TRUE, *f = "Sandy Bridge", *p = "32nm");
2164 FM ( 0, 6, 2,12, *u = "Westmere", *f = "shrink of Nehalem", *p = "32nm");
2165 FM ( 0, 6, 2,13, *u = "Sandy Bridge", *ciu = TRUE, *f = "Sandy Bridge", *p = "32nm");
2166 FM ( 0, 6, 2,14, *u = "Nehalem", *f = "Nehalem", *p = "45nm");
2167 FM ( 0, 6, 2,15, *u = "Westmere", *f = "shrink of Nehalem", *p = "32nm");
2168 FM ( 0, 6, 3, 5, *u = "Saltwell", *p = "14nm");
2169 FM ( 0, 6, 3, 6, *u = "Saltwell", *p = "32nm");
2170 FM ( 0, 6, 3, 7, *u = "Silvermont", *p = "22nm");
2171 FM ( 0, 6, 3,10, *u = "Ivy Bridge", *ciu = TRUE, *f = "shrink of Sandy Bridge", *p = "22nm");
2172 FM ( 0, 6, 3,12, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm");
2173 FM ( 0, 6, 3,13, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm");
2174 FM ( 0, 6, 3,14, *u = "Ivy Bridge", *ciu = TRUE, *f = "shrink of Sandy Bridge", *p = "22nm");
2175 FM ( 0, 6, 3,15, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm");
2176 FM ( 0, 6, 4, 5, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm");
2177 FM ( 0, 6, 4, 6, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm");
2178 FM ( 0, 6, 4, 7, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm");
2179 FM ( 0, 6, 4,10, *u = "Silvermont", *p = "22nm"); // no docs, but /proc/cpuinfo seen in wild
2180 FM ( 0, 6, 4,12, *u = "Airmont", *p = "14nm");
2181 FM ( 0, 6, 4,13, *u = "Silvermont", *p = "22nm");
2182 FMS ( 0, 6, 4,14, 8, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+");
2183 FM ( 0, 6, 4,14, *u = "Skylake", *ciu = TRUE, *f = "Skylake", *p = "14nm");
2184 FM ( 0, 6, 4,15, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm");
2185 FMQ ( 0, 6, 5, 5, iM, *u = "Jintide Gen1", *ciu = TRUE); // undocumented; only instlatx64 example
2186 FMS ( 0, 6, 5, 5, 6, *u = "Cascade Lake", *ciu = TRUE, *f = "optim of Skylake", *p = "14nm++"); // no docs, but example from Greg Stewart
2187 FMS ( 0, 6, 5, 5, 7, *u = "Cascade Lake", *ciu = TRUE, *f = "optim of Skylake", *p = "14nm++");
2188 FMS ( 0, 6, 5, 5, 10, *u = "Cooper Lake", *ciu = TRUE, *f = "optim of Cascade Lake, optim of Skylake", *p = "14nm++");
2189 FM ( 0, 6, 5, 5, *u = "Skylake", *ciu = TRUE, *f = "Skylake", *p = "14nm");
2190 FM ( 0, 6, 5, 6, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm");
2191 FM ( 0, 6, 5, 7, *u = "Knights Landing", *ciu = TRUE, *p = "14nm");
2192 FM ( 0, 6, 5,10, *u = "Silvermont", *p = "22nm"); // no spec update; only MSR_CPUID_table* so far
2193 FM ( 0, 6, 5,12, *u = "Goldmont", *p = "14nm"); // no spec update for Atom; only MSR_CPUID_table* so far
2194 FM ( 0, 6, 5,13, *u = "Silvermont", *p = "22nm"); // no spec update; only MSR_CPUID_table* so far
2195 FMS ( 0, 6, 5,14, 8, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+");
2196 FM ( 0, 6, 5,14, *u = "Skylake", *ciu = TRUE, *f = "Skylake", *p = "14nm");
2197 FM ( 0, 6, 5,15, *u = "Goldmont", *p = "14nm");
2198 FM ( 0, 6, 6, 6, *u = "Palm Cove", *f = "Palm Cove", *p = "10nm"); // no spec update; only MSR_CPUID_table* so far
2199 FM ( 0, 6, 6, 7, *u = "Palm Cove", *f = "Palm Cove", *p = "10nm"); // DPTF*
2200 FM ( 0, 6, 6,10, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+");
2201 FM ( 0, 6, 6,12, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // no spec update; only MSR_CPUID_table* so far; DPTF* claims this is Meteor Lake S => Redwood Cove
2202 FM ( 0, 6, 6,14, *u = "Airmont", *p = "14nm"); // no spec update; only Intel's "Retpoline: A Branch Target Injection Mitigation"
2203 FM ( 0, 6, 7, 5, *u = "Airmont", *p = "14nm"); // no spec update; whispers & rumors
2204 FM ( 0, 6, 7,10, *u = "Goldmont Plus", *p = "14nm");
2205 FM ( 0, 6, 7,13, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // no spec update; only MSR_CPUID_table* so far
2206 FM ( 0, 6, 7,14, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+");
2207 FM ( 0, 6, 8, 5, *u = "Knights Mill", *ciu = TRUE, *p = "14nm"); // no spec update; only MSR_CPUID_table* so far
2208 FM ( 0, 6, 8, 6, *u = "Tremont", *p = "10nm"); // LX*
2209 FMQ ( 0, 6, 8,10, Ha, *u = "Tremont", *p = "10nm"); // no spec update; LX*
2210 FMQ ( 0, 6, 8,10, Hc, *u = "Sunny Cove", *p = "10nm"); // no spec update; LX*
2211 FM ( 0, 6, 8,12, *u = "Willow Cove", *f = "optim of Sunny Cove", *p = "10nm++"); // no spec update; only MSR_CPUID_table* so far
2212 FM ( 0, 6, 8,13, *u = "Willow Cove", *f = "optim of Sunny Cove", *p = "10nm++"); // no spec update; only MSR_CPUID_table* so far
2213 FM ( 0, 6, 8,14, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+/14nm++");
2214 FM ( 0, 6, 8,15, *u = "Sapphire Rapids", *ciu = TRUE, *f = "Golden Cove", *p = "Intel 7"); // LX*
2215 FM ( 0, 6, 9, 6, *u = "Tremont", *p = "10nm"); // LX*
2216 FMQ ( 0, 6, 9, 7, Ha, *u = "Gracemont", *p = "Intel 7");
2217 FMQ ( 0, 6, 9, 7, Hc, *u = "Golden Cove", *p = "Intel 7");
2218 FMQ ( 0, 6, 9, 7, Hz, *u = "Golden Cove", *p = "Intel 7");
2219 FMQ ( 0, 6, 9,10, Ha, *u = "Gracemont", *p = "Intel 7"); // Coreboot*
2220 FMQ ( 0, 6, 9,10, Hc, *u = "Golden Cove", *p = "Intel 7"); // Coreboot*
2221 FM ( 0, 6, 9,12, *u = "Tremont", *p = "10nm"); // LX*
2222 FM ( 0, 6, 9,13, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // LX*
2223 FMS ( 0, 6, 9,14, 9, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+");
2224 FMS ( 0, 6, 9,14, 10, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++");
2225 FMS ( 0, 6, 9,14, 11, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++");
2226 FMS ( 0, 6, 9,14, 12, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++");
2227 FMS ( 0, 6, 9,14, 13, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++");
2228 FM ( 0, 6, 9,14, *u = "Kaby Lake / Coffee Lake", *f = "optim of Skylake", *p = "14nm+/14nm++");
2229 FM ( 0, 6, 9,15, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA
2230 FM ( 0, 6, 10, 5, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+++"); // LX*
2231 FM ( 0, 6, 10, 6, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+++"); // no spec update; only instlatx64 example
2232 FM ( 0, 6, 10, 7, *u = "Cypress Cove", *f = "backport of Sunny Cove", *p = "14nm+++"); // LX*
2233 FM ( 0, 6, 10, 8, *u = "Cypress Cove", *f = "backport of Sunny Cove", *p = "14nm+++"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA
2234 FMQ ( 0, 6, 10,10, Ha, *u = "Crestmont", *p = "Intel 4"); // MSR_CPUID_table*; DPTF*, LX* (but -L); (engr?) sample via instlatx64 from Komachi_ENSAKA
2235 FMQ ( 0, 6, 10,10, Hc, *u = "Redwood Cove", *f = "shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; DPTF*, LX* (but -L); (engr?) sample via instlatx64 from Komachi_ENSAKA
2236 FMQ ( 0, 6, 10,11, Ha, *u = "Crestmont", *p = "Intel 4"); // DPTF*
2237 FMQ ( 0, 6, 10,11, Hc, *u = "Redwood Cove", *f = "shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // DPTF*
2238 FMQ ( 0, 6, 10,12, Ha, *u = "Crestmont", *p = "Intel 4"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA
2239 FMQ ( 0, 6, 10,12, Hc, *u = "Redwood Cove", *f = "shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA
2240 FM ( 0, 6, 10,13, *u = "Granite Rapids", *ciu = TRUE, *f = "Redwood Cove, shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA
2241 FM ( 0, 6, 10,14, *u = "Granite Rapids", *ciu = TRUE, *f = "Redwood Cove, shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; LX*
2242 FM ( 0, 6, 10,15, *u = "Sierra Forest"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA
2243 FMQ ( 0, 6, 11, 5, Ha, *u = "Crestmont", *p = "Intel 4"); // MSR_CPUID_table*
2244 FMQ ( 0, 6, 11, 5, Hc, *u = "Redwood Cove", *f = "optim of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*
2245 FM ( 0, 6, 11, 6, *u = "Crestmont", *p = "Intel 7"); // MSR_CPUID_table*; LX*; (although assumption that Grand Ridge is Crestmont)
2246 FMQ ( 0, 6, 11, 7, Ha, *u = "Gracemont", *p = "Intel 7"); // MSR_CPUID_table*; LX*; DPTF*
2247 FMQ ( 0, 6, 11, 7, Hc, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*; LX*; DPTF*
2248 FMQ ( 0, 6, 11,10, Ha, *u = "Gracemont", *p = "Intel 7"); // DPTF*; Coreboot*
2249 FMQ ( 0, 6, 11,10, Hc, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // DPTF*; Coreboot*
2250 // (0,6),(11,13) is reserved for whatever not-yet-named uarch underpins Lunar Lake
2251 FMQ ( 0, 6, 11,14, Ha, *u = "Gracemont", *p = "Intel 7");
2252 FMQ ( 0, 6, 11,14, Hc, *u = "Golden Cove", *p = "Intel 7"); // possibly no P-cores ever for this model
2253 FMQ ( 0, 6, 11,15, Ha, *u = "Gracemont", *p = "Intel 7"); // MSR_CPUID_table*
2254 FMQ ( 0, 6, 11,15, Hc, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*
2255 FMQ ( 0, 6, 12, 6, Ha, *u = "Skymont", *p = "Intel 20A"); // LX*
2256 FMQ ( 0, 6, 12, 6, Hc, *u = "Lion Cove", *p = "Intel 20A"); // LX*
2257 FM ( 0, 6, 12,15, *u = "Emerald Rapids", *ciu = TRUE, *f = "Raptor Cove, optim of Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*; LX*
22182258 F ( 0, 7, *u = "Itanium");
2219 FM ( 0,11, 0, 0, *u = "Knights Ferry", *ciu = TRUE, *f = "K1OM", *p = "45nm"); // found only on en.wikichip.org
2220 FM ( 0,11, 0, 1, *u = "Knights Corner", *ciu = TRUE, *f = "K1OM", *p = "22nm");
2221 FM ( 0,15, 0, 0, *u = "Willamette", *f = "Netburst", *p = ".18um");
2222 FM ( 0,15, 0, 1, *u = "Willamette", *f = "Netburst", *p = ".18um");
2223 FM ( 0,15, 0, 2, *u = "Northwood", *f = "Netburst", *p = ".13um");
2224 FM ( 0,15, 0, 3, *u = "Prescott", *f = "Netburst", *p = "90nm");
2225 FM ( 0,15, 0, 4, *u = "Prescott", *f = "Netburst", *p = "90nm");
2226 FM ( 0,15, 0, 6, *u = "Cedar Mill", *f = "Netburst", *p = "65nm");
2259 FM ( 0,11, 0, 0, *u = "Knights Ferry", *ciu = TRUE, *f = "K1OM", *p = "45nm"); // found only on en.wikichip.org
2260 FM ( 0,11, 0, 1, *u = "Knights Corner", *ciu = TRUE, *f = "K1OM", *p = "22nm");
2261 FM ( 0,15, 0, 0, *u = "Willamette", *f = "Netburst", *p = ".18um");
2262 FM ( 0,15, 0, 1, *u = "Willamette", *f = "Netburst", *p = ".18um");
2263 FM ( 0,15, 0, 2, *u = "Northwood", *f = "Netburst", *p = ".13um");
2264 FM ( 0,15, 0, 3, *u = "Prescott", *f = "Netburst", *p = "90nm");
2265 FM ( 0,15, 0, 4, *u = "Prescott", *f = "Netburst", *p = "90nm");
2266 FM ( 0,15, 0, 6, *u = "Cedar Mill", *f = "Netburst", *p = "65nm");
22272267 F ( 0,15, *f = "Netburst");
2228 FM ( 1,15, 0, 0, *u = "Itanium2", *p = ".18um");
2229 FM ( 1,15, 0, 1, *u = "Itanium2", *p = ".13um");
2230 FM ( 1,15, 0, 2, *u = "Itanium2", *p = ".13um");
2268 FM ( 1,15, 0, 0, *u = "Itanium2", *p = ".18um");
2269 FM ( 1,15, 0, 1, *u = "Itanium2", *p = ".13um");
2270 FM ( 1,15, 0, 2, *u = "Itanium2", *p = ".13um");
22312271 F ( 1,15, *u = "Itanium2");
2232 F ( 2, 0, *u = "Itanium2", *p = "90nm");
2272 F ( 2, 0, *u = "Itanium2", *p = "90nm");
22332273 F ( 2, 1, *u = "Itanium2");
22342274 DEFAULT ((void)NULL);
22352275 }
34233463 FMS ( 0, 6, 6, 6, 3, "Intel Core (Cannon Lake D0)");
34243464 FM ( 0, 6, 6, 6, "Intel Core (Cannon Lake)");
34253465 FM ( 0, 6, 6, 7, "Intel Core (Cannon Lake)"); // DPTF*
3426 FMSQ( 0, 6, 6,10, 5, sS, "Intel Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Ice Lake C0)"); // ILPMDF* 20210608
3427 FMSQ( 0, 6, 6,10, 6, sS, "Intel Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Ice Lake D2/M1)");
3428 FMQ ( 0, 6, 6,10, sS, "Intel Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Ice Lake)");
3429 FM ( 0, 6, 6,10, "Intel (unknown type) (Ice Lake)");
3466 FMSQ( 0, 6, 6,10, 5, sS, "Intel Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Ice Lake-SP C0)"); // ILPMDF* 20210608
3467 FMS ( 0, 6, 6,10, 5, "Intel Xeon (unknown type) (Ice Lake-SP C0)"); // ILPMDF* 20210608
3468 FMSQ( 0, 6, 6,10, 6, sS, "Intel Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Ice Lake-SP D2/M1)");
3469 FMS ( 0, 6, 6,10, 6, "Intel Xeon (unknown type) (Ice Lake-SP D2/M1)");
3470 FMQ ( 0, 6, 6,10, sS, "Intel Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Ice Lake-SP)");
3471 FM ( 0, 6, 6,10, "Intel Xeon (unknown type) (Ice Lake-SP)");
34303472 // No spec update; MSR_CPUID_table* so far
34313473 // DPTF* claims this is Meteor Lake S
34323474 // ILPMDF* 20221108 claims ICL-D (Ice Lake Xeon D), and provides B0 stepping.
35283570 FMS ( 0, 6, 8,14, 13, "Intel (unknown type) (Whiskey Lake-U V0)"); // ILPMDF* 20190312
35293571 FM ( 0, 6, 8,14, "Intel Core (unknown type) (Kaby Lake / Amber Lake-Y / Whiskey Lake-U / Comet Lake-U)");
35303572 // No spec update; MSR_CPUID_table*, LX*
3573 // coreboot*, based on confidential Sapphire Rapids External Design
3574 // Specification doc (612246), provides steppings D & E0.
35313575 // ILPMDF* 20230214 provides steppings E2, E3, E4, E5.
35323576 // ILPMDF* 20230214 mentions that stepping 8 also is Sapphire Rapids HBM
35333577 // (Xeon Max) B3. Maybe describe that better if I can distinguish them.
3578 // instlatx64 provides a Xeon W sample, but I've seen no spec update for it. Assuming they could be any stepping.
3579 FMSQ( 0, 6, 8,15, 3, sS, "Intel Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids D)");
3580 FMSQ( 0, 6, 8,15, 3, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids D)");
3581 FMS ( 0, 6, 8,15, 3, "Intel Xeon (unknown type) (Sapphire Rapids D)");
3582 FMSQ( 0, 6, 8,15, 4, sS, "Intel Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids E0)");
3583 FMSQ( 0, 6, 8,15, 4, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids E0)");
3584 FMS ( 0, 6, 8,15, 4, "Intel Xeon (unknown type) (Sapphire Rapids E0)");
35343585 FMSQ( 0, 6, 8,15, 5, sS, "Intel Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids E2)");
3586 FMSQ( 0, 6, 8,15, 5, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids E2)");
35353587 FMS ( 0, 6, 8,15, 5, "Intel Xeon (unknown type) (Sapphire Rapids E2)");
35363588 FMSQ( 0, 6, 8,15, 6, sS, "Intel Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids E3)");
3589 FMSQ( 0, 6, 8,15, 6, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids E3)");
35373590 FMS ( 0, 6, 8,15, 6, "Intel Xeon (unknown type) (Sapphire Rapids E3)");
35383591 FMSQ( 0, 6, 8,15, 7, sS, "Intel Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids E4)");
3592 FMSQ( 0, 6, 8,15, 7, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids E4)");
35393593 FMS ( 0, 6, 8,15, 7, "Intel Xeon (unknown type) (Sapphire Rapids E4)");
35403594 FMSQ( 0, 6, 8,15, 8, sS, "Intel Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids E5/B3)");
3595 FMSQ( 0, 6, 8,15, 8, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids E5/B3)");
35413596 FMS ( 0, 6, 8,15, 8, "Intel Xeon (unknown type) (Sapphire Rapids E5/B3)");
35423597 FMQ ( 0, 6, 8,15, sS, "Intel Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids)");
3598 FMQ ( 0, 6, 8,15, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids)");
35433599 FM ( 0, 6, 8,15, "Intel Xeon (unknown type) (Sapphire Rapids)");
35443600 // LX*. Coreboot* provides stepping.
35453601 FMSQ( 0, 6, 9, 6, 0, dC, "Intel Celeron J6400 / N6400 (Elkhart Lake A0)");
35913647 FMQ ( 0, 6, 9, 7, dP, "Intel Pentium Gold G7400 (Alder Lake-S)"); // no docs on Pentium Gold version; instlatx64 sample
35923648 FM ( 0, 6, 9, 7, "Intel (unknown type) (Alder Lake-S/P/H/U)");
35933649 // MSR_CPUID_table*, Coreboot*. Coreboot* provides steppings.
3594 // ILPMDF* 20220510 (and later) claim steppings 3 & 4 *both* are stepping L0. Cut&past error?
3650 // ILPMDF* 20220510 (and later) claim steppings 3 & 4 *both* are stepping L0. Cut&paste error?
35953651 FMSQ( 0, 6, 9,10, 0, Ha, "Intel Core i*-12000 E-core (Alder Lake J0)");
35963652 FMSQ( 0, 6, 9,10, 0, Hc, "Intel Core i*-12000 P-core (Alder Lake J0)");
35973653 FMSQ( 0, 6, 9,10, 0, dc, "Intel Core i*-12000 (Alder Lake J0)");
37043760 FM ( 0, 6, 10, 8, "Intel (unknown type) (Rocket Lake)"); // MSR_CPUID_table*
37053761 FMS ( 0, 6, 10,10, 0, "Intel (unknown type) (Meteor Lake-M A0)"); // DPTF*; undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA; Coreboot* provides steppings.
37063762 FMS ( 0, 6, 10,10, 1, "Intel (unknown type) (Meteor Lake-M A0)"); // DPTF*; undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA; Coreboot* provides steppings.
3763 FMS ( 0, 6, 10,10, 2, "Intel (unknown type) (Meteor Lake-M B0)"); // DPTF*; Coreboot* provides steppings
37073764 FM ( 0, 6, 10,10, "Intel (unknown type) (Meteor Lake-M)"); // MSR_CPUID_table*; DPTF*, LX* (but -L); (engr?) sample via instlatx64 from Komachi_ENSAKA
37083765 FM ( 0, 6, 10,11, "Intel (unknown type) (Meteor Lake-N)"); // DPTF*
37093766 FM ( 0, 6, 10,12, "Intel (unknown type) (Meteor Lake-S)"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA
37123769 FM ( 0, 6, 10,15, "Intel (unknown type) (Sierra Forest)"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA
37133770 FM ( 0, 6, 11, 5, "Intel (unknown type) (Meteor Lake)"); // MSR_CPUID_table*
37143771 FM ( 0, 6, 11, 6, "Intel Atom (Grand Ridge)"); // MSR_CPUID_table*
3772 // Intel doc 743844 provides stepping 1, with name!
37153773 FMSQ( 0, 6, 11, 7, 1, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX B0)");
37163774 FMSQ( 0, 6, 11, 7, 1, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX B0)");
37173775 FMSQ( 0, 6, 11, 7, 1, dc, "Intel Core i*-13000 (Raptor Lake-S/HX B0)");
37203778 FMQ ( 0, 6, 11, 7, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX)");
37213779 FMQ ( 0, 6, 11, 7, dc, "Intel Core i*-13000 (Raptor Lake-S/HX)");
37223780 FM ( 0, 6, 11, 7, "Intel (unknown type) (Raptor Lake-S/HX)");
3723 FMSQ( 0, 6, 11,10, 2, Ha, "Intel Core i*-13000 E-core (Raptor Lake-P J0)"); // ILPMDF* 20230214, instlatx64 sample
3724 FMSQ( 0, 6, 11,10, 2, Hc, "Intel Core i*-13000 P-core (Raptor Lake-P J0)"); // ILPMDF* 20230214, instlatx64 sample
3725 FMSQ( 0, 6, 11,10, 2, dc, "Intel Core i*-13000 (Raptor Lake-P J0)"); // ILPMDF* 20230214
3726 FMS ( 0, 6, 11,10, 2, "Intel (unknown type) (Raptor Lake-P J0)"); // ILPMDF* 20230214
3727 FMSQ( 0, 6, 11,10, 3, Ha, "Intel Core i*-13000 E-core (Raptor Lake-P Q0)"); // ILPMDF* 20230214
3728 FMSQ( 0, 6, 11,10, 3, Hc, "Intel Core i*-13000 P-core (Raptor Lake-P Q0)"); // ILPMDF* 20230214
3729 FMSQ( 0, 6, 11,10, 3, dc, "Intel Core i*-13000 (Raptor Lake-P Q0)"); // ILPMDF* 20230214
3730 FMS ( 0, 6, 11,10, 3, "Intel (unknown type) (Raptor Lake-P Q0)"); // ILPMDF* 20230214
3731 FM ( 0, 6, 11,10, "Intel (unknown type) (Raptor Lake-P)"); // LX*; DPTF*; Coreboot*
3781 // Intel doc 743844 provides steppings 2 & 3, with names!
3782 // IPLMDF* 20230214 contradicts it, saying 2=Q0, but it's prone to cut&paste
3783 // errors, so adhering to the official docs.
3784 FMSQ( 0, 6, 11,10, 2, Ha, "Intel Core i*-13000 E-core (Raptor Lake-H/U/P J0)");
3785 FMSQ( 0, 6, 11,10, 2, Hc, "Intel Core i*-13000 P-core (Raptor Lake-H/U/P J0)");
3786 FMSQ( 0, 6, 11,10, 2, dc, "Intel Core i*-13000 (Raptor Lake-H/U/P J0)");
3787 FMS ( 0, 6, 11,10, 2, "Intel (unknown type) (Raptor Lake-H/U/P J0)");
3788 FMSQ( 0, 6, 11,10, 3, Ha, "Intel Core i*-13000 E-core (Raptor Lake-P Q0)");
3789 FMSQ( 0, 6, 11,10, 3, Hc, "Intel Core i*-13000 P-core (Raptor Lake-P Q0)");
3790 FMSQ( 0, 6, 11,10, 3, dc, "Intel Core i*-13000 (Raptor Lake-P Q0)");
3791 FMS ( 0, 6, 11,10, 3, "Intel (unknown type) (Raptor Lake-P Q0)");
3792 FM ( 0, 6, 11,10, "Intel (unknown type) (Raptor Lake-P)");
37323793 FM ( 0, 6, 11,13, "Intel (unknown type) (Lunar Lake)"); // LX*
3733 FMS ( 0, 6, 11,14, 0, "Intel (unknown type) (Alder Lake-N A0)"); // Coreboot*, DPTF*
3734 FM ( 0, 6, 11,14, "Intel (unknown type) (Alder Lake-N)"); // Coreboot*, LX*, DPTF*
3794 FMSQ( 0, 6, 11,14, 0, Ia, "Intel Core i*-N300 N-Series E-core (Alder Lake-N A0)");
3795 FMSQ( 0, 6, 11,14, 0, Ic, "Intel Core i*-N300 N-Series P-core (Alder Lake-N A0)"); // possibly no P-cores ever for this model
3796 FMSQ( 0, 6, 11,14, 0, Ha, "Intel N-Series E-core (Alder Lake-N A0)");
3797 FMSQ( 0, 6, 11,14, 0, Hc, "Intel N-Series P-core (Alder Lake-N A0)"); // possibly no P-cores ever for this model
3798 FMS ( 0, 6, 11,14, 0, "Intel N-Series (Alder Lake-N A0)");
3799 FMQ ( 0, 6, 11,14, Ia, "Intel Core i*-N300 N-Series E-core (Alder Lake-N)");
3800 FMQ ( 0, 6, 11,14, Ic, "Intel Core i*-N300 N-Series P-core (Alder Lake-N)"); // possibly no P-cores ever for this model
3801 FMQ ( 0, 6, 11,14, Ha, "Intel N-Series E-core (Alder Lake-N)");
3802 FMQ ( 0, 6, 11,14, Hc, "Intel N-Series P-core (Alder Lake-N)"); // possibly no P-cores ever for this model
3803 FM ( 0, 6, 11,14, "Intel N-Series (Alder Lake-N)");
3804 // Intel doc 743844 provides steppings 2 & 5, with names!
37353805 FMSQ( 0, 6, 11,15, 2, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX C0)");
37363806 FMSQ( 0, 6, 11,15, 2, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX C0)");
37373807 FMSQ( 0, 6, 11,15, 2, dc, "Intel Core i*-13000 (Raptor Lake-S/HX C0)");
37383808 FMS ( 0, 6, 11,15, 2, "Intel (unknown type) (Raptor Lake-S/HX C0)");
3739 FMSQ( 0, 6, 11,15, 5, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX C0)");
3740 FMSQ( 0, 6, 11,15, 5, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX C0)");
3741 FMSQ( 0, 6, 11,15, 5, dc, "Intel Core i*-13000 (Raptor Lake-S/HX C0)");
3742 FMS ( 0, 6, 11,15, 5, "Intel (unknown type) (Raptor Lake-S/HX C0)");
3743 FMQ ( 0, 6, 11,15, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/H)");
3744 FMQ ( 0, 6, 11,15, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/H)");
3745 FMQ ( 0, 6, 11,15, dc, "Intel Core i*-13000 (Raptor Lake-S/H)");
3746 FM ( 0, 6, 11,15, "Intel (unknown type) (Raptor Lake-S/H)");
3809 FMSQ( 0, 6, 11,15, 5, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX/P C0)");
3810 FMSQ( 0, 6, 11,15, 5, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX/P C0)");
3811 FMSQ( 0, 6, 11,15, 5, dc, "Intel Core i*-13000 (Raptor Lake-S/HX/P C0)");
3812 FMS ( 0, 6, 11,15, 5, "Intel (unknown type) (Raptor Lake-S/HX/P C0)");
3813 FMQ ( 0, 6, 11,15, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX/P)");
3814 FMQ ( 0, 6, 11,15, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX/P)");
3815 FMQ ( 0, 6, 11,15, dc, "Intel Core i*-13000 (Raptor Lake-S/HX/P)");
3816 FM ( 0, 6, 11,15, "Intel (unknown type) (Raptor Lake-S/HX/P)");
3817 FM ( 0, 6, 12, 6, "Intel (unknown type) (Arrow Lake)"); // LX*
37473818 FM ( 0, 6, 12,15, "Intel Xeon (unknown type) (Emerald Rapids)"); // MSR_CPUID_table*, LX*
37483819 FQ ( 0, 6, sX, "Intel Xeon (unknown model)");
37493820 FQ ( 0, 6, se, "Intel Xeon (unknown model)");
47294800 FMS (10,15, 7, 0, 0, "AMD Ryzen (Phoenix A0)");
47304801 FM (10,15, 7, 0, "AMD Ryzen (Phoenix)");
47314802 FMS (10,15, 7, 4, 0, "AMD Ryzen (Phoenix E0)"); // undocumented, but engr sample via instlatx64 from bakerlab.org (6220795)
4803 FMS (10,15, 7, 4, 1, "AMD Ryzen (Phoenix E1)"); // undocumented, but engr sample via from @BenchLeaks
47324804 FM (10,15, 7, 4, "AMD Ryzen (Phoenix)"); // undocumented, but engr sample via instlatx64 from bakerlab.org (6220795)
47334805 FMS (10,15, 7, 8, 0, "AMD Ryzen (Phoenix 2 A0)"); // Coreboot*
47344806 FM (10,15, 7, 8, "AMD Ryzen (Phoenix 2)"); // Coreboot*
47354807 FMS (10,15, 10, 0, 0, "AMD Ryzen (Bergamo A0)"); // undocumented, but (engr?) sample via instlatx64 from @ExecuFix
4808 FMS (10,15, 10, 0, 1, "AMD Ryzen (Bergamo A1)"); // undocumented, but (engr?) sample from @YuuKi_AnS
47364809 FM (10,15, 10, 0, "AMD Ryzen (Bergamo)"); // undocumented, but (engr?) sample via instlatx64 from @ExecuFix
47374810 FMS (10,15, 10, 1, 1, "AMD Ryzen (Bergamo B1)");
47384811 FM (10,15, 10, 1, "AMD Ryzen (Bergamo)");
52295302 #define GET_CoresPerComputeUnit_AMD(val_8000001e_ebx) \
52305303 (BIT_EXTRACT_LE((val_8000001e_ebx), 8, 16))
52315304
5232 #define V2_TOPO_SMT 1
5233 #define V2_TOPO_CORE 2
5234
52355305 static void decode_mp_synth(code_stash_t* stash)
52365306 {
52375307 switch (stash->vendor) {
52475317 */
52485318 if (stash->saw_1f) {
52495319 stash->mp.method = "Intel leaf 0x1f";
5320 unsigned int last_count = 1;
52505321 unsigned int try;
52515322 for (try = 0; try < LENGTH(stash->val_1f_ecx); try++) {
5252 if (GET_V2_TOPO_LEVEL(stash->val_1f_ecx[try]) == V2_TOPO_SMT) {
5253 stash->mp.hyperthreads
5254 = GET_V2_TOPO_PROCESSORS(stash->val_1f_ebx[try]);
5255 } else if (GET_V2_TOPO_LEVEL(stash->val_1f_ecx[try]) == V2_TOPO_CORE) {
5256 stash->mp.cores = GET_V2_TOPO_PROCESSORS(stash->val_1f_ebx[try]);
5323 unsigned int level = GET_V2_TOPO_LEVEL(stash->val_1f_ecx[try]);
5324 if (level < LENGTH(v2TopoToCotopo)) {
5325 unsigned ct = v2TopoToCotopo[level];
5326 if (ct != Invalid) {
5327 unsigned int count
5328 = GET_V2_TOPO_PROCESSORS(stash->val_1f_ebx[try]);
5329 stash->mp.count[ct] = count / last_count;
5330 last_count = count;
5331 }
52575332 }
52585333 }
52595334 } else if (stash->saw_b) {
52635338 if (ht == 0) {
52645339 ht = 1;
52655340 }
5266 stash->mp.cores = tc / ht;
5267 stash->mp.hyperthreads = ht;
5341 stash->mp.count[Core] = tc / ht;
5342 stash->mp.count[Smt] = ht;
52685343 } else if (stash->saw_4) {
52695344 unsigned int tc = GET_LogicalProcessorCount(stash->val_1_ebx);
52705345 unsigned int c;
52765351 c = tc / 2;
52775352 stash->mp.method = "Intel leaf 1/4 (zero fallback)";
52785353 }
5279 stash->mp.cores = c;
5280 stash->mp.hyperthreads = tc / c;
5354 stash->mp.count[Core] = c;
5355 stash->mp.count[Smt] = tc / c;
52815356 } else {
52825357 stash->mp.method = "Intel leaf 1";
5283 stash->mp.cores = 1;
5358 stash->mp.count[Core] = 1;
52845359 if (IS_HTT(stash->val_1_edx)) {
52855360 unsigned int tc = GET_LogicalProcessorCount(stash->val_1_ebx);
5286 stash->mp.hyperthreads = (tc >= 2 ? tc : 2);
5361 stash->mp.count[Smt] = (tc >= 2 ? tc : 2);
52875362 } else {
5288 stash->mp.hyperthreads = 1;
5363 stash->mp.count[Smt] = 1;
52895364 }
52905365 }
52915366 break;
52925367 case VENDOR_AMD:
52935368 case VENDOR_HYGON:
5294 /*
5295 ** Logic from:
5296 ** AMD CPUID Specification (25481 Rev. 2.16),
5297 ** 3. LogicalProcessorCount, CmpLegacy, HTT, and NC
5298 ** AMD CPUID Specification (25481 Rev. 2.28),
5299 ** 3. Multiple Core Calculation
5300 */
5301 if (IS_HTT(stash->val_1_edx)) {
5302 unsigned int tc = GET_LogicalProcessorCount(stash->val_1_ebx);
5303 unsigned int c;
5304 if (GET_ApicIdCoreIdSize(stash->val_80000008_ecx) != 0) {
5305 unsigned int size = GET_ApicIdCoreIdSize(stash->val_80000008_ecx);
5306 unsigned int mask = (1 << size) - 1;
5307 c = (GET_NC_AMD(stash->val_80000008_ecx) & mask) + 1;
5308 } else {
5309 c = GET_NC_AMD(stash->val_80000008_ecx) + 1;
5369 if (stash->saw_b) {
5370 /*
5371 ** Logic by analogy to Intel
5372 */
5373 unsigned int ht = GET_X2APIC_PROCESSORS(stash->val_b_ebx[0]);
5374 unsigned int tc = GET_X2APIC_PROCESSORS(stash->val_b_ebx[1]);
5375 stash->mp.method = (stash->vendor == VENDOR_AMD ? "AMD leaf 0xb"
5376 : "Hygon leaf 0xb");
5377 if (ht == 0) {
5378 ht = 1;
53105379 }
5311 if ((tc == c) == IS_CmpLegacy(stash->val_80000001_ecx)) {
5312 stash->mp.method = (stash->vendor == VENDOR_AMD ? "AMD"
5313 : "Hygon");
5314 if (c > 1) {
5315 stash->mp.cores = c;
5316 stash->mp.hyperthreads = tc / c;
5380 stash->mp.count[Core] = tc / ht;
5381 stash->mp.count[Smt] = ht;
5382 } else if (IS_HTT(stash->val_1_edx)) {
5383 /*
5384 ** Logic from:
5385 ** AMD CPUID Specification (25481 Rev. 2.16),
5386 ** 3. LogicalProcessorCount, CmpLegacy, HTT, and NC
5387 ** AMD CPUID Specification (25481 Rev. 2.28),
5388 ** 3. Multiple Core Calculation
5389 **
5390 ** For Families 10h-16h, the CU (CMT "compute unit") logic was a
5391 ** logical extension.
5392 **
5393 ** For Families 17h and later, terminology changed to reflect that
5394 ** the Family 10h-16h cores had been sharing resources significantly:
5395 ** Family 10h-16h => Family 17h
5396 ** ----------------------------
5397 ** CU => core
5398 ** core => thread
5399 ** And leaf 0x8000001e/ebx is used for smt_count, because 1/ebx is
5400 ** unreliable.
5401 */
5402 unsigned int size = (GET_ApicIdCoreIdSize(stash->val_80000008_ecx) != 0
5403 ? GET_ApicIdCoreIdSize(stash->val_80000008_ecx)
5404 : 32);
5405 unsigned int mask = RIGHTMASK(size);
5406 unsigned int core_count
5407 = (GET_NC_AMD(stash->val_80000008_ecx) & mask) + 1;
5408 unsigned int total_count = GET_LogicalProcessorCount(stash->val_1_ebx);
5409 unsigned int smt_count = total_count / core_count;
5410 unsigned int cu_count = 1;
5411 if (GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) != 0) {
5412 if (Synth_Family(stash->val_80000001_eax) > 0x16) {
5413 unsigned int threads_per_core
5414 = GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) + 1;
5415 smt_count = threads_per_core;
5416 core_count /= threads_per_core;
53175417 } else {
5318 stash->mp.cores = 1;
5319 stash->mp.hyperthreads = (tc >= 2 ? tc : 2);
5418 unsigned int cores_per_cu
5419 = GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) + 1;
5420 cu_count = (core_count / cores_per_cu);
5421 core_count = cores_per_cu;
53205422 }
5321 } else {
5322 /*
5323 ** Rev 2.28 leaves out mention that this case is nonsensical, but
5324 ** I'm leaving it in here as an "unknown" case.
5325 */
53265423 }
5424 stash->mp.method = (stash->vendor == VENDOR_AMD
5425 ? "AMD leaf 1/0x8000008"
5426 : "Hygon leaf 1/0x80000008");
5427 stash->mp.count[Core] = core_count;
5428 stash->mp.count[Smt] = smt_count;
5429 stash->mp.count[Cu] = cu_count;
53275430 } else {
5328 stash->mp.method = (stash->vendor == VENDOR_AMD ? "AMD" : "Hygon");
5329 stash->mp.cores = 1;
5330 stash->mp.hyperthreads = 1;
5431 stash->mp.method = (stash->vendor == VENDOR_AMD ? "AMD leaf 1"
5432 : "Hygon leaf 1");
5433 stash->mp.count[Core] = 1;
5434 stash->mp.count[Smt] = 1;
53315435 }
53325436 break;
53335437 default:
53345438 if (!IS_HTT(stash->val_1_edx)) {
53355439 stash->mp.method = "Generic leaf 1 no multi-threading";
5336 stash->mp.cores = 1;
5337 stash->mp.hyperthreads = 1;
5440 stash->mp.count[Core] = 1;
5441 stash->mp.count[Smt] = 1;
53385442 }
53395443 break;
53405444 }
53425446
53435447 static void print_mp_synth(const struct mp* mp)
53445448 {
5449 static ccstring prefix[NumCotopos] = { "hyper-threaded (t",
5450 "multi-core (c",
5451 "multi-compute-unit (cu",
5452 "multi-module (m",
5453 "multi-tile (t",
5454 "multi-die (d",
5455 "multi-die-group (dg",
5456 "multi-package (p" };
5457
53455458 printf(" (multi-processing synth) = ");
53465459 if (mp->method == NULL) {
53475460 printf("?");
5348 } else if (mp->cores > 1) {
5349 if (mp->hyperthreads > 1) {
5350 printf("multi-core (c=%u), hyper-threaded (t=%u)",
5351 mp->cores, mp->hyperthreads);
5352 } else {
5353 printf("multi-core (c=%u)", mp->cores);
5461 } else {
5462 boolean first = TRUE;
5463 for (unsigned int ct = NumCotopos-1;; ct--) {
5464 if (mp->count[ct] > 1) {
5465 if (first) {
5466 first = FALSE;
5467 } else {
5468 printf(", ");
5469 }
5470 printf("%s=%u)", prefix[ct], mp->count[ct]);
5471 }
5472 if (ct == 0) break;
53545473 }
5355 } else if (mp->hyperthreads > 1) {
5356 printf("hyper-threaded (t=%u)", mp->hyperthreads);
5357 } else {
5358 printf("none");
5474 if (first) {
5475 printf("none");
5476 }
53595477 }
53605478 printf("\n");
53615479
54075525
54085526 static void print_apic_synth (code_stash_t* stash)
54095527 {
5410 unsigned int smt_width = 0;
5411 unsigned int core_width = 0;
5412 unsigned int cu_width = 0;
5413
5528 typedef struct {
5529 ccstring abbrev;
5530 boolean alwaysShowWidth;
5531 boolean alwaysShowId;
5532 } CotopoDisplay;
5533 static CotopoDisplay dsp[NumCotopos] = { { "SMT", TRUE, TRUE },
5534 { "CORE", TRUE, TRUE },
5535 { "CU", FALSE, FALSE },
5536 { "MOD", FALSE, FALSE },
5537 { "TILE", FALSE, FALSE },
5538 { "DIE", FALSE, FALSE },
5539 { "DIEGRP", FALSE, FALSE },
5540 { "PKG", FALSE, TRUE } };
5541 unsigned int widths[NumCotopos] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5542 unsigned int offsets[NumCotopos] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5543 unsigned int tails[NumCotopos] = { 0, 0, 0, 0, 0, 0, 0, 0 };
5544
54145545 switch (stash->vendor) {
54155546 case VENDOR_INTEL:
54165547 /*
54235554 ** Extension to the 0x1f leaf was obvious.
54245555 */
54255556 if (stash->saw_1f) {
5557 unsigned int last_width = 0;
54265558 unsigned int try;
54275559 for (try = 0; try < LENGTH(stash->val_1f_ecx); try++) {
54285560 unsigned int level = GET_V2_TOPO_LEVEL(stash->val_1f_ecx[try]);
5429 if (level == V2_TOPO_SMT) {
5430 smt_width = GET_V2_TOPO_WIDTH(stash->val_1f_eax[try]);
5431 } else if (level == V2_TOPO_CORE) {
5432 core_width = GET_V2_TOPO_WIDTH(stash->val_1f_eax[try]);
5561 unsigned int width = GET_V2_TOPO_WIDTH(stash->val_1f_eax[try]);
5562 if (level < LENGTH(v2TopoToCotopo)) {
5563 unsigned ct = v2TopoToCotopo[level];
5564 if (ct != Invalid) {
5565 widths[ct] = width - last_width;
5566 }
54335567 }
5568 last_width = width;
54345569 }
54355570 } else if (stash->saw_b) {
5436 smt_width = GET_X2APIC_WIDTH(stash->val_b_eax[0]);
5437 core_width = GET_X2APIC_WIDTH(stash->val_b_eax[1]);
5571 widths[Smt] = GET_X2APIC_WIDTH(stash->val_b_eax[0]);
5572 widths[Core] = GET_X2APIC_WIDTH(stash->val_b_eax[1]) - widths[Smt];
54385573 } else if (stash->saw_4 && (stash->val_4_eax & 0x1f) != 0) {
54395574 unsigned int core_count = GET_NC_INTEL(stash->val_4_eax) + 1;
54405575 unsigned int smt_count = (GET_LogicalProcessorCount(stash->val_1_ebx)
54415576 / core_count);
5442 smt_width = bits_needed(smt_count);
5443 core_width = bits_needed(core_count);
5577 widths[Smt] = bits_needed(smt_count);
5578 widths[Core] = bits_needed(core_count);
54445579 } else {
54455580 return;
54465581 }
54475582 break;
54485583 case VENDOR_AMD:
5584 case VENDOR_HYGON:
54495585 /*
54505586 ** Logic deduced by analogy: As Intel's decode_mp_synth code is to AMD's
54515587 ** decode_mp_synth code, so is Intel's APIC synth code to this.
54545590 ** logical extension.
54555591 **
54565592 ** For Families 17h and later, terminology changed to reflect that
5457 ** the Family 10h-16h cores had been sharing resources significantly,
5458 ** similarly to (but less drastically than) SMT threads:
5593 ** the Family 10h-16h cores had been sharing resources significantly:
54595594 ** Family 10h-16h => Family 17h
54605595 ** ----------------------------
54615596 ** CU => core
54635598 ** And leaf 0x8000001e/ebx is used for smt_count, because 1/ebx is
54645599 ** unreliable.
54655600 */
5466 if (IS_HTT(stash->val_1_edx)
5467 && GET_ApicIdCoreIdSize(stash->val_80000008_ecx) != 0) {
5601 if (stash->saw_b) {
5602 widths[Smt] = GET_X2APIC_WIDTH(stash->val_b_eax[0]);
5603 widths[Core] = GET_X2APIC_WIDTH(stash->val_b_eax[1]) - widths[Smt];
5604 } else if (IS_HTT(stash->val_1_edx)
5605 && GET_ApicIdCoreIdSize(stash->val_80000008_ecx) != 0) {
54685606 unsigned int size = GET_ApicIdCoreIdSize(stash->val_80000008_ecx);
5469 unsigned int mask = (1 << size) - 1;
5470 unsigned int core_count = ((GET_NC_AMD(stash->val_80000008_ecx) & mask)
5471 + 1);
5472 unsigned int smt_count = (GET_LogicalProcessorCount(stash->val_1_ebx)
5473 / core_count);
5474 unsigned int cu_count = 1;
5607 unsigned int mask = RIGHTMASK(size);
5608 unsigned int core_count
5609 = (GET_NC_AMD(stash->val_80000008_ecx) & mask) + 1;
5610 unsigned int total_count = GET_LogicalProcessorCount(stash->val_1_ebx);
5611 unsigned int smt_count = total_count / core_count;
5612 unsigned int cu_count = 1;
54755613 if (GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) != 0) {
54765614 if (Synth_Family(stash->val_80000001_eax) > 0x16) {
54775615 unsigned int threads_per_core
54855623 core_count = cores_per_cu;
54865624 }
54875625 }
5488 smt_width = bits_needed(smt_count);
5489 core_width = bits_needed(core_count);
5490 cu_width = bits_needed(cu_count);
5626 widths[Smt] = bits_needed(smt_count);
5627 widths[Core] = bits_needed(core_count);
5628 widths[Cu] = bits_needed(cu_count);
54915629 } else {
54925630 return;
54935631 }
54965634 return;
54975635 }
54985636
5499 // Possibly this should be expanded with Intel leaf 1f's module, tile, and
5500 // die levels. They could be made into hidden architectural levels unless
5501 // actually present, much like the CU level.
5502
55035637 printf(" (APIC widths synth):");
5504 if (cu_width != 0) {
5505 printf(" CU_width=%u", cu_width);
5638 for (unsigned int ct = NumCotopos-1;; ct--) {
5639 if (dsp[ct].alwaysShowWidth || widths[ct] != 0) {
5640 printf(" %s_width=%u", dsp[ct].abbrev, widths[ct]);
5641 }
5642 if (ct == 0) break;
55065643 }
5507 printf(" CORE_width=%u", core_width);
5508 printf(" SMT_width=%u", smt_width);
55095644 printf("\n");
55105645
5511 unsigned int smt_off = 24;
5512 unsigned int smt_tail = smt_off + smt_width;
5513 unsigned int core_off = smt_tail;
5514 unsigned int core_tail = core_off + core_width;
5515 unsigned int cu_off = core_tail;
5516 unsigned int cu_tail = cu_off + cu_width;
5517 unsigned int pkg_off = cu_tail;
5518 unsigned int pkg_tail = 32;
5646 // Compute the offsets & tails so that the bit fields can be walked in
5647 // reverse order, outermost:Pkg to innermost:Smt.
5648 {
5649 unsigned int offset = 0;
5650 for (unsigned int ct = 0; ct < NumCotopos; ct++) {
5651 offsets[ct] = offset;
5652 tails[ct] = offset + widths[ct];
5653 offset = tails[ct];
5654 }
5655 // The highest level (Pkg) always is all of the remaining bits
5656 tails[NumCotopos-1] = 32;
5657 }
5658
5659 unsigned int apic_id;
5660 if (stash->saw_8000001e && Synth_Family(stash->val_1_eax) != 0x15) {
5661 // The 0x8000001e/eax extended APIC ID appears to have unreliable values
5662 // in the Piledriver..Excavator timeframe.
5663 apic_id = stash->val_8000001e_eax;
5664 } else if (stash->saw_1f) {
5665 apic_id = stash->val_1f_edx;
5666 } else if (stash->saw_b) {
5667 apic_id = stash->val_b_edx;
5668 } else {
5669 apic_id = BIT_EXTRACT_LE(stash->val_1_ebx, 24, 32);
5670 }
55195671
55205672 printf(" (APIC synth):");
5521 printf(" PKG_ID=%d", (pkg_off < pkg_tail
5522 ? BIT_EXTRACT_LE(stash->val_1_ebx, pkg_off, pkg_tail)
5523 : 0));
5524 if (cu_width != 0) {
5525 printf(" CU_ID=%d", BIT_EXTRACT_LE(stash->val_1_ebx, cu_off, cu_tail));
5673 for (unsigned int ct = NumCotopos-1;; ct--) {
5674 if (dsp[ct].alwaysShowId || widths[ct] != 0) {
5675 printf(" %s_ID=%u",
5676 dsp[ct].abbrev,
5677 BIT_EXTRACT_LE(apic_id, offsets[ct], tails[ct]));
5678 }
5679 if (ct == 0) break;
55265680 }
5527 printf(" CORE_ID=%d", BIT_EXTRACT_LE(stash->val_1_ebx, core_off, core_tail));
5528 printf(" SMT_ID=%d", BIT_EXTRACT_LE(stash->val_1_ebx, smt_off, smt_tail));
55295681 printf("\n");
55305682 }
55315683
63066458 static named_item names[]
63076459 = { { "AVX-VNNI-INT8 instructions" , 4, 4, bools },
63086460 { "AVX-NE-CONVERT instructions" , 5, 5, bools },
6461 { "AVX-COMPLEX instructions" , 8, 8, bools },
63096462 { "PREFETCHIT0, PREFETCHIT1 instructions" , 14, 14, bools },
63106463 { "CET_SSS: shadow stacks w/o page faults" , 18, 18, bools },
63116464 };
63236476 { "DDPD_U: data dep prefetcher disable" , 3, 3, bools },
63246477 { "BHI_CTRL: IBP BHB-focused disable" , 4, 4, bools },
63256478 { "MCDT_NO: MCDT mitigation not needed" , 5, 5, bools },
6479 { "UC-lock disable" , 6, 6, bools },
63266480 };
63276481 print_names(value, names, LENGTH(names),
63286482 /* max_len => */ 40);
63956549 print_b_1f_eax(unsigned int value)
63966550 {
63976551 static named_item names[]
6398 = { { "bit width of level" , 0, 4, NIL_IMAGES },
6552 = { { "bit width of level & previous levels" , 0, 4, NIL_IMAGES },
63996553 };
64006554
64016555 print_names(value, names, LENGTH(names),
64166570 static void
64176571 print_b_1f_ecx(unsigned int value)
64186572 {
6573 // If more levels are added here, be sure to check:
6574 // V2_TOPO_NUM
6575 // val_1f_{eax,ebx,ecx} (in code_stash_t)
6576 // NIL_STASH
6577 // v2TopotoCotopo
6578 // Cotopo
64196579 static ccstring level_type[1<<8] = { "invalid (0)",
64206580 "thread (1)",
64216581 "core (2)",
64226582 "module (3)",
64236583 "tile (4)",
6424 "die (5)" };
6584 "die (5)",
6585 "die group (6)" };
64256586
64266587 static named_item names[]
64276588 = { { "level number" , 0, 7, NIL_IMAGES },
67156876 static named_item names[]
67166877 = { { "infrequent updates of COS" , 1, 1, bools },
67176878 { "code and data prioritization supported" , 2, 2, bools },
6879 { "non-contiguous 1s value supported" , 3, 3, bools },
67186880 };
67196881
67206882 print_names(value, names, LENGTH(names),
67646926 { "SGX ENCLV E*VIRTCHILD, ESETCONTEXT" , 5, 5, bools },
67656927 { "SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC", 6, 6, bools },
67666928 { "SGX ENCLU EVERIFYREPORT2" , 7, 7, bools },
6929 { "SGX ENCLS EUPDATESVN" , 10, 10, bools },
67676930 { "SGX ENCLU EDECCSSA" , 11, 11, bools },
67686931 };
67696932
72157378 = { { "mispredict bit supported" , 0, 0, bools },
72167379 { "timed LBRs supported" , 1, 1, bools },
72177380 { "branch type field supported" , 2, 2, bools },
7381 { "event logging supported bitmap" , 16, 19, NIL_IMAGES },
72187382 };
72197383
72207384 print_names(value, names, LENGTH(names),
72807444
72817445 print_names(value, names, LENGTH(names),
72827446 /* max_len => */ 0);
7447 }
7448
7449 static void
7450 print_23_0_ebx(unsigned int value)
7451 {
7452 static named_item names[]
7453 = { { "IA32_PERFEVTSELx UnitMask2 supported" , 0, 0, bools },
7454 { "IA32_PERFEVTSELx Z bit supported" , 1, 1, bools },
7455 };
7456
7457 print_names(value, names, LENGTH(names),
7458 /* max_len => */ 36);
72837459 }
72847460
72857461 static void
75737749 { "use synced timeline" , 15, 15, bools },
75747750 { "use direct local flush entire" , 17, 17, bools },
75757751 { "no non-architectural core sharing" , 18, 18, bools },
7752 { "use hypercalls for MMIO config space I/O", 21, 21, bools },
75767753 };
75777754
75787755 print_names(value, names, LENGTH(names),
87038880 { "INVLPGB/TLBSYNC hyperv interc enable" , 24, 24, bools },
87048881 { "VNMI: NMI virtualization" , 25, 25, bools },
87058882 { "IBS virtualization" , 26, 26, bools },
8883 { "extended LVT offset fault change" , 27, 27, bools },
87068884 { "guest SVME addr check" , 28, 28, bools }, // LX*, Qemu*
87078885 };
87088886
90659243 {
90669244 static named_item names[]
90679245 = { { "no nested data-breakpoints" , 0, 0, bools },
9246 { "FsGsKernelGsBaseNonSerializing" , 1, 1, bools },
90689247 { "LFENCE always serializing" , 2, 2, bools },
90699248 { "SMM paging configuration lock support" , 3, 3, bools },
90709249 { "null selector clears base" , 6, 6, bools },
90719250 { "upper address ignore support" , 7, 7, bools },
90729251 { "automatic IBRS" , 8, 8, bools },
90739252 { "SMM_CTL MSR not supported" , 9, 9, bools },
9253 { "FSRS: fast short REP STOSB support" , 10, 10, bools },
9254 { "FSRC: fast short REP CMPSB support" , 11, 11, bools },
90749255 { "prefetch control MSR support" , 13, 13, bools },
90759256 { "CPUID disable for non-privileged" , 17, 17, bools },
9257 { "enhanced predictive store forwarding" , 18, 18, bools },
90769258 };
90779259
90789260 print_names(value, names, LENGTH(names),
91119293 = { { "number of core perf ctrs" , 0, 3, NIL_IMAGES },
91129294 { "number of LBR stack entries" , 4, 9, NIL_IMAGES },
91139295 { "number of avail Northbridge perf ctrs" , 10, 15, NIL_IMAGES },
9296 { "number of available UMC PMCs" , 16, 21, NIL_IMAGES },
91149297 };
91159298
91169299 print_names(value, names, LENGTH(names),
91569339 static void
91579340 print_80000026_1_ebx(unsigned int value)
91589341 {
9342 // These strings are from 55901 for Raphael. Is it possible they will differ
9343 // on other uarch's?
9344 static ccstring native_model[1<<4] = { "Zen4 (0)" };
9345 static ccstring core_type[1<<4] = { "performance (0)",
9346 "efficiency (1)" };
9347
91599348 static named_item names[]
91609349 = { { "number of logical processors at level" , 0, 15, NIL_IMAGES },
91619350 { "power efficiency ranking" , 16, 23, NIL_IMAGES },
9162 { "native mode ID" , 24, 27, NIL_IMAGES },
9163 { "core type" , 28, 31, NIL_IMAGES },
9351 { "native model ID" , 24, 27, native_model },
9352 { "core type" , 28, 31, core_type },
91649353 };
91659354
91669355 print_names(value, names, LENGTH(names),
96549843 stash->val_4_eax = words[WORD_EAX];
96559844 }
96569845 } else if (reg == 0xb) {
9657 stash->saw_b = TRUE;
9846 if (words[WORD_EAX] != 0
9847 || words[WORD_EBX] != 0
9848 || words[WORD_ECX] != 0
9849 || words[WORD_EDX] != 0) {
9850 // If this returns all 0's, it's an unsupported leaf, and not even
9851 // the extended APIC ID should be used. AMD is particularly prone
9852 // to this.
9853 stash->saw_b = TRUE;
9854 }
9855 if (try == 0) {
9856 stash->val_b_edx = words[WORD_EDX];
9857 }
96589858 if (try < LENGTH(stash->val_b_eax)) {
96599859 stash->val_b_eax[try] = words[WORD_EAX];
96609860 }
96759875 }
96769876 } else if (reg == 0x1f) {
96779877 stash->saw_1f = TRUE;
9878 if (try == 0) {
9879 stash->val_1f_edx = words[WORD_EDX];
9880 }
96789881 if (try < LENGTH(stash->val_1f_eax)) {
96799882 stash->val_1f_eax[try] = words[WORD_EAX];
96809883 }
97009903 } else if (reg == 0x80000008) {
97019904 stash->val_80000008_ecx = words[WORD_ECX];
97029905 } else if (reg == 0x8000001e) {
9906 stash->saw_8000001e = TRUE;
9907 stash->val_8000001e_eax = words[WORD_EAX];
97039908 stash->val_8000001e_ebx = words[WORD_EBX];
9704 } else if (reg == 0x80860003) {
9909 } else if (reg == 0x80860003) {
97059910 memcpy(&stash->transmeta_info[0], words,
97069911 sizeof(unsigned int)*WORD_NUM);
97079912 } else if (reg == 0x80860004) {
1005810263 } else if (reg == 0x23) {
1005910264 if (try == 0) {
1006010265 printf(" Architecture Performance Monitoring Extended (0x23):\n");
10266 print_23_0_ebx(words[WORD_EBX]);
1006110267 } else if (try == 1) {
10062 printf(" general counters bitmap = 0x%0llx\n",
10268 printf(" general counters bitmap = 0x%0llx\n",
1006310269 (unsigned long long)words[WORD_EAX]);
10064 printf(" fixed counters bitmap = 0x%0llx\n",
10270 printf(" fixed counters bitmap = 0x%0llx\n",
1006510271 (unsigned long long)words[WORD_EBX]);
1006610272 } else if (try == 2) {
1006710273 // All reserved
1038410590 printf(" Extended Performance Monitoring and Debugging (0x80000022):\n");
1038510591 print_80000022_eax(words[WORD_EAX]);
1038610592 print_80000022_ebx(words[WORD_EBX]);
10593 printf(" active UMCs bitmask = 0x%0x\n",
10594 words[WORD_ECX]);
1038710595 } else if (reg == 0x80000023) {
1038810596 printf(" Multi-Key Encrypted Memory Capabilities (0x80000023):\n");
1038910597 print_80000023_eax(words[WORD_EAX]);
1059910807 status = sched_setaffinity(0, sizeof(cpu_set_t), &cpuset);
1060010808 #endif
1060110809 if (status == -1) {
10602 if (cpu > 0) {
10603 if (errno == EINVAL) return -1;
10604 }
10810 if (errno == EINVAL) return -1;
1060510811
1060610812 fprintf(stderr,
1060710813 "%s: unable to setaffinity to cpu %d; errno = %d (%s)\n",
+4
-2
cpuid.man less more
00 .\"
1 .\" $Id: cpuid.man,v 20230306 2023/03/06 04:07:16 todd $
1 .\" $Id: cpuid.man,v 20230505 2023/05/05 07:40:05 todd $
22 .\"
3 .TH CPUID 1 "6 Mar 2023" "20230306"
3 .TH CPUID 1 "5 May 2023" "20230505"
44 .SH NAME
55 cpuid \- Dump CPUID information for each CPU
66 .SH SYNOPSIS
528528 Supporting 13th Generation Intel Core Processor for S/P/PX/H/HX/U Processor Line
529529 Platforms, formerly known as Raptor Lake
530530 .br
531 759603: Intel Processor and Intel Core i3 N-Series Datasheet, Volume 1 of 2
532 .br
531533 Intel Microcode Update Guidance
532534 .br
533535 Branch History Injection and Intra-mode Branch Target Injection /
+1
-1
cpuid.spec less more
0 %define version 20230306
0 %define version 20230505
11 %define release 1
22 Summary: dumps CPUID information about the CPU(s)
33 Name: cpuid
+4
-3
debian/changelog less more
0 cpuid (20230306-1) UNRELEASED; urgency=low
0 cpuid (20230505-1) UNRELEASED; urgency=low
11
22 * New upstream release.
3
4 -- Debian Janitor <janitor@jelmer.uk> Mon, 03 Apr 2023 10:32:45 -0000
3 * New upstream release.
4
5 -- Debian Janitor <janitor@jelmer.uk> Fri, 19 May 2023 14:55:51 -0000
56
67 cpuid (20230120-1) unstable; urgency=medium
78