New upstream version 21.4.0+dfsg1
Sebastian Ramacher
2 years ago
| 20 | 20 | cmake_minimum_required(VERSION 3.5) |
| 21 | 21 | project(IntelMediaDriver) |
| 22 | 22 | |
| 23 | set(MEDIA_VERSION "21.3.4${MEDIA_VERSION_EXTRA}" CACHE STRING "" FORCE) | |
| 23 | set(MEDIA_VERSION "21.4.0${MEDIA_VERSION_EXTRA}" CACHE STRING "" FORCE) | |
| 24 | 24 | |
| 25 | 25 | include(os_release_info.cmake) |
| 26 | 26 |
| 72 | 72 | |
| 73 | 73 | ## Supported Platforms |
| 74 | 74 | |
| 75 | * BDW (Broadwell) | |
| 76 | * SKL (Skylake) | |
| 77 | * BXT (Broxton) / APL (Apollo Lake) | |
| 78 | * KBLx (KBL/Kaby Lake; CFL/Coffe Lake; WHL/Whiskey Lake; CML/Comet Lake; AML/Amber Lake) | |
| 79 | * ICL (Ice Lake) | |
| 80 | * JSL (Jasper Lake)/EHL (Elkhart Lake) | |
| 81 | * TGL (Tiger Lake) | |
| 82 | * DG1/SG1 | |
| 75 | - BDW (Broadwell) | |
| 76 | - SKL (Skylake) | |
| 77 | - BXTx (BXT: Broxton, APL: Apollo Lake, GLK: Gemini Lake) | |
| 78 | - KBLx (KBL: Kaby Lake, CFL: Coffe Lake, WHL: Whiskey Lake, CML: Comet Lake, AML: Amber Lake) | |
| 79 | - ICL (Ice Lake) | |
| 80 | - JSL (Jasper Lake) / EHL (Elkhart Lake) | |
| 81 | - TGLx (TGL: Tiger Lake, RKL: Rocket Lake, ADL-S/P: Alder Lake) | |
| 82 | - DG1/SG1 | |
| 83 | 83 | |
| 84 | 84 | |
| 85 | 85 | ## Components and Features |
| 86 | 86 | |
| 87 | 87 | Media driver contains three components as below |
| 88 | * **Video decoding** calls hardware-based decoder([VDBox](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol08-media_vdbox.pdf)) which provides fully-accelerated hardware video decoding to release the graphics engine for other operations. | |
| 89 | * **Video encoding** supports two modes, one calls hardware-based encoder([VDEnc](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol08-media_vdbox.pdf)/[Huc](https://01.org/linuxgraphics/downloads/firmware?langredirect=1)) to provide low power encoding, another one is hardware([PAK](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol08-media_vdbox.pdf))+shader(media kernel+[VME](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol04-configurations.pdf)) based encoding. User could choose the mode through VA-API. | |
| 90 | * **Video processing** supports several popular features by hardware-based video processor([VEBox/SFC](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol09-media_vebox.pdf)) and shader(media kernel) based solution together. | |
| 88 | - **Video decoding** calls hardware-based decoder([VDBox](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol08-media_vdbox.pdf)) which provides fully-accelerated hardware video decoding to release the graphics engine for other operations. | |
| 89 | - **Video encoding** supports two modes, one calls hardware-based encoder([VDEnc](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol08-media_vdbox.pdf)/[Huc](https://01.org/linuxgraphics/downloads/firmware?langredirect=1)) to provide low power encoding, another one is hardware([PAK](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol08-media_vdbox.pdf))+shader(media kernel+[VME](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol04-configurations.pdf)) based encoding. User could choose the mode through VA-API. | |
| 90 | - **Video processing** supports several popular features by hardware-based video processor([VEBox/SFC](https://01.org/sites/default/files/documentation/intel-gfx-prm-osrc-kbl-vol09-media_vebox.pdf)) and shader(media kernel) based solution together. | |
| 91 | 91 | |
| 92 | 92 | Media driver supports two build types as below |
| 93 | * **Full Feature Build** is default driver build, which supports all feature by hardware accelerator and close source shaders(media kernel binaries). Ubuntu [intel-media-va-driver-non-free](https://packages.ubuntu.com/disco/intel-media-va-driver-non-free) package is generated from this build type. | |
| 94 | * **Free Kernel Build**, enables fully open source shaders(media kernels) and hardware features but the features would be limited. Ubuntu [intel-media-va-driver](https://packages.ubuntu.com/disco/intel-media-va-driver) package is generated from this build type. | |
| 93 | - **Full Feature Build** is default driver build, which supports all feature by hardware accelerator and close source shaders(media kernel binaries). Ubuntu [intel-media-va-driver-non-free](https://packages.ubuntu.com/disco/intel-media-va-driver-non-free) package is generated from this build type. | |
| 94 | - **Free Kernel Build**, enables fully open source shaders(media kernels) and hardware features but the features would be limited. Ubuntu [intel-media-va-driver](https://packages.ubuntu.com/disco/intel-media-va-driver) package is generated from this build type. | |
| 95 | 95 | |
| 96 | 96 | |
| 97 | 97 | ### Decoding/Encoding Features |
| 98 | 98 | |
| 99 | 99 | |
| 100 | |CODEC | Build Types | BDW | SKL | BXT/APL | KBLx | ICL | EHL/JSL | TGL/RKL/ADL-S/ADL-P| DG1/SG1 | | |
| 100 | | CODEC | Build Types | DG1/SG1 | TGLx | EHL/JSL | ICL | KBLx | BXTx | SKL | BDW | | |
| 101 | 101 | |---|---|---|---|---|---|---|---|---|---| |
| 102 | | AVC | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/Es</u><br><i>D<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | | |
| 102 | | AVC | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/Es</u><br><i>D<i> | | |
| 103 | 103 | | MPEG-2 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | |
| 104 | 104 | | VC-1 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D</u><br><i> <i> | <u>D</u><br><i> <i> | <u>D</u><br><i> <i> | <u>D</u><br><i> <i> | <u>D</u><br><i> <i> | <u>D</u><br><i> <i> | <u>D</u><br><i> <i> | <u>D</u><br><i> <i> | |
| 105 | | JPEG | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D</u><br><i>D<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | | |
| 106 | | VP8 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D*</u><br><i>D*<i> | | | |
| 107 | | HEVC 8bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | | |
| 108 | | HEVC 8bit 422 | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | <u>D/Es</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | | |
| 109 | | HEVC 8bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | | |
| 110 | | HEVC 10bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | <u>D</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | | |
| 111 | | HEVC 10bit 422 | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | <u>D/Es</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | | |
| 112 | | HEVC 10bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | | |
| 113 | | HEVC 12bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | | | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | | |
| 114 | | HEVC 12bit 422 | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | | | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | | |
| 115 | | HEVC 12bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | | | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | | |
| 116 | | VP9 8bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | | |
| 117 | | VP9 8bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | | |
| 118 | | VP9 10bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | <u>D</u><br><i>D<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | | |
| 119 | | VP9 10bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | | |
| 120 | | VP9 12bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | | | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | | |
| 121 | | VP9 12bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | | | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | | |
| 122 | | AV1 8bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | | | <u>D</u><br><i>D**<i> | <u>D</u><br><i>D**<i> | | |
| 123 | | AV1 10bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | | | | | | | <u>D</u><br><i>D**<i> | <u>D</u><br><i>D**<i> | | |
| 124 | ||
| 125 | * D - Hardware Decoding | |
| 126 | * E - Hardware Encoding, Low Power Encoding(VDEnc/Huc) | |
| 127 | * Es - Hardware(PAK) + Shader(media kernel+VME) Encoding | |
| 128 | ||
| 129 | \* VP8 decoding is only supported on TGL platform | |
| 130 | ||
| 131 | \** AV1 film grain kernel is not open source yet which doesn't necessarily match the libaom algorithm or film grain synthesis. | |
| 132 | ||
| 133 | For more information, please refer to | |
| 134 | * [Media Features Summary](https://github.com/intel/media-driver/blob/master/docs/media_features.md#media-features-summary) | |
| 135 | * [Supported Decoding Output Format and Max Resolution](https://github.com/intel/media-driver/blob/master/docs/media_features.md#supported-decoding-output-format-and-max-resolution) | |
| 136 | * [Supported Encoding Input Format and Max Resolution](https://github.com/intel/media-driver/blob/master/docs/media_features.md#supported-encoding-input-format-and-max-resolution) | |
| 105 | | JPEG | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D</u><br><i>D<i> | | |
| 106 | | VP8 | <u>Full-Feature</u><br><i>Free-Kernel</i> | | <u>D*</u><br><i>D*<i> | <u>D</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | | |
| 107 | | HEVC 8bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | | | |
| 108 | | HEVC 8bit 422 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | | | | | | |
| 109 | | HEVC 8bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | | | | | | |
| 110 | | HEVC 10bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E/Es</u><br><i>D/E<i> | <u>D/Es</u><br><i>D<i> | <u>D</u><br><i>D<i> | | | | |
| 111 | | HEVC 10bit 422 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | <u>D</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | | | | | | |
| 112 | | HEVC 10bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | | | | | | |
| 113 | | HEVC 12bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/Es</u><br><i>D<i> | <u>D/Es</u><br><i>D<i> | | | | | | | | |
| 114 | | HEVC 12bit 422 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | | | | | | | | |
| 115 | | HEVC 12bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | | | | | | | | |
| 116 | | VP9 8bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | | | | |
| 117 | | VP9 8bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | | | | | | |
| 118 | | VP9 10bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D</u><br><i>D<i> | | | | | |
| 119 | | VP9 10bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | <u>D/E</u><br><i>D/E<i> | | | | | | |
| 120 | | VP9 12bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | | | | | | | | |
| 121 | | VP9 12bit 444 | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D</u><br><i>D<i> | <u>D</u><br><i>D<i> | | | | | | | | |
| 122 | | AV1 8bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D</u><br><i>D**<i> | <u>D</u><br><i>D**<i> | | | | | | | | |
| 123 | | AV1 10bit | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>D</u><br><i>D**<i> | <u>D</u><br><i>D**<i> | | | | | | | | |
| 124 | | | |
| 125 | ||
| 126 | - \* VP8 decoding is only supported on TGL platform | |
| 127 | - \** AV1 film grain kernel is not open source yet which doesn't necessarily match the libaom algorithm or film grain synthesis. | |
| 128 | - D - Hardware Decoding | |
| 129 | - E - Hardware Encoding, Low Power Encoding(VDEnc/Huc) | |
| 130 | - Es - Hardware(PAK) + Shader(media kernel+VME) Encoding | |
| 131 | ||
| 132 | ||
| 133 | ||
| 134 | For more decoding and encoding features information, please refer to | |
| 135 | - [Media Features Summary](https://github.com/intel/media-driver/blob/master/docs/media_features.md#media-features-summary) | |
| 136 | - [Supported Decoding Output Format and Max Resolution](https://github.com/intel/media-driver/blob/master/docs/media_features.md#supported-decoding-output-format-and-max-resolution) | |
| 137 | - [Supported Encoding Input Format and Max Resolution](https://github.com/intel/media-driver/blob/master/docs/media_features.md#supported-encoding-input-format-and-max-resolution) | |
| 137 | 138 | |
| 138 | 139 | ### Video Processing Features |
| 139 | 140 | |
| 140 | 141 | |
| 141 | | Features | Build Types | BDW | SKL | BXT/APL | KBLx | ICL | EHL/JSL | TGL/RKL/ADL-S/ADL-P | DG1/SG1 | | |
| 142 | |---|---|---|---|---|----|---|---|---|---| | |
| 143 | | Blending | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | | |
| 144 | | CSC<br>(Color Space Conversion) | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | | |
| 145 | | De-interlace | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i>Yes</i> | <u>Yes*</u><br><i>Yes*</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | | |
| 146 | | De-noise | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>No</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 147 | | Luma Key | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | | |
| 148 | | Mirroring | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | | |
| 149 | | ProcAmp<br>(brightness,contrast,hue,saturation) | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | | |
| 150 | | Rotation | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | | |
| 151 | | Scaling | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | | |
| 152 | | Sharpening | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | | |
| 153 | | STD/E<br>(Skin Tone Detect & Enhancement) | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>No</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 154 | | TCC<br>(Total Color Control) | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>No</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 155 | | Color fill | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | | |
| 156 | | Chroma Siting | <u>Full-Feature</u><br><i>Free-Kernel</i> | <br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | | |
| 157 | | HDR10 Tone Mapping | <u>Full-Feature</u><br><i>Free-Kernel</i> | <br><i> </i> | <br><i> </i> | <br><i> </i> | <br><i> </i> | <u>Yes</u><br><i> </i> | <u>No</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 158 | ||
| 159 | \* EHL/JSL only support BOB DI | |
| 142 | | CODEC | Build Types | DG1/SG1 | TGLx | EHL/JSL | ICL | KBLx | BXTx | SKL | BDW | | |
| 143 | |---|---|---|---|---|---|---|---|---|---| | |
| 144 | | Blending | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 145 | | CSC | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 146 | | De-interlace | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes*</u><br><i>Yes*</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 147 | | De-noise | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 148 | | Luma Key | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 149 | | Mirroring | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 150 | | ProcAmp | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 151 | | Rotation | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 152 | | Scaling | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 153 | | Sharpening | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 154 | | STD/E | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 155 | | TCC | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 156 | | Color fill | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | | |
| 157 | | Chroma Siting | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i>Yes</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <br><i> </i> | | |
| 158 | | HDR10 TM | <u>Full-Feature</u><br><i>Free-Kernel</i> | <u>Yes</u><br><i> </i> | <u>Yes</u><br><i> </i> | <br><i> </i> | <u>Yes</u><br><i> </i> | <br><i> </i> | <br><i> </i> | <br><i> </i> | <br><i> </i> | | |
| 159 | ||
| 160 | - \* EHL/JSL only support BOB DI | |
| 161 | - CSC: Color Space Conversion | |
| 162 | - ProcAmp: brightness,contrast,hue,saturation | |
| 163 | - STD/E: Skin Tone Detect & Enhancement | |
| 164 | - TCC: Total Color Control | |
| 165 | - HDR10 TM: HDR10 Tone Mapping | |
| 166 | ||
| 160 | 167 | |
| 161 | 168 | For more feature information, please refer to [Supported video processing csc/scaling format](https://github.com/intel/media-driver/blob/master/docs/media_features.md#supported-video-processing-cscscaling-format) |
| 162 | 169 | |
| 165 | 172 | |
| 166 | 173 | Media-driver supports few build types as described below. You could refer to |
| 167 | 174 | the following settings to enable them. |
| 168 | * **Full Feature Build**: ENABLE_KERNELS=ON(Default) ENABLE_NONFREE_KERNELS=ON(Default) | |
| 169 | * **Free Kernel Build**: ENABLE_KERNELS=ON ENABLE_NONFREE_KERNELS=OFF | |
| 170 | * If trying to use pre-built open source kernel binaries, please add BUILD_KERNELS=OFF(Default). | |
| 171 | * If trying to rebuild open source kernel from source code, please add BUILD_KERNELS=ON. | |
| 175 | - **Full Feature Build**: ENABLE_KERNELS=ON(Default) ENABLE_NONFREE_KERNELS=ON(Default) | |
| 176 | - **Free Kernel Build**: ENABLE_KERNELS=ON ENABLE_NONFREE_KERNELS=OFF | |
| 177 | - If trying to use pre-built open source kernel binaries, please add BUILD_KERNELS=OFF(Default). | |
| 178 | - If trying to rebuild open source kernel from source code, please add BUILD_KERNELS=ON. | |
| 172 | 179 | |
| 173 | 180 | Media-driver requires special i915 kernel mode driver (kmd) version to support the following |
| 174 | 181 | new platforms since upstream version of i915 kmd does not fully support them |
| 175 | 182 | (pending patches upstream): |
| 176 | * DG1 | |
| 177 | * SG1 | |
| 183 | - DG1 | |
| 184 | - SG1 | |
| 178 | 185 | |
| 179 | 186 | By default, media-driver builds against upstream i915 kmd and will miss |
| 180 | 187 | support for the platforms listed above. To enable new platforms which |
| 194 | 201 | * ICL: starting from kernel 5.2 |
| 195 | 202 | * EHL/JSL: starting from kernel 5.8 |
| 196 | 203 | * TGL: starting from kernel 5.9 |
| 197 | * RKL: [drm-tip](https://cgit.freedesktop.org/drm-tip) | |
| 204 | * RKL/ADL-S/ADL-P: [drm-tip](https://cgit.freedesktop.org/drm-tip) | |
| 198 | 205 | |
| 199 | 206 | ##### (*) Other names and brands may be claimed as property of others. |
| 1 | 1 | |
| 2 | 2 | ## Supported Decoding Output Format and Max Resolution |
| 3 | 3 | |
| 4 | (2k=2048x2048, 4k=4096x4096, 8k=8192x8192, 16k=16384x16384) | |
| 4 | | Codec | Type | DG1/SG1 | TGLx | ICL | KBLx | BXTx | SKL | BDW | | |
| 5 | |------------|----------|----------------|----------------|----------------|------|------|------|------| | |
| 6 | | AVC | Output | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | | |
| 7 | | | Max Res. | 4k | 4k | 4k | 4k | 4k | 4k | 4k | | |
| 8 | | MPEG-2 | Output | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | | |
| 9 | | | Max Res. | 2k | 2k | 2k | 2k | 2k | 2k | 2k | | |
| 10 | | VC-1 | Output | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | | |
| 11 | | | Max Res. | 4k | 4k | 4k | 4k | 4k | 4k | 4k | | |
| 12 | | VP8 | Output | | NV12* | NV12 | NV12 | NV12 | NV12 | NV12 | | |
| 13 | | | Max Res. | | 4k* | 4k | 4k | 4k | 4k | 4k | | |
| 14 | | HEVC 8bit | Output | NV12/YUY2/AYUV | NV12/YUY2/AYUV | NV12/YUY2/AYUV | NV12 | NV12 | NV12 | | | |
| 15 | | | Max Res. | 8k | 8k | 8k | 8k | 8k | 8k | | | |
| 16 | | HEVC 10bit | Output | P010/Y210/Y410 | P010/Y210/Y410 | P010/Y210/Y410 | P010 | P010 | | | | |
| 17 | | | Max Res. | 8k | 8k | 8k | 8k | 8k | | | | |
| 18 | | HEVC 12bit | Output | P016/Y216/Y416 | P016/Y216/Y416 | | | | | | | |
| 19 | | | Max Res. | 8k | 8k | | | | | | | |
| 20 | | VP9 8bit | Output | NV12/AYUV | NV12/AYUV | NV12/AYUV | NV12 | NV12 | | | | |
| 21 | | | Max Res. | 8k | 8k | 8k | 8k | 4k | | | | |
| 22 | | VP9 10bit | Output | P010/Y410 | P010/Y410 | P010/Y410 | P010 | | | | | |
| 23 | | | Max Res. | 8k | 8k | 8k | 8k | | | | | |
| 24 | | VP9 12bit | Output | P016/Y216/Y416 | P016/Y216/Y416 | | | | | | | |
| 25 | | | Max Res. | 8k | 8k | | | | | | | |
| 26 | | AV1 8bit | Output | NV12 | NV12 | | | | | | | |
| 27 | | | Max Res. | 8k | 8k | | | | | | | |
| 28 | | AV1 10bit | Output | P010 | P010 | | | | | | | |
| 29 | | | Max Res. | 8k | 8k | | |
| 5 | 30 | |
| 31 | - \* VP8 is only supported on TGL platform | |
| 6 | 32 | |
| 7 | | Codec | Type | BDW | SKL | BXT/APL | KBLx | ICL | TGL/RKL/ADL-S/ADL-P | DG1/SG1 | | |
| 8 | |---|---|---|---|---|---|---|---|---| | |
| 9 | | AVC | Output | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | | |
| 10 | | | Max Res. | 4k | 4k | 4k | 4k | 4k | 4k | 4k | | |
| 11 | | MPEG-2 | Output | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | | |
| 12 | | | Max Res. | 2k | 2k | 2k | 2k | 2k | 2k | 2k | | |
| 13 | | VC-1 | Output | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | | |
| 14 | | | Max Res. | 4k | 4k | 4k | 4k | 4k | 4k | 4k | | |
| 15 | | JPEG* | Max Res. | 16k | 16k | 16k | 16k | 16k | 16k | 16k | | |
| 16 | | VP8 | Output | NV12 | NV12 | NV12 | NV12 | NV12 | NV12** | | | |
| 17 | | | Max Res. | 4k | 4k | 4k | 4k | 4k | 4k** | | | |
| 18 | | HEVC 8bit | Output | | NV12 | NV12 | NV12 | NV12/YUY2/AYUV | NV12/YUY2/AYUV | NV12/YUY2/AYUV | | |
| 19 | | | Max Res. | | 8k | 8k | 8k | 8k | 8k | 8k | | |
| 20 | | HEVC 10bit | Output | | | P010 | P010 | P010/Y210/Y410 | P010/Y210/Y410 | P010/Y210/Y410 | | |
| 21 | | | Max Res. | | | 8k | 8k | 8k | 8k | 8k | | |
| 22 | | HEVC 12bit | Output | | | | | | P016/Y216/Y416 | P016/Y216/Y416 | | |
| 23 | | | Max Res. | | | | | | 8k | 8k | | |
| 24 | | VP9 8bit | Output | | | NV12 | NV12 | NV12/AYUV | NV12/AYUV | NV12/AYUV | | |
| 25 | | | Max Res. | | | 4k | 8k | 8k | 8k | 8k | | |
| 26 | | VP9 10bit | Output | | | | P010 | P010/Y410 | P010/Y410 | P010/Y410 | | |
| 27 | | | Max Res. | | | | 8k | 8k | 8k | 8k | | |
| 28 | | VP9 12bit | Output | | | | | | P016/Y216/Y416 | P016/Y216/Y416 | | |
| 29 | | | Max Res. | | | | | | 8k | 8k | | |
| 30 | | AV1 8bit | Output | | | | | | NV12 | NV12 | | |
| 31 | | | Max Res. | | | | | | 8k | 8k | | |
| 32 | | AV1 10bit | Output | | | | | | P010 | P010 | | |
| 33 | | | Max Res. | | | | | | 8k | 8k | | |
| 34 | ||
| 35 | * \* JPEG output format: NV12/411P/422H/422V/444P/BGRP/RGBP/YUY2/ARGB | |
| 36 | * \** VP8 is only supported on TGL platform | |
| 33 | ### JPEG Decoding Format Support | |
| 34 | | Input Format | Output Format | Max resolution | Supported Platforms | | |
| 35 | |------------------------------------------------------|---------------|----------------|---------------------| | |
| 36 | | 4:2:0, 8-bit | IMC3 | 16K | BDW+ | | |
| 37 | | 4:2:2, 8-bit | 422H | 16K | BDW+ | | |
| 38 | | 4:2:2, 8-bit | 422V | 16K | BDW+ | | |
| 39 | | 4:1:1, 8-bit | 411P | 16K | BDW+ | | |
| 40 | | 4:4:4, 8-bit | 444P | 16K | BDW+ | | |
| 41 | | 4:4:4, 8-bit | RGBP / BGRP | 16K | BDW+ | | |
| 42 | | 4:0:0, 8-bit | 400P | 16K | BDW+ | | |
| 43 | | 420 / 422H<br/>interleaved single scan | YUY2 | 16K | BDW+ | | |
| 44 | | 420 / 422H<br/>interleaved single scan | UYVY | 16K | BDW+ | | |
| 45 | | 420 / 422H / 422<br/>interleaved single scanV | NV12 | 16K | BDW+ | | |
| 46 | | 400/420/422H/444/RGB/BGR<br/>interleaved single scan | A8R8G8B8 | 16K | SKL+ | | |
| 37 | 47 | |
| 38 | 48 | ## Supported Encoding Input Format and Max Resolution |
| 39 | 49 | |
| 40 | 50 | ### Hardware Encoding, Low Power Encoding(VDEnc/Huc) |
| 41 | 51 | |
| 42 | (4k=4096x4096, 16k=16384x16384) | |
| 52 | | Codec | Type | DG1/SG1 | TGLx | ICL | KBLx | BXTx | SKL | BDW | | |
| 53 | |------------|--------------|-----------|-----------|-----------|--------|--------|--------|-----| | |
| 54 | | AVC | Input | *More | *More | *More | *More | NV12 | NV12 | | | |
| 55 | | | Max Res. | 4k | 4k | 4k | 4k | 4k | 4k | | | |
| 56 | | JPEG | Input/Output | **Note | **Note | **Note | **Note | **Note | **Note | | | |
| 57 | | | Max Res. | 16k | 16k | 16k | 16k | 16k | 16k | | | |
| 58 | | HEVC 8bit | Input | NV12/AYUV | NV12/AYUV | NV12/AYUV | | | | | | |
| 59 | | | Max Res. | 8K | 8K | 8K | | | | | | |
| 60 | | HEVC 10bit | Input | P010/Y410 | P010/Y410 | P010/Y410 | | | | | | |
| 61 | | | Max Res. | 8k | 8k | 8k | | | | | | |
| 62 | | VP9 8bit | Input | NV12/AYUV | NV12/AYUV | NV12/AYUV | | | | | | |
| 63 | | | Max Res. | 8k | 8k | 8k | | | | | | |
| 64 | | VP9 10bit | Input | P010/Y410 | P010/Y410 | P010/Y410 | | | | | | |
| 65 | | | Max Res. | 8k | 8k | 8k | | |
| 43 | 66 | |
| 44 | ||
| 45 | | Codec | Type | BDW | SKL | BXT/APL | KBLx | ICL | TGL/RKL/ADL-S/ADL-P | DG1/SG1 | | |
| 46 | |---|---|---|---|---|---|---|---|---| | |
| 47 | | AVC | Input | | NV12 | NV12 | More* | More* | More* | More* | | |
| 48 | | | Max Res. | | 4k | 4k | 4k | 4k | 4k | 4k | | |
| 49 | | JPEG | Input/Output | | Note** | Note** | Note** | Note** | Note** | Note** | | |
| 50 | | | Max Res. | | 16k | 16k | 16k | 16k | 16k | 16k | | |
| 51 | | HEVC 8bit | Input | | | | | NV12/AYUV | NV12/AYUV | NV12/AYUV | | |
| 52 | | | Max Res. | | | | | 8K | 8K | 8K | | |
| 53 | | HEVC 10bit | Input | | | | | P010/Y410 | P010/Y410 | P010/Y410 | | |
| 54 | | | Max Res. | | | | | 8k | 8k | 8k | | |
| 55 | | VP9 8bit | Input | | | | | NV12/AYUV | NV12/AYUV | NV12/AYUV | | |
| 56 | | | Max Res. | | | | | 8k | 8k | 8k | | |
| 57 | | VP9 10bit | Input | | | | | P010/Y410 | P010/Y410 | P010/Y410 | | |
| 58 | | | Max Res. | | | | | 8k | 8k | 8k | | |
| 59 | ||
| 60 | * \* KBL/CFL/ICL/TGL AVC encoding supported input formats: NV12/YUY2/YUYV/YVYU/UYVY/AYUV/ARGB | |
| 61 | * \** JPEG encoding supports input format NV12/YUY2/UYVY/AYUV/ABGR/Y8 and output format YUV400/YUV420/YUV422H_2Y/YUV444/RGB24. | |
| 67 | - \*More: KBL/CFL/ICL/TGL AVC encoding supported input formats: NV12/YUY2/YUYV/YVYU/UYVY/AYUV/ARGB | |
| 68 | - \**Note: JPEG encoding supports input format NV12/YUY2/UYVY/AYUV/ABGR/Y8 and output format YUV400/YUV420/YUV422H_2Y/YUV444/RGB24. | |
| 62 | 69 | |
| 63 | 70 | |
| 64 | 71 | ### Hardware(PAK) + Shader(media kernel+VME) Encoding |
| 65 | 72 | |
| 66 | (2k=2048x2048, 4k=4096x4096, 8k=8192x8192) | |
| 67 | ||
| 68 | ||
| 69 | | Codec | Type | BDW | SKL | BXT/APL | KBLx | ICL | TGL/RKL/ADL-S/ADL-P | DG1/SG1 | | |
| 70 | |---|---|---|---|---|---|---|---|---| | |
| 71 | | AVC | Input | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | | |
| 72 | | | Max Res. | 4k | 4k | 4k | 4k | 4k | 4k | 4k | | |
| 73 | | MPEG2 | Input | NV12 | NV12 | | NV12 | NV12 | NV12 | NV12 | | |
| 74 | | | Max Res. | 2k | 2k | | 2k | 2k | 2k | 2k | | |
| 75 | | VP8 | Input | | | | NV12 | NV12 | NV12 | NV12 | | |
| 76 | | | Max Res. | | | | 4k | 4k | 4k | 4k | | |
| 77 | | HEVC 8bit | Input | | NV12 | NV12 | NV12 | NV12/AYUV | NV12/AYUV | NV12/AYUV | | |
| 78 | | | Max Res. | | 4k | 4k | 4k | 8k | 8k | 8k | | |
| 79 | | HEVC 10bit | Input | | | | | P010/Y410 | P010/Y410 | P010/Y410 | | |
| 80 | | | Max Res. | | | | | 8k | 8k | 8k | | |
| 81 | ||
| 73 | | Codec | Type | DG1/SG1 | TGLx | ICL | KBLx | BXTx | SKL | BDW | | |
| 74 | |------------|----------|-----------|-----------|-----------|------|------|------|------| | |
| 75 | | AVC | Input | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | NV12 | | |
| 76 | | | Max Res. | 4k | 4k | 4k | 4k | 4k | 4k | 4k | | |
| 77 | | MPEG2 | Input | NV12 | NV12 | NV12 | NV12 | | NV12 | NV12 | | |
| 78 | | | Max Res. | 2k | 2k | 2k | 2k | | 2k | 2k | | |
| 79 | | VP8 | Input | NV12 | NV12 | NV12 | NV12 | | | | | |
| 80 | | | Max Res. | 4k | 4k | 4k | 4k | | | | | |
| 81 | | HEVC 8bit | Input | NV12/AYUV | NV12/AYUV | NV12/AYUV | NV12 | NV12 | NV12 | | | |
| 82 | | | Max Res. | 8k | 8k | 8k | 4k | 4k | 4k | | | |
| 83 | | HEVC 10bit | Input | P010/Y410 | P010/Y410 | P010/Y410 | | | | | | |
| 84 | | | Max Res. | 8k | 8k | 8k | | |
| 82 | 85 | |
| 83 | 86 | ## Supported Video Processing CSC/Scaling Format |
| 84 | 87 | |
| 85 | | Platform | Format | NV12 | YV12 | I420 | P010 | YUY2 | UYVY | Y210 | AYUV | Y410 | P016*| Y216*| Y416*| | |
| 86 | |-----------------------|--------|------|------|------|------|------|------|------|------|------|------|------|------| | |
| 87 | | BDW | Input | Y | Y | Y | | Y | | | | | | | | | |
| 88 | | | Output | Y | Y | Y | | Y | | | | | | | | | |
| 89 | |SKL/BXT/KBL/CFL/WHL/CML| Input | Y | Y | Y | Y | Y | | | | | | | | | |
| 90 | | | Output | Y | Y | Y | | Y | | | | | | | | | |
| 91 | | ICL | Input | Y | Y | Y | Y | Y | Y | Y | Y | Y | | | | | |
| 92 | | | Output | Y | Y | Y | Y | Y | | Y | Y | Y | | | | | |
| 93 | | JSL/EHL | Input | Y | Y | Y | Y | Y | Y | Y | Y | Y | | | | | |
| 94 | | | Output | Y | Y | Y | Y | Y | | Y | Y | Y | | | | | |
| 95 | | TGL/RKL/ADL-S/ADL-P | Input | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | | |
| 96 | | | Output | Y | Y | Y | Y | Y | | Y | Y | Y | Y | Y | Y | | |
| 97 | | DG1/SG1 | Input | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | | |
| 98 | | | Output | Y | Y | Y | Y | Y | | Y | Y | Y | Y | Y | Y | | |
| 88 | | Platform | Format | NV12 | YV12 | I420 | P010 | YUY2 | UYVY | Y210 | AYUV | Y410 | P016* | Y216* | Y416* | | |
| 89 | |---------------|--------|------|------|------|------|------|------|------|------|------|-------|-------|-------| | |
| 90 | | BDW | Input | Y | Y | Y | | Y | | | | | | | | | |
| 91 | | | Output | Y | Y | Y | | Y | | | | | | | | | |
| 92 | | SKL/BXTx/KBLx | Input | Y | Y | Y | Y | Y | | | | | | | | | |
| 93 | | | Output | Y | Y | Y | | Y | | | | | | | | | |
| 94 | | ICL | Input | Y | Y | Y | Y | Y | Y | Y | Y | Y | | | | | |
| 95 | | | Output | Y | Y | Y | Y | Y | | Y | Y | Y | | | | | |
| 96 | | JSL/EHL | Input | Y | Y | Y | Y | Y | Y | Y | Y | Y | | | | | |
| 97 | | | Output | Y | Y | Y | Y | Y | | Y | Y | Y | | | | | |
| 98 | | TGLx | Input | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | | |
| 99 | | | Output | Y | Y | Y | Y | Y | | Y | Y | Y | Y | Y | Y | | |
| 100 | | DG1/SG1 | Input | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | Y | | |
| 101 | | | Output | Y | Y | Y | Y | Y | | Y | Y | Y | Y | Y | | |
| 99 | 102 | |
| 100 | * \* For SFC path, there are NOT real 16bit, SFC precision is 12bit; For kernel path, we support real 16bit.⏎ | |
| 103 | * \* For SFC path, there are NOT real 16bit, SFC precision is 12bit; For kernel path, we support real 16bit. | |
| 104 | ||
| 105 | ##### Resolution definition: 2k=2048x2048, 4k=4096x4096, 8k=8192x8192, 16k=16384x16384⏎ |
| 27 | 27 | #define __CODEC_DEF_COMMON_H__ |
| 28 | 28 | |
| 29 | 29 | #include "mos_defs.h" |
| 30 | #include "mos_os_next.h" | |
| 30 | #include "mos_os.h" | |
| 31 | 31 | #include <math.h> |
| 32 | 32 | |
| 33 | 33 | #define CODEC_MAX_NUM_REF_FRAME 16 |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_avc.h | |
| 23 | //! \brief Defines basic AVC types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details This is the base header for all codec_def AVC files. All codec_def AVC files should include this file which should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_AVC_H__ | |
| 27 | #define __CODEC_DEF_COMMON_AVC_H__ | |
| 28 | ||
| 29 | #include "codec_def_common.h" | |
| 30 | ||
| 31 | #define CODEC_AVC_MAX_NUM_REF_FRAME 16 | |
| 32 | #define CODEC_AVC_NUM_REF_LISTS 2 | |
| 33 | #define CODEC_AVC_NUM_REF_DMV_BUFFERS (CODEC_AVC_MAX_NUM_REF_FRAME + 1) // Max 16 references + 1 for the current frame | |
| 34 | #define CODEC_AVC_NUM_DMV_BUFFERS (CODEC_AVC_NUM_REF_DMV_BUFFERS + 1) // 1 for non-reference | |
| 35 | #define CODEC_AVC_NUM_INIT_DMV_BUFFERS 4 | |
| 36 | ||
| 37 | #define CODEC_MAX_NUM_REF_FIELD (CODEC_MAX_NUM_REF_FRAME * CODEC_NUM_FIELDS_PER_FRAME) | |
| 38 | #define CODEC_AVC_MAX_SPS_NUM 32 | |
| 39 | #define CODEC_AVC_MAX_PPS_NUM 255 | |
| 40 | ||
| 41 | #define CODEC_AVC_NUM_UNCOMPRESSED_SURFACE 128 // 7 bits | |
| 42 | ||
| 43 | //! | |
| 44 | //! \enum CODEC_AVC_WEIGHT_SCALE_SIZE | |
| 45 | //! \brief Codec AVC weight scale size | |
| 46 | //! | |
| 47 | enum CODEC_AVC_WEIGHT_SCALE_SIZE | |
| 48 | { | |
| 49 | CODEC_AVC_WEIGHT_SCALE_4x4 = 24, | |
| 50 | CODEC_AVC_WEIGHT_SCALE_8x8 = 32, | |
| 51 | CODEC_AVC_WEIGHT_SCALE = 56 | |
| 52 | }; | |
| 53 | ||
| 54 | typedef enum | |
| 55 | { | |
| 56 | CODEC_AVC_BASE_PROFILE = 66, | |
| 57 | CODEC_AVC_MAIN_PROFILE = 77, | |
| 58 | CODEC_AVC_EXTENDED_PROFILE = 88, | |
| 59 | CODEC_AVC_HIGH_PROFILE = 100, | |
| 60 | CODEC_AVC_HIGH10_PROFILE = 110, | |
| 61 | CODEC_AVC_HIGH422_PROFILE = 122, | |
| 62 | CODEC_AVC_HIGH444_PROFILE = 244, | |
| 63 | CODEC_AVC_CAVLC444_INTRA_PROFILE = 44, | |
| 64 | CODEC_AVC_SCALABLE_BASE_PROFILE = 83, | |
| 65 | CODEC_AVC_SCALABLE_HIGH_PROFILE = 86 | |
| 66 | } CODEC_AVC_PROFILE_IDC; | |
| 67 | ||
| 68 | typedef enum | |
| 69 | { | |
| 70 | CODEC_AVC_LEVEL_1 = 10, | |
| 71 | CODEC_AVC_LEVEL_1b = 9, | |
| 72 | CODEC_AVC_LEVEL_11 = 11, | |
| 73 | CODEC_AVC_LEVEL_12 = 12, | |
| 74 | CODEC_AVC_LEVEL_13 = 13, | |
| 75 | CODEC_AVC_LEVEL_2 = 20, | |
| 76 | CODEC_AVC_LEVEL_21 = 21, | |
| 77 | CODEC_AVC_LEVEL_22 = 22, | |
| 78 | CODEC_AVC_LEVEL_3 = 30, | |
| 79 | CODEC_AVC_LEVEL_31 = 31, | |
| 80 | CODEC_AVC_LEVEL_32 = 32, | |
| 81 | CODEC_AVC_LEVEL_4 = 40, | |
| 82 | CODEC_AVC_LEVEL_41 = 41, | |
| 83 | CODEC_AVC_LEVEL_42 = 42, | |
| 84 | CODEC_AVC_LEVEL_5 = 50, | |
| 85 | CODEC_AVC_LEVEL_51 = 51, | |
| 86 | CODEC_AVC_LEVEL_52 = 52 | |
| 87 | } CODEC_AVC_LEVEL_IDC; | |
| 88 | ||
| 89 | // H.264 Inverse Quantization Matrix Buffer | |
| 90 | typedef struct _CODEC_AVC_IQ_MATRIX_PARAMS | |
| 91 | { | |
| 92 | uint8_t ScalingList4x4[6][16]; | |
| 93 | uint8_t ScalingList8x8[2][64]; | |
| 94 | } CODEC_AVC_IQ_MATRIX_PARAMS, *PCODEC_AVC_IQ_MATRIX_PARAMS; | |
| 95 | ||
| 96 | typedef struct _CODEC_AVC_FRAME_STORE_ID | |
| 97 | { | |
| 98 | bool inUse; | |
| 99 | bool reUse; | |
| 100 | } CODEC_AVC_FRAME_STORE_ID, *PCODEC_AVC_FRAME_STORE_ID; | |
| 101 | ||
| 102 | const uint8_t CODEC_AVC_Qmatrix_scan_4x4[16] = | |
| 103 | { | |
| 104 | 0, 1, 4, 8, 5, 2, 3, 6, 9, 12, 13, 10, 7, 11, 14, 15 | |
| 105 | }; | |
| 106 | ||
| 107 | const uint8_t CODEC_AVC_Qmatrix_scan_8x8[64] = | |
| 108 | { | |
| 109 | 0, 1, 8, 16, 9, 2, 3, 10, 17, 24, 32, 25, 18, 11, 4, 5, | |
| 110 | 12, 19, 26, 33, 40, 48, 41, 34, 27, 20, 13, 6, 7, 14, 21, 28, | |
| 111 | 35, 42, 49, 56, 57, 50, 43, 36, 29, 22, 15, 23, 30, 37, 44, 51, | |
| 112 | 58, 59, 52, 45, 38, 31, 39, 46, 53, 60, 61, 54, 47, 55, 62, 63 | |
| 113 | }; | |
| 114 | ||
| 115 | const uint8_t CODEC_AVC_Default_4x4_Intra[16] = | |
| 116 | { | |
| 117 | 6, 13, 13, 20, 20, 20, 28, 28, 28, 28, 32, 32, 32, 37, 37, 42 | |
| 118 | }; | |
| 119 | ||
| 120 | const uint8_t CODEC_AVC_Default_4x4_Inter[16] = | |
| 121 | { | |
| 122 | 10, 14, 14, 20, 20, 20, 24, 24, 24, 24, 27, 27, 27, 30, 30, 34 | |
| 123 | }; | |
| 124 | ||
| 125 | const uint8_t CODEC_AVC_Default_8x8_Intra[64] = | |
| 126 | { | |
| 127 | 6, 10, 10, 13, 11, 13, 16, 16, 16, 16, 18, 18, 18, 18, 18, 23, | |
| 128 | 23, 23, 23, 23, 23, 25, 25, 25, 25, 25, 25, 25, 27, 27, 27, 27, | |
| 129 | 27, 27, 27, 27, 29, 29, 29, 29, 29, 29, 29, 31, 31, 31, 31, 31, | |
| 130 | 31, 33, 33, 33, 33, 33, 36, 36, 36, 36, 38, 38, 38, 40, 40, 42 | |
| 131 | }; | |
| 132 | ||
| 133 | const uint8_t CODEC_AVC_Default_8x8_Inter[64] = | |
| 134 | { | |
| 135 | 9, 13, 13, 15, 13, 15, 17, 17, 17, 17, 19, 19, 19, 19, 19, 21, | |
| 136 | 21, 21, 21, 21, 21, 22, 22, 22, 22, 22, 22, 22, 24, 24, 24, 24, | |
| 137 | 24, 24, 24, 24, 25, 25, 25, 25, 25, 25, 25, 27, 27, 27, 27, 27, | |
| 138 | 27, 28, 28, 28, 28, 28, 30, 30, 30, 30, 32, 32, 32, 33, 33, 35 | |
| 139 | }; | |
| 140 | #endif // __CODEC_DEF_COMMON_AVC_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017-2019, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_encode.h | |
| 23 | //! \brief Defines common types and macros shared by CodecHal, MHW, and DDI layer for encode. | |
| 24 | //! \details All codec_def_encode may include this file which should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_ENCODE_H__ | |
| 27 | #define __CODEC_DEF_COMMON_ENCODE_H__ | |
| 28 | ||
| 29 | #include "mos_defs.h" | |
| 30 | ||
| 31 | #define CODEC_NUM_REF_BUFFERS (CODEC_MAX_NUM_REF_FRAME + 1) // Max 16 references (for AVC) + 1 for the current frame | |
| 32 | #define CODEC_NUM_NON_REF_BUFFERS 3 | |
| 33 | #define CODEC_NUM_TRACKED_BUFFERS (CODEC_NUM_REF_BUFFERS + CODEC_NUM_NON_REF_BUFFERS) | |
| 34 | #define CODEC_CURR_TRACKED_BUFFER CODEC_NUM_TRACKED_BUFFERS | |
| 35 | ||
| 36 | //BRC | |
| 37 | #define BRC_IMG_STATE_SIZE_PER_PASS 128 | |
| 38 | #define BRC_IMG_STATE_SIZE_PER_PASS_G10 144 | |
| 39 | #define BRC_IMG_STATE_SIZE_PER_PASS_G11 192 | |
| 40 | ||
| 41 | // Quality/Performance differentiators for HSW AVC Encode | |
| 42 | #define NUM_TARGET_USAGE_MODES 8 | |
| 43 | #define NUM_VDENC_TARGET_USAGE_MODES 8 | |
| 44 | ||
| 45 | //weighted prediction | |
| 46 | #define CODEC_NUM_WP_FRAME 8 | |
| 47 | #define CODEC_MAX_FORWARD_WP_FRAME 6 | |
| 48 | #define CODEC_MAX_BACKWARD_WP_FRAME 2 | |
| 49 | #define CODEC_WP_OUTPUT_L0_START 0 | |
| 50 | #define CODEC_WP_OUTPUT_L1_START 6 | |
| 51 | ||
| 52 | #define CODEC_720P_MAX_PIC_WIDTH 1280 | |
| 53 | #define CODEC_720P_MAX_PIC_HEIGHT 1280 | |
| 54 | ||
| 55 | #define CODEC_MAX_PIC_WIDTH 1920 | |
| 56 | #define CODEC_MAX_PIC_HEIGHT 1920 // Tablet usage in portrait mode, image resolution = 1200x1920, so change MAX_HEIGHT to 1920 | |
| 57 | ||
| 58 | #define CODEC_2K_MAX_PIC_WIDTH 2048 | |
| 59 | #define CODEC_2K_MAX_PIC_HEIGHT 2048 | |
| 60 | ||
| 61 | #define CODEC_4K_MAX_PIC_WIDTH 4096 | |
| 62 | #define CODEC_4K_MAX_PIC_HEIGHT 4096 | |
| 63 | ||
| 64 | #define CODEC_8K_MAX_PIC_WIDTH 8192 | |
| 65 | #define CODEC_8K_MAX_PIC_HEIGHT 8192 | |
| 66 | ||
| 67 | #define CODEC_16K_MAX_PIC_WIDTH 16384 | |
| 68 | #define CODEC_12K_MAX_PIC_HEIGHT 12288 | |
| 69 | #define CODEC_16K_MAX_PIC_HEIGHT 16384 | |
| 70 | ||
| 71 | #define CODECHAL_MAD_BUFFER_SIZE 4 // buffer size is 4 bytes | |
| 72 | ||
| 73 | #define CODEC_128_MIN_PIC_WIDTH 128 | |
| 74 | #define CODEC_96_MIN_PIC_HEIGHT 96 | |
| 75 | ||
| 76 | // HME | |
| 77 | #define SCALE_FACTOR_2x 2 | |
| 78 | #define SCALE_FACTOR_4x 4 | |
| 79 | #define SCALE_FACTOR_16x 16 | |
| 80 | #define SCALE_FACTOR_32x 32 | |
| 81 | ||
| 82 | #define CODECHAL_VP9_MB_CODE_SIZE 204 | |
| 83 | ||
| 84 | typedef struct tagENCODE_RECT | |
| 85 | { | |
| 86 | uint16_t Top; // [0..(FrameHeight+ M-1)/M -1] | |
| 87 | uint16_t Bottom; // [0..(FrameHeight+ M-1)/M -1] | |
| 88 | uint16_t Left; // [0..(FrameWidth+15)/16-1] | |
| 89 | uint16_t Right; // [0..(FrameWidth+15)/16-1] | |
| 90 | } ENCODE_RECT; | |
| 91 | ||
| 92 | typedef struct tagMOVE_RECT | |
| 93 | { | |
| 94 | uint32_t SourcePointX; | |
| 95 | uint32_t SourcePointY; | |
| 96 | uint32_t DestRectTop; | |
| 97 | uint32_t DestRectBottom; | |
| 98 | uint32_t DestRectLeft; | |
| 99 | uint32_t DestRectRight; | |
| 100 | } MOVE_RECT; | |
| 101 | ||
| 102 | /*! \brief Defines ROI settings. | |
| 103 | * | |
| 104 | * {Top, Bottom, Left, Right} defines the ROI boundary. The values are in unit of blocks. The block size M should use LCU size (e.g. sif LCU size is 32x32, M is 32). And its range should be within the frame boundary, so that: | |
| 105 | * 0 <= Top <= Bottom <= (FrameHeight+ M-1)/M -1 | |
| 106 | * 0 <= Left <= Right <= (FrameWidth+M-1)/M-1 | |
| 107 | * If input range is out of frame boundary, driver should trim it. | |
| 108 | * ROI alignes with LCU based rectangular blocks and cannot have arbitrary pixel-based location. | |
| 109 | * Region overlapping is allowed. For MBs reside within more than one ROIs, parameters from ROI with smaller index rules. For example, when ROI[0] and ROI[1] overlap on a certain area, the QP value for the overlapped area will be determined by value of ROI[0]. The order of ROI[] reflects objects’ relative relationship of depth. Foreground objects should have ROI index smaller than background objects. | |
| 110 | */ | |
| 111 | typedef struct _CODEC_ROI | |
| 112 | { | |
| 113 | uint16_t Top; //!< [0..(FrameHeight+15)/16-1] | |
| 114 | uint16_t Bottom; //!< [0..(FrameHeight+15)/16-1] | |
| 115 | uint16_t Left; //!< [0..(FrameWidth+15)/16-1] | |
| 116 | uint16_t Right; //!< [0..(FrameWidth+15)/16-1] | |
| 117 | /*! \brief For ROIValueInDeltaQP equals CQP case, this parameter gives explicit delta QP value of ROI regional QP vs. frame QP. | |
| 118 | * | |
| 119 | * Value range [-51..51]. If regional QP PriorityLevelOfDQp + QpY is out of range of [0..51], driver should crop it. It could be applied on both CQP and BRC cases. For ROIValueInDeltaQP equals 0BRC cases, this parameter describes the priority level of the ROI region. Value range [-3..3]. The higher the absolute value, the bigger range of delta QP is allowed. And it is usually applies on BRC case. BRC will decide the actual delta QP value. Positive priority level means negative delta QP should be applied. And negative priority level means positive delta QP which implies the region should be intentionally blurred. In either case, value Priority level 0 means same as non-ROI region. It is suggested that application does not set value 0. But if it happens, driver will treat that ROI as part of non-ROI background. | |
| 120 | */ | |
| 121 | char PriorityLevelOrDQp; | |
| 122 | } CODEC_ROI, *PCODEC_ROI; | |
| 123 | ||
| 124 | /*! \brief Indicates the uncompressed input color space | |
| 125 | * | |
| 126 | * Valid only when input is ARGB format. | |
| 127 | */ | |
| 128 | typedef enum _CODEC_INPUT_COLORSPACE | |
| 129 | { | |
| 130 | ECOLORSPACE_P709 = 0, | |
| 131 | ECOLORSPACE_P601 = 1, | |
| 132 | ECOLORSPACE_P2020 = 2 | |
| 133 | } CODEC_INPUT_COLORSPACE, ENCODE_INPUT_COLORSPACE; | |
| 134 | ||
| 135 | /*! \brief Indicates the tolerance the application has to variations in the frame size. | |
| 136 | * | |
| 137 | * For example, wireless display scenarios may require very steady bitrate to reduce buffering time. It affects the BRC algorithm used, but may or may not have an effect based on the combination of other BRC parameters. Only valid when the driver reports support for FrameSizeToleranceSupport. | |
| 138 | */ | |
| 139 | typedef enum _CODEC_FRAMESIZE_TOLERANCE | |
| 140 | { | |
| 141 | EFRAMESIZETOL_NORMAL = 0, | |
| 142 | EFRAMESIZETOL_LOW = 1, //!< Maps to "sliding window" | |
| 143 | EFRAMESIZETOL_EXTREMELY_LOW = 2 //!< Maps to "low delay" | |
| 144 | } CODEC_FRAMESIZE_TOLERANCE, ENCODE_FRAMESIZE_TOLERANCE; | |
| 145 | ||
| 146 | /*! \brief Provides a hint to encoder about the scenario for the encoding session. | |
| 147 | * | |
| 148 | * BRC algorithm may tune differently based on this info. | |
| 149 | */ | |
| 150 | typedef enum _CODEC_SCENARIO | |
| 151 | { | |
| 152 | ESCENARIO_UNKNOWN = 0, | |
| 153 | ESCENARIO_DISPLAYREMOTING = 1, | |
| 154 | ESCENARIO_VIDEOCONFERENCE = 2, | |
| 155 | ESCENARIO_ARCHIVE = 3, | |
| 156 | ESCENARIO_LIVESTREAMING = 4, | |
| 157 | ESCENARIO_VIDEOCAPTURE = 5, | |
| 158 | ESCENARIO_VIDEOSURVEILLANCE = 6, | |
| 159 | ESCENARIO_GAMESTREAMING = 7, | |
| 160 | ESCENARIO_REMOTEGAMING = 8 | |
| 161 | } CODEC_SCENARIO, ENCODE_SCENARIO; | |
| 162 | ||
| 163 | /*! \brief Provides a hint to encoder about the content for the encoding session. | |
| 164 | */ | |
| 165 | typedef enum _CODEC_CONTENT | |
| 166 | { | |
| 167 | ECONTENT_UNKNOWN = 0, | |
| 168 | ECONTENT_FULLSCREENVIDEO = 1, | |
| 169 | ECONTENT_NONVIDEOSCREEN = 2 | |
| 170 | } CODEC_CONTENT, ENCODE_CONTENT; | |
| 171 | ||
| 172 | typedef enum | |
| 173 | { | |
| 174 | RATECONTROL_CBR = 1, | |
| 175 | RATECONTROL_VBR = 2, | |
| 176 | RATECONTROL_CQP = 3, | |
| 177 | RATECONTROL_AVBR = 4, | |
| 178 | RATECONTROL_RESERVED0 = 8, // This is used by MSDK for Lookahead and hence not used here | |
| 179 | RATECONTROL_ICQ = 9, | |
| 180 | RATECONTROL_VCM = 10, | |
| 181 | RATECONTROL_QVBR = 14, | |
| 182 | RATECONTROL_CQL = 15, | |
| 183 | RATECONTROL_IWD_VBR = 100 | |
| 184 | } RATE_CONTROL_METHOD; | |
| 185 | ||
| 186 | //! | |
| 187 | //! \brief Help function to check if the rate control method is BRC | |
| 188 | //! | |
| 189 | //! \param [in] rc | |
| 190 | //! Rate control method | |
| 191 | //! | |
| 192 | //! \return True if using BRC , else return false | |
| 193 | //! | |
| 194 | inline bool IsRateControlBrc(uint8_t rc) | |
| 195 | { | |
| 196 | return (rc == RATECONTROL_CBR) || | |
| 197 | (rc == RATECONTROL_VBR) || | |
| 198 | (rc == RATECONTROL_AVBR) || | |
| 199 | (rc == RATECONTROL_VCM) || | |
| 200 | (rc == RATECONTROL_ICQ) || | |
| 201 | (rc == RATECONTROL_QVBR); | |
| 202 | } | |
| 203 | ||
| 204 | typedef enum | |
| 205 | { | |
| 206 | DEFAULT_WEIGHTED_INTER_PRED_MODE = 0, | |
| 207 | EXPLICIT_WEIGHTED_INTER_PRED_MODE = 1, | |
| 208 | IMPLICIT_WEIGHTED_INTER_PRED_MODE = 2, | |
| 209 | INVALID_WEIGHTED_INTER_PRED_MODE = -1 | |
| 210 | } WEIGHTED_INTER_PRED_MODE; | |
| 211 | ||
| 212 | // used from MHW & DDI | |
| 213 | typedef enum | |
| 214 | { | |
| 215 | ROLLING_I_DISABLED = 0, | |
| 216 | ROLLING_I_COLUMN = 1, | |
| 217 | ROLLING_I_ROW = 2, | |
| 218 | ROLLING_I_SQUARE = 3 | |
| 219 | } ROLLING_I_SETTING; | |
| 220 | ||
| 221 | typedef enum | |
| 222 | { | |
| 223 | BRC_ROLLING_I_DISABLED = 0, | |
| 224 | BRC_ROLLING_I_COLUMN = 4, | |
| 225 | BRC_ROLLING_I_ROW = 8, | |
| 226 | BRC_ROLLING_I_SQUARE = 12, | |
| 227 | BRC_ROLLING_I_QP = 13 | |
| 228 | }BRC_ROLLING_I_SETTING; | |
| 229 | ||
| 230 | typedef enum _CODECHAL_MFX_SURFACE_ID | |
| 231 | { | |
| 232 | CODECHAL_MFX_REF_SURFACE_ID = 0, | |
| 233 | CODECHAL_MFX_SRC_SURFACE_ID = 4, | |
| 234 | CODECHAL_MFX_DSRECON_SURFACE_ID = 5 | |
| 235 | } CODECHAL_MFX_SURFACE_ID; | |
| 236 | ||
| 237 | typedef enum _CODECHAL_HCP_SURFACE_ID | |
| 238 | { | |
| 239 | CODECHAL_HCP_DECODED_SURFACE_ID = 0, | |
| 240 | CODECHAL_HCP_SRC_SURFACE_ID = 1, // Encode | |
| 241 | CODECHAL_HCP_LAST_SURFACE_ID = 2, // VP9 | |
| 242 | CODECHAL_HCP_GOLDEN_SURFACE_ID = 3, // VP9 | |
| 243 | CODECHAL_HCP_ALTREF_SURFACE_ID = 4, // VP9 | |
| 244 | CODECHAL_HCP_REF_SURFACE_ID = 5 | |
| 245 | } CODECHAL_HCP_SURFACE_ID; | |
| 246 | ||
| 247 | // --------------------------- | |
| 248 | // Structures | |
| 249 | // --------------------------- | |
| 250 | // used from MHW & DDI | |
| 251 | typedef struct _BSBuffer | |
| 252 | { | |
| 253 | uint8_t *pBase; | |
| 254 | uint8_t *pCurrent; | |
| 255 | uint32_t SliceOffset; // Slice offset, always byte aligned | |
| 256 | uint8_t BitOffset; // bit offset for pCurrent. | |
| 257 | uint32_t BitSize; // bit size per slice, first slice may include SPS & PPS | |
| 258 | uint32_t BufferSize; // buffer size | |
| 259 | } BSBuffer, *PBSBuffer; | |
| 260 | ||
| 261 | typedef struct _CODEC_ENCODER_SLCDATA | |
| 262 | { | |
| 263 | uint32_t SliceOffset; | |
| 264 | uint32_t BitSize; | |
| 265 | uint32_t CmdOffset; | |
| 266 | uint32_t SkipEmulationByteCount; | |
| 267 | ||
| 268 | // MPEG2 only | |
| 269 | struct | |
| 270 | { | |
| 271 | uint8_t SliceGroup; | |
| 272 | uint16_t NextSgMbXCnt; | |
| 273 | uint16_t NextSgMbYCnt; | |
| 274 | }; | |
| 275 | } CODEC_ENCODER_SLCDATA, *PCODEC_ENCODER_SLCDATA; | |
| 276 | ||
| 277 | typedef struct _CODECHAL_NAL_UNIT_PARAMS | |
| 278 | { | |
| 279 | uint32_t uiNalUnitType; | |
| 280 | uint32_t uiOffset; | |
| 281 | uint32_t uiSize; | |
| 282 | bool bInsertEmulationBytes; | |
| 283 | uint32_t uiSkipEmulationCheckCount; | |
| 284 | } CODECHAL_NAL_UNIT_PARAMS, *PCODECHAL_NAL_UNIT_PARAMS; | |
| 285 | ||
| 286 | typedef struct tagFRAMERATE | |
| 287 | { | |
| 288 | uint32_t Numerator; | |
| 289 | uint32_t Denominator; | |
| 290 | } FRAMERATE; | |
| 291 | ||
| 292 | /*********************************************************************************\ | |
| 293 | Constants for VDENC costing look-up-tables | |
| 294 | \*********************************************************************************/ | |
| 295 | typedef enum _CODEC_VDENC_LUTMODE | |
| 296 | { | |
| 297 | CODEC_VDENC_LUTMODE_INTRA_SADMPM = 0x00, | |
| 298 | CODEC_VDENC_LUTMODE_INTRA_32x32 = 0x01, | |
| 299 | CODEC_VDENC_LUTMODE_INTRA_16x16 = 0x02, | |
| 300 | CODEC_VDENC_LUTMODE_INTRA_8x8 = 0x03, | |
| 301 | CODEC_VDENC_LUTMODE_INTER_32x16 = 0x04, | |
| 302 | CODEC_VDENC_LUTMODE_INTER_16x32 = 0x04, | |
| 303 | CODEC_VDENC_LUTMODE_INTER_AMP = 0x04, //All asymmetrical shapes | |
| 304 | CODEC_VDENC_LUTMODE_INTER_16x16 = 0x05, | |
| 305 | CODEC_VDENC_LUTMODE_INTER_16x8 = 0x06, | |
| 306 | CODEC_VDENC_LUTMODE_INTER_8x16 = 0x06, | |
| 307 | CODEC_VDENC_LUTMODE_INTER_8x8 = 0x07, | |
| 308 | CODEC_VDENC_LUTMODE_INTER_32x32 = 0x08, | |
| 309 | CODEC_VDENC_LUTMODE_INTER_BIDIR = 0x09, | |
| 310 | CODEC_VDENC_LUTMODE_REF_ID = 0x0A, | |
| 311 | CODEC_VDENC_LUTMODE_INTRA_CHROMA = 0x0B, | |
| 312 | CODEC_VDENC_LUTMODE_INTRA_NxN = 0x0C, | |
| 313 | CODEC_VDENC_LUTMODE_INTRA_RDEMPM = 0x0D, | |
| 314 | CODEC_VDENC_LUTMODE_MERGE_32X32 = 0x0E, | |
| 315 | CODEC_VDENC_LUTMODE_MERGE_16x16 = 0x0F, | |
| 316 | CODEC_VDENC_LUTMODE_MERGE_8x8 = 0x10, | |
| 317 | CODEC_VDENC_LUTMODE_SKIP_32X32 = 0x11, | |
| 318 | CODEC_VDENC_LUTMODE_SKIP_16x16 = 0x12, | |
| 319 | CODEC_VDENC_LUTMODE_SKIP_8x8 = 0x13, | |
| 320 | CODEC_VDENC_LUTMODE_INTRA_DC_32x32_SAD = 0x14, | |
| 321 | CODEC_VDENC_LUTMODE_INTRA_DC_16x16_SAD = 0x15, | |
| 322 | CODEC_VDENC_LUTMODE_INTRA_DC_8x8_SAD = 0x16, | |
| 323 | CODEC_VDENC_LUTMODE_INTRA_DC_4x4_SAD = 0x17, | |
| 324 | CODEC_VDENC_LUTMODE_INTRA_NONDC_32x32_SAD = 0x18, | |
| 325 | CODEC_VDENC_LUTMODE_INTRA_NONDC_16x16_SAD = 0x19, | |
| 326 | CODEC_VDENC_LUTMODE_INTRA_NONDC_8x8_SAD = 0x1A, | |
| 327 | CODEC_VDENC_LUTMODE_INTRA_NONDC_4x4_SAD = 0x1B, | |
| 328 | CODEC_VDENC_LUTMODE_INTRA_DC_32x32_RD = 0x1C, | |
| 329 | CODEC_VDENC_LUTMODE_INTRA_DC_8x8_RD = 0x1D, | |
| 330 | CODEC_VDENC_LUTMODE_INTRA_NONDC_32x32_RD = 0x1E, | |
| 331 | CODEC_VDENC_LUTMODE_INTRA_NONDC_8x8_RD = 0x1F, | |
| 332 | CODEC_VDENC_LUTMODE_INTRA_LEFT_BOUNDARY_SAD = 0x20, | |
| 333 | CODEC_VDENC_LUTMODE_INTRA_TOP_BOUNDARY_SAD = 0x21, | |
| 334 | CODEC_VDENC_LUTMODE_INTRA_TU_SPLIT = 0x22, | |
| 335 | CODEC_VDENC_LUTMODE_INTER_TU_SPLIT = 0x23, | |
| 336 | CODEC_VDENC_LUTMODE_TU_CBF_FLAG = 0x24, | |
| 337 | CODEC_VDENC_LUTMODE_INTRA_TU_32_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 0, | |
| 338 | CODEC_VDENC_LUTMODE_INTRA_TU_16_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 1, | |
| 339 | CODEC_VDENC_LUTMODE_INTRA_TU_8_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 2, | |
| 340 | CODEC_VDENC_LUTMODE_INTRA_TU_4_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 3, | |
| 341 | CODEC_VDENC_LUTMODE_INTER_TU_32_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 4, | |
| 342 | CODEC_VDENC_LUTMODE_INTER_TU_16_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 5, | |
| 343 | CODEC_VDENC_LUTMODE_INTER_TU_8_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 6, | |
| 344 | CODEC_VDENC_LUTMODE_INTER_TU_4_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 7, | |
| 345 | ||
| 346 | CODEC_VDENC_LUTMODE_TU_COEF_EST = 0x2C, | |
| 347 | CODEC_VDENC_LUTMODE_INTRA_TU_32_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 0, | |
| 348 | CODEC_VDENC_LUTMODE_INTRA_TU_16_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 1, | |
| 349 | CODEC_VDENC_LUTMODE_INTRA_TU_8_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 2, | |
| 350 | CODEC_VDENC_LUTMODE_INTRA_TU_4_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 3, | |
| 351 | CODEC_VDENC_LUTMODE_INTER_TU_32_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 4, | |
| 352 | CODEC_VDENC_LUTMODE_INTER_TU_16_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 5, | |
| 353 | CODEC_VDENC_LUTMODE_INTER_TU_8_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 6, | |
| 354 | CODEC_VDENC_LUTMODE_INTER_TU_4_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 7, | |
| 355 | ||
| 356 | CODEC_VDENC_LUTMODE_INTRA_TU_32_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 8, | |
| 357 | CODEC_VDENC_LUTMODE_INTRA_TU_16_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 9, | |
| 358 | CODEC_VDENC_LUTMODE_INTRA_TU_8_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 10, | |
| 359 | CODEC_VDENC_LUTMODE_INTRA_TU_4_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 11, | |
| 360 | CODEC_VDENC_LUTMODE_INTER_TU_32_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 12, | |
| 361 | CODEC_VDENC_LUTMODE_INTER_TU_16_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 13, | |
| 362 | CODEC_VDENC_LUTMODE_INTER_TU_8_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 14, | |
| 363 | CODEC_VDENC_LUTMODE_INTER_TU_4_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 15, | |
| 364 | ||
| 365 | CODEC_VDENC_LUTMODE_INTRA_TU_32_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 16, | |
| 366 | CODEC_VDENC_LUTMODE_INTRA_TU_16_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 17, | |
| 367 | CODEC_VDENC_LUTMODE_INTRA_TU_8_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 18, | |
| 368 | CODEC_VDENC_LUTMODE_INTRA_TU_4_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 19, | |
| 369 | CODEC_VDENC_LUTMODE_INTER_TU_32_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 20, | |
| 370 | CODEC_VDENC_LUTMODE_INTER_TU_16_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 21, | |
| 371 | CODEC_VDENC_LUTMODE_INTER_TU_8_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 22, | |
| 372 | CODEC_VDENC_LUTMODE_INTER_TU_4_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 23, | |
| 373 | ||
| 374 | CODEC_VDENC_LUTMODE_INTRA_TU_32_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 24, | |
| 375 | CODEC_VDENC_LUTMODE_INTRA_TU_16_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 25, | |
| 376 | CODEC_VDENC_LUTMODE_INTRA_TU_8_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 26, | |
| 377 | CODEC_VDENC_LUTMODE_INTRA_TU_4_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 27, | |
| 378 | CODEC_VDENC_LUTMODE_INTER_TU_32_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 28, | |
| 379 | CODEC_VDENC_LUTMODE_INTER_TU_16_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 29, | |
| 380 | CODEC_VDENC_LUTMODE_INTER_TU_8_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 30, | |
| 381 | CODEC_VDENC_LUTMODE_INTER_TU_4_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 31, | |
| 382 | ||
| 383 | // VP9 specific cost | |
| 384 | CODEC_VDENC_LUTMODE_INTRA_32x16 = 0x4C, | |
| 385 | CODEC_VDENC_LUTMODE_INTRA_16x8 = 0x4D, | |
| 386 | CODEC_VDENC_LUTMODE_INTER_NEARESTMV = 0x4E, | |
| 387 | CODEC_VDENC_LUTMODE_INTER_NEARMV = 0x4F, | |
| 388 | CODEC_VDENC_LUTMODE_INTER_ZEROMV = 0x50, | |
| 389 | CODEC_VDENC_LUTMODE_TU_DEPTH0 = 0x51, | |
| 390 | CODEC_VDENC_LUTMODE_TU_DEPTH1 = 0x52, | |
| 391 | CODEC_VDENC_LUTMODE_TU_DEPTH2 = 0x53, | |
| 392 | ||
| 393 | CODEC_VDENC_LUTMODE_INTRA_64X64DC = 0x54, | |
| 394 | CODEC_VDENC_LUTMODE_MERGE_64X64 = 0x55, | |
| 395 | CODEC_VDENC_LUTMODE_SKIP_64X64 = 0x56, | |
| 396 | ||
| 397 | CODEC_VDENC_NUM_MODE_COST = 0x57 | |
| 398 | } CODEC_VDENC_LUTMODE; | |
| 399 | ||
| 400 | // Batch buffer type | |
| 401 | enum | |
| 402 | { | |
| 403 | MB_ENC_Frame_BB = 0, | |
| 404 | MB_ENC_Field_BB, | |
| 405 | //Add new buffer type here | |
| 406 | NUM_ENCODE_BB_TYPE | |
| 407 | }; | |
| 408 | ||
| 409 | typedef enum | |
| 410 | { | |
| 411 | FRAME_NO_SKIP = 0, // encode as normal, no skip frames | |
| 412 | FRAME_SKIP_NORMAL = 1 // one or more frames were skipped prior to curr frame. Encode curr frame as normal, update BRC | |
| 413 | } FRAME_SKIP_FLAG; | |
| 414 | ||
| 415 | typedef enum _CODEC_SLICE_STRUCTS | |
| 416 | { | |
| 417 | CODECHAL_SLICE_STRUCT_ONESLICE = 0, // Once slice for the whole frame | |
| 418 | CODECHAL_SLICE_STRUCT_POW2ROWS = 1, // Slices are power of 2 number of rows, all slices the same | |
| 419 | CODECHAL_SLICE_STRUCT_ROWSLICE = 2, // Slices are any number of rows, all slices the same | |
| 420 | CODECHAL_SLICE_STRUCT_ARBITRARYROWSLICE = 3, // Slices are any number of rows, slices can be different | |
| 421 | CODECHAL_SLICE_STRUCT_ARBITRARYMBSLICE = 4 // Slices are any number of MBs, slices can be different | |
| 422 | // 5 - 7 are Reserved | |
| 423 | } CODEC_SLICE_STRUCTS; | |
| 424 | ||
| 425 | //FEI Encode Macros | |
| 426 | #define CodecHalIsFeiEncode(codecFunction) \ | |
| 427 | ( codecFunction == CODECHAL_FUNCTION_FEI_PRE_ENC || \ | |
| 428 | codecFunction == CODECHAL_FUNCTION_FEI_ENC || \ | |
| 429 | codecFunction == CODECHAL_FUNCTION_FEI_PAK || \ | |
| 430 | codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK) | |
| 431 | ||
| 432 | //Encode Macros | |
| 433 | #define CodecHalIsEncode(codecFunction) \ | |
| 434 | (codecFunction == CODECHAL_FUNCTION_ENC || \ | |
| 435 | codecFunction == CODECHAL_FUNCTION_PAK || \ | |
| 436 | codecFunction == CODECHAL_FUNCTION_ENC_PAK || \ | |
| 437 | codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK ||\ | |
| 438 | codecFunction == CODECHAL_FUNCTION_HYBRIDPAK) || \ | |
| 439 | CodecHalIsFeiEncode(codecFunction) | |
| 440 | ||
| 441 | #define CodecHalUsesVideoEngine(codecFunction) \ | |
| 442 | (codecFunction == CODECHAL_FUNCTION_PAK || \ | |
| 443 | codecFunction == CODECHAL_FUNCTION_ENC_PAK || \ | |
| 444 | codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK || \ | |
| 445 | codecFunction == CODECHAL_FUNCTION_FEI_PAK || \ | |
| 446 | codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK) | |
| 447 | ||
| 448 | #define CodecHalUsesRenderEngine(codecFunction, standard) \ | |
| 449 | (codecFunction == CODECHAL_FUNCTION_ENC || \ | |
| 450 | (codecFunction == CODECHAL_FUNCTION_ENC_PAK) || \ | |
| 451 | codecFunction == CODECHAL_FUNCTION_HYBRIDPAK || \ | |
| 452 | ((codecFunction == CODECHAL_FUNCTION_DECODE) && (standard == CODECHAL_VC1)) || \ | |
| 453 | codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK || \ | |
| 454 | codecFunction == CODECHAL_FUNCTION_FEI_PRE_ENC || \ | |
| 455 | codecFunction == CODECHAL_FUNCTION_FEI_ENC || \ | |
| 456 | codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK) | |
| 457 | ||
| 458 | #define CodecHalUsesOnlyRenderEngine(codecFunction) \ | |
| 459 | (codecFunction == CODECHAL_FUNCTION_ENC || \ | |
| 460 | codecFunction == CODECHAL_FUNCTION_FEI_ENC || \ | |
| 461 | codecFunction == CODECHAL_FUNCTION_HYBRIDPAK) | |
| 462 | ||
| 463 | #define CodecHalUsesVdencEngine(codecFunction) \ | |
| 464 | (codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK) | |
| 465 | ||
| 466 | #define CodecHalUsesPakEngine(codecFunction) \ | |
| 467 | (codecFunction == CODECHAL_FUNCTION_PAK || \ | |
| 468 | codecFunction == CODECHAL_FUNCTION_ENC_PAK) | |
| 469 | ||
| 470 | #define CodecHalIsRateControlBrc(rateControl, standard) (\ | |
| 471 | (rateControl == RATECONTROL_CBR) || \ | |
| 472 | (rateControl == RATECONTROL_VBR) || \ | |
| 473 | (rateControl == RATECONTROL_AVBR) || \ | |
| 474 | (rateControl == RATECONTROL_CQL) || \ | |
| 475 | ((( rateControl == RATECONTROL_VCM) || \ | |
| 476 | ( rateControl == RATECONTROL_ICQ) || \ | |
| 477 | ( rateControl == RATECONTROL_QVBR) || \ | |
| 478 | ( rateControl == RATECONTROL_IWD_VBR)) && \ | |
| 479 | ( standard == CODECHAL_AVC )) ) | |
| 480 | ||
| 481 | // The current definition of the first encode mode CODECHAL_ENCODE_MODE_AVC should be used | |
| 482 | // as a base for subsequent encode modes | |
| 483 | #define CODECHAL_ENCODE_MODE_BIT_OFFSET ((uint32_t)(log((double)CODECHAL_ENCODE_MODE_AVC)/log(2.))) | |
| 484 | #define CODECHAL_ENCODE_MODE_BIT_MASK (( 1L << CODECHAL_ENCODE_MODE_BIT_OFFSET) - 1 ) | |
| 485 | ||
| 486 | #endif // __CODEC_DEF_COMMON_ENCODE_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_hevc.h | |
| 23 | //! \brief Defines basic HEVC types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details This is the base header for all codec_def HEVC files. All codec_def HEVC files should include this file which should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_HEVC_H__ | |
| 27 | #define __CODEC_DEF_COMMON_HEVC_H__ | |
| 28 | ||
| 29 | #include "codec_def_common.h" | |
| 30 | ||
| 31 | #define CODEC_MAX_NUM_REF_FRAME_HEVC 15 | |
| 32 | #define CODECHAL_MAX_CUR_NUM_REF_FRAME_HEVC 8 | |
| 33 | #define CODEC_HEVC_VDENC_LCU_WIDTH 64 | |
| 34 | #define CODEC_HEVC_VDENC_LCU_HEIGHT 64 | |
| 35 | ||
| 36 | /*! \brief Quantization matrix data, which is sent on a per-picture basis. | |
| 37 | * | |
| 38 | * The quantization matrix buffer is sent only when scaling_list_enabled_flag takes value 1. If 0, driver should assume "flat" scaling lists are present and all the entries takes value 16. | |
| 39 | */ | |
| 40 | typedef struct _CODECHAL_HEVC_IQ_MATRIX_PARAMS | |
| 41 | { | |
| 42 | /*! \brief Scaling lists for the 4x4 scaling process. | |
| 43 | * | |
| 44 | * Corresponding to ScalingList[ 0 ][ MatrixID ][ i ] in HEVC specification, where MatrixID is in the range of 0 to 5, inclusive, and i is in the range of 0 to 15, inclusive. | |
| 45 | */ | |
| 46 | uint8_t ucScalingLists0[6][16]; | |
| 47 | ||
| 48 | /*! \brief Scaling lists for the 8x8 scaling process. | |
| 49 | * | |
| 50 | * Corresponding to ScalingList[ 1 ][ MatrixID ][ i ] in the HEVC specification, where MatrixID is in the range of 0 to 5, inclusive, and i is in the range of 0 to 63, inclusive. | |
| 51 | */ | |
| 52 | uint8_t ucScalingLists1[6][64]; | |
| 53 | ||
| 54 | /*! \brief Scaling lists for the 8x8 scaling process. | |
| 55 | * | |
| 56 | * Corresponding to ScalingList[ 2 ][ MatrixID ][ i ] in HEVC specification, where MatrixID is in the range of 0 to 5, inclusive, and i is in the range of 0 to 63, inclusive. | |
| 57 | */ | |
| 58 | uint8_t ucScalingLists2[6][64]; | |
| 59 | ||
| 60 | /*! \brief Scaling lists for the 8x8 scaling process. | |
| 61 | * | |
| 62 | * Corresponding to ScalingList[ 3 ][ MatrixID ][ i ] in HEVC specification, where MatrixID is in the range of 0 to 1, inclusive, and i is in the range of 0 to 63, inclusive. | |
| 63 | */ | |
| 64 | uint8_t ucScalingLists3[2][64]; | |
| 65 | ||
| 66 | /*! \brief DC value of the scaling list for 16x16 size. | |
| 67 | * | |
| 68 | * With sizeID equal to 2 and corresponding to scaling_list_dc_coef_minus8[ sizeID − 2 ][ matrixID ] +8 with sizeID equal to 2 and matrixID in the range of 0 to 5, inclusive, in HEVC specification. | |
| 69 | */ | |
| 70 | uint8_t ucScalingListDCCoefSizeID2[6]; | |
| 71 | ||
| 72 | /*! \brief DC value of the scaling list for 32x32 size. | |
| 73 | * | |
| 74 | * With sizeID equal to 3, and corresponding to scaling_list_dc_coef_minus8[ sizeID − 2 ][ matrixID ] +8 with sizeID equal to 3 and matrixID in the range of 0 to 1, inclusive, in HEVC specification. | |
| 75 | */ | |
| 76 | uint8_t ucScalingListDCCoefSizeID3[2]; | |
| 77 | } CODECHAL_HEVC_IQ_MATRIX_PARAMS, *PCODECHAL_HEVC_IQ_MATRIX_PARAMS; | |
| 78 | ||
| 79 | typedef struct _CODEC_HEVC_SCC_PIC_PARAMS | |
| 80 | { | |
| 81 | union | |
| 82 | { | |
| 83 | struct | |
| 84 | { | |
| 85 | uint32_t pps_curr_pic_ref_enabled_flag : 1; | |
| 86 | uint32_t palette_mode_enabled_flag : 1; | |
| 87 | uint32_t motion_vector_resolution_control_idc : 2; //[0..2] | |
| 88 | uint32_t intra_boundary_filtering_disabled_flag : 1; | |
| 89 | uint32_t residual_adaptive_colour_transform_enabled_flag : 1; | |
| 90 | uint32_t pps_slice_act_qp_offsets_present_flag : 1; | |
| 91 | uint32_t ReservedBits6 : 25; | |
| 92 | } fields; | |
| 93 | uint32_t dwScreenContentCodingPropertyFlags; | |
| 94 | } PicSCCExtensionFlags; | |
| 95 | ||
| 96 | uint8_t palette_max_size; // [0..64] | |
| 97 | uint8_t delta_palette_max_predictor_size; // [0..128] | |
| 98 | uint8_t PredictorPaletteSize; // [0..127] | |
| 99 | uint16_t PredictorPaletteEntries[3][128]; | |
| 100 | char pps_act_y_qp_offset_plus5; // [-7..17] | |
| 101 | char pps_act_cb_qp_offset_plus5; // [-7..17] | |
| 102 | char pps_act_cr_qp_offset_plus3; // [-9..15] | |
| 103 | ||
| 104 | } CODEC_HEVC_SCC_PIC_PARAMS, *PCODEC_HEVC_SCC_PIC_PARAMS; | |
| 105 | ||
| 106 | #endif // __CODEC_DEF_COMMON_HEVC_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_jpeg.h | |
| 23 | //! \brief Defines basic JPEG types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details This is the base header for all codec_def JPEG files. All codec_def JPEG files should include this file which should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_JPEG_H__ | |
| 27 | #define __CODEC_DEF_COMMON_JPEG_H__ | |
| 28 | ||
| 29 | #include "codec_def_common.h" | |
| 30 | ||
| 31 | #define JPEG_MAX_NUM_HUFF_TABLE_INDEX 2 // For baseline only allowed 2, else could have 4. | |
| 32 | #define JPEG_NUM_QUANTMATRIX 64 // Elements of 8x8 matrix in zig-zag scan order. | |
| 33 | #define JPEG_MAX_NUM_OF_QUANTMATRIX 4 // JPEG decoders can store up to 4 different quantization matrix | |
| 34 | ||
| 35 | #define JPEG_NUM_HUFF_TABLE_DC_BITS 12 // Huffman Table DC BITS | |
| 36 | #define JPEG_NUM_HUFF_TABLE_DC_HUFFVAL 12 // Huffman Table DC HUFFVAL | |
| 37 | #define JPEG_NUM_HUFF_TABLE_AC_BITS 16 // Huffman Table AC BITS | |
| 38 | #define JPEG_NUM_HUFF_TABLE_AC_HUFFVAL 162 // Huffman Table AC HUFFVAL | |
| 39 | ||
| 40 | //! | |
| 41 | //! \enum CodecJpegComponents | |
| 42 | //! \brief JPEG Component Types | |
| 43 | //! | |
| 44 | enum CodecJpegComponents | |
| 45 | { | |
| 46 | jpegComponentY = 0, //!< Component Y | |
| 47 | jpegComponentU = 1, //!< Component U | |
| 48 | jpegComponentV = 2, //!< Component V | |
| 49 | jpegNumComponent = 3, //!< Component number | |
| 50 | }; | |
| 51 | ||
| 52 | //! | |
| 53 | //! \struct CodecJpegQuantMatrix | |
| 54 | //! \brief JPEG Quantization Matrix | |
| 55 | //! | |
| 56 | struct CodecJpegQuantMatrix | |
| 57 | { | |
| 58 | uint32_t m_jpegQMTableType[JPEG_MAX_NUM_OF_QUANTMATRIX]; //!< Quant Matrix table type | |
| 59 | uint8_t m_quantMatrix[JPEG_MAX_NUM_OF_QUANTMATRIX][JPEG_NUM_QUANTMATRIX]; //!< Quant Matrix | |
| 60 | }; | |
| 61 | ||
| 62 | #endif // __CODEC_DEF_COMMON_JPEG_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_mpeg2.h | |
| 23 | //! \brief Defines basic MPEG2 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details This is the base header for all codec_def MPEG2 files. All codec_def MPEG2 files should include this file which should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_MPEG2_H__ | |
| 27 | #define __CODEC_DEF_COMMON_MPEG2_H__ | |
| 28 | ||
| 29 | #include "codec_def_common.h" | |
| 30 | ||
| 31 | //! | |
| 32 | //! \struct CodecMpeg2IqMatrix | |
| 33 | //! \brief Inverse Quantization Matrix Buffer | |
| 34 | //! | |
| 35 | struct CodecMpeg2IqMatrix | |
| 36 | { | |
| 37 | int32_t m_loadIntraQuantiserMatrix; //!< Indicate if intra Quantiser Matrix is available | |
| 38 | int32_t m_loadNonIntraQuantiserMatrix; //!< Indicate if non intra Quantiser Matrix is available | |
| 39 | int32_t m_loadChromaIntraQuantiserMatrix; //!< Indicate if chroma intra Quantiser Matrix is available | |
| 40 | int32_t m_loadChromaNonIntraQuantiserMatrix;//!< Indicate if chroma non intra Quantiser Matrix is available | |
| 41 | uint8_t m_intraQuantiserMatrix[64]; //!< Intra Quantiser Matrix | |
| 42 | uint8_t m_nonIntraQuantiserMatrix[64]; //!< Non intra Quantiser Matrix | |
| 43 | uint8_t m_chromaIntraQuantiserMatrix[64]; //!< Chroma intra Quantiser Matrix | |
| 44 | uint8_t m_chromaNonIntraQuantiserMatrix[64];//!< Chroma non intra Quantiser Matrix | |
| 45 | }; | |
| 46 | ||
| 47 | #endif // __CODEC_DEF_COMMON_MPEG2_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017-2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_vp9.h | |
| 23 | //! \brief Defines decode VP9 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to VP9 codec only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_VP9_H__ | |
| 27 | #define __CODEC_DEF_COMMON_VP9_H__ | |
| 28 | ||
| 29 | #include "mos_os.h" | |
| 30 | ||
| 31 | #define CODEC_VP9_SUPER_BLOCK_WIDTH 64 | |
| 32 | #define CODEC_VP9_SUPER_BLOCK_HEIGHT 64 | |
| 33 | #define CODEC_VP9_MIN_BLOCK_WIDTH 8 | |
| 34 | #define CODEC_VP9_MIN_BLOCK_HEIGHT 8 | |
| 35 | ||
| 36 | #define CODEC_VP9_BLOCK_TYPES 2 //Outside dimension. 0 = Y with DC, 1 = UV | |
| 37 | #define CODEC_VP9_REF_TYPES 2 // intra=0, inter=1 | |
| 38 | #define CODEC_VP9_COEF_BANDS 6 //Middle dimension reflects the coefficient position within the transform. | |
| 39 | #define CODEC_VP9_UNCONSTRAINED_NODES 3 | |
| 40 | /* Inside dimension is measure of nearby complexity, that reflects the energy | |
| 41 | of nearby coefficients are nonzero. For the first coefficient (DC, unless | |
| 42 | block type is 0), we look at the (already encoded) blocks above and to the | |
| 43 | left of the current block. The context index is then the number (0,1,or 2) | |
| 44 | of these blocks having nonzero coefficients. | |
| 45 | After decoding a coefficient, the measure is determined by the size of the | |
| 46 | most recently decoded coefficient. | |
| 47 | Note that the intuitive meaning of this measure changes as coefficients | |
| 48 | are decoded, e.g., prior to the first token, a zero means that my neighbors | |
| 49 | are empty while, after the first token, because of the use of end-of-block, | |
| 50 | a zero means we just decoded a zero and hence guarantees that a non-zero | |
| 51 | coefficient will appear later in this block. However, this shift | |
| 52 | in meaning is perfectly OK because our context depends also on the | |
| 53 | coefficient band (and since zigzag positions 0, 1, and 2 are in | |
| 54 | distinct bands). */ | |
| 55 | #define CODEC_VP9_PREV_COEF_CONTEXTS 6 | |
| 56 | #define CODEC_VP9_MBSKIP_CONTEXTS 3 | |
| 57 | #define CODEC_VP9_INTER_MODE_CONTEXTS 7 | |
| 58 | #define CODEC_VP9_INTER_MODES 4 //NEAREST_MV, NEAR_MV, ZERO_MV, NEW_MV | |
| 59 | #define CODEC_VP9_SWITCHABLE_FILTERS 3 // number of switchable filters | |
| 60 | #define CODEC_VP9_INTRA_INTER_CONTEXTS 4 | |
| 61 | #define CODEC_VP9_COMP_INTER_CONTEXTS 5 | |
| 62 | #define CODEC_VP9_REF_CONTEXTS 5 | |
| 63 | #define CODEC_VP9_BLOCK_SIZE_GROUPS 4 | |
| 64 | #define CODEC_VP9_INTRA_MODES 10 //DC_PRED,V_PRED,H_PRED,D45_PRED,D135_PRED,D117_PRED,D153_PRED,D207_PRED,D63_PRED,TM_PRED | |
| 65 | #define CODEC_VP9_PARTITION_PLOFFSET 4 // number of probability models per block size | |
| 66 | #define CODECHAL_VP9_PARTITION_CONTEXTS (4 * CODEC_VP9_PARTITION_PLOFFSET) | |
| 67 | #define CODEC_VP9_MV_JOINTS 4 | |
| 68 | #define CODEC_VP9_MV_CLASSES 11 | |
| 69 | #define CODEC_VP9_CLASS0_BITS 1 /* bits at integer precision for class 0 */ | |
| 70 | #define CODECHAL_VP9_CLASS0_SIZE (1 << CODEC_VP9_CLASS0_BITS) | |
| 71 | #define CODECHAL_VP9_MV_OFFSET_BITS (CODEC_VP9_MV_CLASSES + CODEC_VP9_CLASS0_BITS - 2) | |
| 72 | #define CODEC_VP9_MV_FP_SIZE 4 | |
| 73 | #define CODEC_VP9_NUM_REF_FRAMES_LOG2 3 | |
| 74 | #define CODEC_VP9_NUM_REF_FRAMES (1 << CODEC_VP9_NUM_REF_FRAMES_LOG2) | |
| 75 | #define CODECHAL_VP9_NUM_DPB_BUFFERS (CODEC_VP9_NUM_REF_FRAMES + 4) | |
| 76 | #define CODEC_VP9_NUM_CONTEXTS 4 | |
| 77 | #define CODEC_VP9_MAX_REF_LF_DELTAS 4 | |
| 78 | #define CODEC_VP9_MAX_MODE_LF_DELTAS 2 | |
| 79 | #define CODECHAL_VP9_SEG_TREE_PROBS (CODEC_VP9_MAX_SEGMENTS - 1) | |
| 80 | #define CODEC_VP9_PREDICTION_PROBS 3 | |
| 81 | #define CODEC_VP9_MAX_LOOP_FILTER 63 | |
| 82 | ||
| 83 | #define CODEC_VP9_MAX_QP 255 | |
| 84 | #define CODEC_VP9_QINDEX_RANGE (CODEC_VP9_MAX_QP + 1) | |
| 85 | #define CODEC_VP9_MAX_REPAK_THRESHOLD 40342 | |
| 86 | ||
| 87 | //VP9 Profile | |
| 88 | typedef enum { | |
| 89 | CODEC_PROFILE_VP9_PROFILE0 = 0, | |
| 90 | CODEC_PROFILE_VP9_PROFILE1 = 1, | |
| 91 | CODEC_PROFILE_VP9_PROFILE2 = 2, | |
| 92 | CODEC_PROFILE_VP9_PROFILE3 = 3 | |
| 93 | }CODEC_VP9_PROFILE_IDC; | |
| 94 | ||
| 95 | typedef enum { | |
| 96 | CODEC_VP9_KEY_FRAME = 0, | |
| 97 | CODEC_VP9_INTER_FRAME = 1, | |
| 98 | CODEC_VP9_FRAME_TYPES, | |
| 99 | } CODEC_VP9_FRAME_TYPE; | |
| 100 | ||
| 101 | // block transform size | |
| 102 | typedef enum { | |
| 103 | CODEC_VP9_TX_4X4 = 0, // 4x4 transform | |
| 104 | CODEC_VP9_TX_8X8 = 1, // 8x8 transform | |
| 105 | CODEC_VP9_TX_16X16 = 2, // 16x16 transform | |
| 106 | CODEC_VP9_TX_32X32 = 3, // 32x32 transform | |
| 107 | CODEC_VP9_TX_SELECTABLE = 4, // selectable transform | |
| 108 | CODEC_VP9_TX_SIZES = 4, | |
| 109 | } CODEC_VP9_TX_SIZE; | |
| 110 | ||
| 111 | typedef enum CODEC_VP9_PARTITION_TYPE { | |
| 112 | CODEC_VP9_PARTITION_NONE, | |
| 113 | CODEC_VP9_PARTITION_HORZ, | |
| 114 | CODEC_VP9_PARTITION_VERT, | |
| 115 | CODEC_VP9_PARTITION_SPLIT, | |
| 116 | CODEC_VP9_PARTITION_TYPES, | |
| 117 | CODECHAL_VP9_PARTITION_INVALID = CODEC_VP9_PARTITION_TYPES | |
| 118 | } CODEC_VP9_PARTITION_TYPE; | |
| 119 | ||
| 120 | typedef uint8_t CODEC_VP9_COEFF_PROBS_MODEL[CODEC_VP9_REF_TYPES][CODEC_VP9_COEF_BANDS] | |
| 121 | [CODEC_VP9_PREV_COEF_CONTEXTS] | |
| 122 | [CODEC_VP9_UNCONSTRAINED_NODES]; | |
| 123 | ||
| 124 | static const uint16_t CODECHAL_VP9_QUANT_DC[CODEC_VP9_QINDEX_RANGE] = { | |
| 125 | 4, 8, 8, 9, 10, 11, 12, 12, | |
| 126 | 13, 14, 15, 16, 17, 18, 19, 19, | |
| 127 | 20, 21, 22, 23, 24, 25, 26, 26, | |
| 128 | 27, 28, 29, 30, 31, 32, 32, 33, | |
| 129 | 34, 35, 36, 37, 38, 38, 39, 40, | |
| 130 | 41, 42, 43, 43, 44, 45, 46, 47, | |
| 131 | 48, 48, 49, 50, 51, 52, 53, 53, | |
| 132 | 54, 55, 56, 57, 57, 58, 59, 60, | |
| 133 | 61, 62, 62, 63, 64, 65, 66, 66, | |
| 134 | 67, 68, 69, 70, 70, 71, 72, 73, | |
| 135 | 74, 74, 75, 76, 77, 78, 78, 79, | |
| 136 | 80, 81, 81, 82, 83, 84, 85, 85, | |
| 137 | 87, 88, 90, 92, 93, 95, 96, 98, | |
| 138 | 99, 101, 102, 104, 105, 107, 108, 110, | |
| 139 | 111, 113, 114, 116, 117, 118, 120, 121, | |
| 140 | 123, 125, 127, 129, 131, 134, 136, 138, | |
| 141 | 140, 142, 144, 146, 148, 150, 152, 154, | |
| 142 | 156, 158, 161, 164, 166, 169, 172, 174, | |
| 143 | 177, 180, 182, 185, 187, 190, 192, 195, | |
| 144 | 199, 202, 205, 208, 211, 214, 217, 220, | |
| 145 | 223, 226, 230, 233, 237, 240, 243, 247, | |
| 146 | 250, 253, 257, 261, 265, 269, 272, 276, | |
| 147 | 280, 284, 288, 292, 296, 300, 304, 309, | |
| 148 | 313, 317, 322, 326, 330, 335, 340, 344, | |
| 149 | 349, 354, 359, 364, 369, 374, 379, 384, | |
| 150 | 389, 395, 400, 406, 411, 417, 423, 429, | |
| 151 | 435, 441, 447, 454, 461, 467, 475, 482, | |
| 152 | 489, 497, 505, 513, 522, 530, 539, 549, | |
| 153 | 559, 569, 579, 590, 602, 614, 626, 640, | |
| 154 | 654, 668, 684, 700, 717, 736, 755, 775, | |
| 155 | 796, 819, 843, 869, 896, 925, 955, 988, | |
| 156 | 1022, 1058, 1098, 1139, 1184, 1232, 1282, 1336, | |
| 157 | }; | |
| 158 | ||
| 159 | static const uint16_t CODECHAL_VP9_QUANT_AC[CODEC_VP9_QINDEX_RANGE] = { | |
| 160 | 4, 8, 9, 10, 11, 12, 13, 14, | |
| 161 | 15, 16, 17, 18, 19, 20, 21, 22, | |
| 162 | 23, 24, 25, 26, 27, 28, 29, 30, | |
| 163 | 31, 32, 33, 34, 35, 36, 37, 38, | |
| 164 | 39, 40, 41, 42, 43, 44, 45, 46, | |
| 165 | 47, 48, 49, 50, 51, 52, 53, 54, | |
| 166 | 55, 56, 57, 58, 59, 60, 61, 62, | |
| 167 | 63, 64, 65, 66, 67, 68, 69, 70, | |
| 168 | 71, 72, 73, 74, 75, 76, 77, 78, | |
| 169 | 79, 80, 81, 82, 83, 84, 85, 86, | |
| 170 | 87, 88, 89, 90, 91, 92, 93, 94, | |
| 171 | 95, 96, 97, 98, 99, 100, 101, 102, | |
| 172 | 104, 106, 108, 110, 112, 114, 116, 118, | |
| 173 | 120, 122, 124, 126, 128, 130, 132, 134, | |
| 174 | 136, 138, 140, 142, 144, 146, 148, 150, | |
| 175 | 152, 155, 158, 161, 164, 167, 170, 173, | |
| 176 | 176, 179, 182, 185, 188, 191, 194, 197, | |
| 177 | 200, 203, 207, 211, 215, 219, 223, 227, | |
| 178 | 231, 235, 239, 243, 247, 251, 255, 260, | |
| 179 | 265, 270, 275, 280, 285, 290, 295, 300, | |
| 180 | 305, 311, 317, 323, 329, 335, 341, 347, | |
| 181 | 353, 359, 366, 373, 380, 387, 394, 401, | |
| 182 | 408, 416, 424, 432, 440, 448, 456, 465, | |
| 183 | 474, 483, 492, 501, 510, 520, 530, 540, | |
| 184 | 550, 560, 571, 582, 593, 604, 615, 627, | |
| 185 | 639, 651, 663, 676, 689, 702, 715, 729, | |
| 186 | 743, 757, 771, 786, 801, 816, 832, 848, | |
| 187 | 864, 881, 898, 915, 933, 951, 969, 988, | |
| 188 | 1007, 1026, 1046, 1066, 1087, 1108, 1129, 1151, | |
| 189 | 1173, 1196, 1219, 1243, 1267, 1292, 1317, 1343, | |
| 190 | 1369, 1396, 1423, 1451, 1479, 1508, 1537, 1567, | |
| 191 | 1597, 1628, 1660, 1692, 1725, 1759, 1793, 1828, | |
| 192 | }; | |
| 193 | ||
| 194 | static const uint16_t CODECHAL_VP9_QUANT_DC_10[CODEC_VP9_QINDEX_RANGE] = { | |
| 195 | 4, 9, 10, 13, 15, 17, 20, 22, | |
| 196 | 25, 28, 31, 34, 37, 40, 43, 47, | |
| 197 | 50, 53, 57, 60, 64, 68, 71, 75, | |
| 198 | 78, 82, 86, 90, 93, 97, 101, 105, | |
| 199 | 109, 113, 116, 120, 124, 128, 132, 136, | |
| 200 | 140, 143, 147, 151, 155, 159, 163, 166, | |
| 201 | 170, 174, 178, 182, 185, 189, 193, 197, | |
| 202 | 200, 204, 208, 212, 215, 219, 223, 226, | |
| 203 | 230, 233, 237, 241, 244, 248, 251, 255, | |
| 204 | 259, 262, 266, 269, 273, 276, 280, 283, | |
| 205 | 287, 290, 293, 297, 300, 304, 307, 310, | |
| 206 | 314, 317, 321, 324, 327, 331, 334, 337, | |
| 207 | 343, 350, 356, 362, 369, 375, 381, 387, | |
| 208 | 394, 400, 406, 412, 418, 424, 430, 436, | |
| 209 | 442, 448, 454, 460, 466, 472, 478, 484, | |
| 210 | 490, 499, 507, 516, 525, 533, 542, 550, | |
| 211 | 559, 567, 576, 584, 592, 601, 609, 617, | |
| 212 | 625, 634, 644, 655, 666, 676, 687, 698, | |
| 213 | 708, 718, 729, 739, 749, 759, 770, 782, | |
| 214 | 795, 807, 819, 831, 844, 856, 868, 880, | |
| 215 | 891, 906, 920, 933, 947, 961, 975, 988, | |
| 216 | 1001, 1015, 1030, 1045, 1061, 1076, 1090, 1105, | |
| 217 | 1120, 1137, 1153, 1170, 1186, 1202, 1218, 1236, | |
| 218 | 1253, 1271, 1288, 1306, 1323, 1342, 1361, 1379, | |
| 219 | 1398, 1416, 1436, 1456, 1476, 1496, 1516, 1537, | |
| 220 | 1559, 1580, 1601, 1624, 1647, 1670, 1692, 1717, | |
| 221 | 1741, 1766, 1791, 1817, 1844, 1871, 1900, 1929, | |
| 222 | 1958, 1990, 2021, 2054, 2088, 2123, 2159, 2197, | |
| 223 | 2236, 2276, 2319, 2363, 2410, 2458, 2508, 2561, | |
| 224 | 2616, 2675, 2737, 2802, 2871, 2944, 3020, 3102, | |
| 225 | 3188, 3280, 3375, 3478, 3586, 3702, 3823, 3953, | |
| 226 | 4089, 4236, 4394, 4559, 4737, 4929, 5130, 5347, | |
| 227 | }; | |
| 228 | ||
| 229 | static const uint16_t CODECHAL_VP9_QUANT_AC_10[CODEC_VP9_QINDEX_RANGE] = { | |
| 230 | 4, 9, 11, 13, 16, 18, 21, 24, | |
| 231 | 27, 30, 33, 37, 40, 44, 48, 51, | |
| 232 | 55, 59, 63, 67, 71, 75, 79, 83, | |
| 233 | 88, 92, 96, 100, 105, 109, 114, 118, | |
| 234 | 122, 127, 131, 136, 140, 145, 149, 154, | |
| 235 | 158, 163, 168, 172, 177, 181, 186, 190, | |
| 236 | 195, 199, 204, 208, 213, 217, 222, 226, | |
| 237 | 231, 235, 240, 244, 249, 253, 258, 262, | |
| 238 | 267, 271, 275, 280, 284, 289, 293, 297, | |
| 239 | 302, 306, 311, 315, 319, 324, 328, 332, | |
| 240 | 337, 341, 345, 349, 354, 358, 362, 367, | |
| 241 | 371, 375, 379, 384, 388, 392, 396, 401, | |
| 242 | 409, 417, 425, 433, 441, 449, 458, 466, | |
| 243 | 474, 482, 490, 498, 506, 514, 523, 531, | |
| 244 | 539, 547, 555, 563, 571, 579, 588, 596, | |
| 245 | 604, 616, 628, 640, 652, 664, 676, 688, | |
| 246 | 700, 713, 725, 737, 749, 761, 773, 785, | |
| 247 | 797, 809, 825, 841, 857, 873, 889, 905, | |
| 248 | 922, 938, 954, 970, 986, 1002, 1018, 1038, | |
| 249 | 1058, 1078, 1098, 1118, 1138, 1158, 1178, 1198, | |
| 250 | 1218, 1242, 1266, 1290, 1314, 1338, 1362, 1386, | |
| 251 | 1411, 1435, 1463, 1491, 1519, 1547, 1575, 1603, | |
| 252 | 1631, 1663, 1695, 1727, 1759, 1791, 1823, 1859, | |
| 253 | 1895, 1931, 1967, 2003, 2039, 2079, 2119, 2159, | |
| 254 | 2199, 2239, 2283, 2327, 2371, 2415, 2459, 2507, | |
| 255 | 2555, 2603, 2651, 2703, 2755, 2807, 2859, 2915, | |
| 256 | 2971, 3027, 3083, 3143, 3203, 3263, 3327, 3391, | |
| 257 | 3455, 3523, 3591, 3659, 3731, 3803, 3876, 3952, | |
| 258 | 4028, 4104, 4184, 4264, 4348, 4432, 4516, 4604, | |
| 259 | 4692, 4784, 4876, 4972, 5068, 5168, 5268, 5372, | |
| 260 | 5476, 5584, 5692, 5804, 5916, 6032, 6148, 6268, | |
| 261 | 6388, 6512, 6640, 6768, 6900, 7036, 7172, 7312, | |
| 262 | }; | |
| 263 | ||
| 264 | typedef struct _CODEC_VP9_SEG_PARAMS | |
| 265 | { | |
| 266 | union | |
| 267 | { | |
| 268 | struct | |
| 269 | { | |
| 270 | uint16_t SegmentReferenceEnabled : 1; // [0..1] | |
| 271 | uint16_t SegmentReference : 2; // [0..3] | |
| 272 | uint16_t SegmentReferenceSkipped : 1; // [0..1] | |
| 273 | uint16_t ReservedField3 : 12; // [0] | |
| 274 | } fields; | |
| 275 | uint32_t value; | |
| 276 | } SegmentFlags; | |
| 277 | ||
| 278 | uint8_t FilterLevel[4][2]; // [0..63] | |
| 279 | uint16_t LumaACQuantScale; // | |
| 280 | uint16_t LumaDCQuantScale; // | |
| 281 | uint16_t ChromaACQuantScale; // | |
| 282 | uint16_t ChromaDCQuantScale; // | |
| 283 | } CODEC_VP9_SEG_PARAMS, *PCODEC_VP9_SEG_PARAMS; | |
| 284 | ||
| 285 | #endif | |
| 286 |
| 0 | /* | |
| 1 | * Copyright (c) 2017-2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_decode_av1.h | |
| 23 | //! \brief Defines decode AV1 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to AV1 decode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_DECODE_AV1_H__ | |
| 27 | #define __CODEC_DEF_DECODE_AV1_H__ | |
| 28 | ||
| 29 | #include "codec_def_common_av1.h" | |
| 30 | ||
| 31 | #define CODECHAL_MAX_DPB_NUM_AV1 127 // Maximum number of uncompressed decoded buffers that driver supports for non-LST mode | |
| 32 | #define CODEC_NUM_REF_AV1_TEMP_BUFFERS 8 | |
| 33 | #define CODEC_NUM_AV1_SECOND_BB 64 | |
| 34 | #define CODEC_NUM_AV1_TEMP_BUFFERS (CODEC_NUM_REF_AV1_TEMP_BUFFERS + 1) //!< Temp buffers number | |
| 35 | #define CODECHAL_MAX_DPB_NUM_LST_AV1 255 // Maximum number of uncompressed decoded buffers that driver supports with LST support | |
| 36 | ||
| 37 | // AV1 parameters definition | |
| 38 | ||
| 39 | //! | |
| 40 | //! \struct CodecAv1FilmGrainParams | |
| 41 | //! \brief Define the film grain parameters for AV1 | |
| 42 | //! | |
| 43 | struct CodecAv1FilmGrainParams | |
| 44 | { | |
| 45 | union | |
| 46 | { | |
| 47 | struct | |
| 48 | { | |
| 49 | uint32_t m_applyGrain : 1; //!< apply Grain flag | |
| 50 | uint32_t m_chromaScalingFromLuma : 1; //!< chroma scaling from luma | |
| 51 | uint32_t m_grainScalingMinus8 : 2; //!< Grain scaling minus 8 | |
| 52 | uint32_t m_arCoeffLag : 2; //!< AR Coeff lag | |
| 53 | uint32_t m_arCoeffShiftMinus6 : 2; //!< AR coeff shift minus 6 | |
| 54 | uint32_t m_grainScaleShift : 2; //!< grain scale shift | |
| 55 | uint32_t m_overlapFlag : 1; //!< overlap flag | |
| 56 | uint32_t m_clipToRestrictedRange : 1; //!< clip to restricted range flag | |
| 57 | uint32_t m_reservedBits : 20; //!< reserved bits | |
| 58 | } m_fields; | |
| 59 | uint32_t m_value; //!< film grain info flag value | |
| 60 | } m_filmGrainInfoFlags; | |
| 61 | ||
| 62 | uint16_t m_randomSeed; //!< random seed | |
| 63 | uint8_t m_numYPoints; //!< num Y points, range [0..14] | |
| 64 | uint8_t m_pointYValue[14]; //!< point Y value array | |
| 65 | uint8_t m_pointYScaling[14]; //!< point Y scaling array | |
| 66 | uint8_t m_numCbPoints; //!< num Cb Points, range [0..10] | |
| 67 | uint8_t m_pointCbValue[10]; //!< point Cb Value | |
| 68 | uint8_t m_pointCbScaling[10]; //!< point Cb Scaling | |
| 69 | uint8_t m_numCrPoints; //!< num Cr Points, range [0..10] | |
| 70 | uint8_t m_pointCrValue[10]; //!< point Cr Value | |
| 71 | uint8_t m_pointCrScaling[10]; //!< point Cr Scaling | |
| 72 | int8_t m_arCoeffsY[24]; //!< ar coeffs for Y, range [-128..127] | |
| 73 | int8_t m_arCoeffsCb[25]; //!< ar coeffs for Cb, range [-128..127] | |
| 74 | int8_t m_arCoeffsCr[25]; //!< ar coeffs for Cr, range [-128..127] | |
| 75 | uint8_t m_cbMult; //!< cb multipler | |
| 76 | uint8_t m_cbLumaMult; //!< cb Luma Multipler | |
| 77 | uint16_t m_cbOffset; //!< cb offset, range [0..512] | |
| 78 | uint8_t m_crMult; //!< Cr multipler | |
| 79 | uint8_t m_crLumaMult; //!< Cr Luma Multipler | |
| 80 | uint16_t m_crOffset; //!< Cr Offset, range [0..512] | |
| 81 | uint32_t m_reservedDws[4]; //!< reserved DWs | |
| 82 | }; | |
| 83 | ||
| 84 | //! | |
| 85 | //! \struct CodecAv1PicParams | |
| 86 | //! \brief Define AV1 picture parameters | |
| 87 | //! | |
| 88 | struct CodecAv1PicParams | |
| 89 | { | |
| 90 | CODEC_PICTURE m_currPic; | |
| 91 | CODEC_PICTURE m_currDisplayPic; | |
| 92 | uint8_t m_profile; // [0..2] | |
| 93 | uint8_t m_anchorFrameInsertion; | |
| 94 | uint8_t m_anchorFrameNum; | |
| 95 | PMOS_SURFACE m_anchorFrameList; | |
| 96 | ||
| 97 | // sequence info | |
| 98 | uint8_t m_orderHintBitsMinus1; // [0..7] | |
| 99 | uint8_t m_bitDepthIdx; // [0..2] | |
| 100 | uint8_t m_matrixCoefficients; // [0..14] | |
| 101 | uint8_t m_reserved8b; | |
| 102 | ||
| 103 | union | |
| 104 | { | |
| 105 | struct | |
| 106 | { | |
| 107 | uint32_t m_stillPicture : 1; | |
| 108 | uint32_t m_use128x128Superblock : 1; | |
| 109 | uint32_t m_enableFilterIntra : 1; | |
| 110 | uint32_t m_enableIntraEdgeFilter : 1; | |
| 111 | ||
| 112 | // read_compound_tools | |
| 113 | uint32_t m_enableInterintraCompound : 1; // [0..1] | |
| 114 | uint32_t m_enableMaskedCompound : 1; // [0..1] | |
| 115 | ||
| 116 | uint32_t m_enableDualFilter : 1; | |
| 117 | uint32_t m_enableOrderHint : 1; | |
| 118 | uint32_t m_enableJntComp : 1; | |
| 119 | uint32_t m_enableCdef : 1; | |
| 120 | uint32_t m_reserved3b : 3; | |
| 121 | ||
| 122 | uint32_t m_monoChrome : 1; | |
| 123 | uint32_t m_colorRange : 1; | |
| 124 | uint32_t m_subsamplingX : 1; | |
| 125 | uint32_t m_subsamplingY : 1; | |
| 126 | uint32_t m_chromaSamplePosition : 1; | |
| 127 | uint32_t m_filmGrainParamsPresent : 1; | |
| 128 | uint32_t m_reservedSeqInfoBits : 13; | |
| 129 | } m_fields; | |
| 130 | uint32_t m_value; | |
| 131 | } m_seqInfoFlags; | |
| 132 | ||
| 133 | // frame info | |
| 134 | union | |
| 135 | { | |
| 136 | struct | |
| 137 | { | |
| 138 | uint32_t m_frameType : 2; | |
| 139 | uint32_t m_showFrame : 1; | |
| 140 | uint32_t m_showableFrame : 1; | |
| 141 | uint32_t m_errorResilientMode : 1; | |
| 142 | uint32_t m_disableCdfUpdate : 1; | |
| 143 | uint32_t m_allowScreenContentTools : 1; // [0..1] | |
| 144 | uint32_t m_forceIntegerMv : 1; // [0..1] | |
| 145 | uint32_t m_allowIntrabc : 1; | |
| 146 | uint32_t m_useSuperres : 1; | |
| 147 | uint32_t m_allowHighPrecisionMv : 1; | |
| 148 | uint32_t m_isMotionModeSwitchable : 1; | |
| 149 | uint32_t m_useRefFrameMvs : 1; | |
| 150 | uint32_t m_disableFrameEndUpdateCdf : 1; | |
| 151 | uint32_t m_uniformTileSpacingFlag : 1; | |
| 152 | uint32_t m_allowWarpedMotion : 1; | |
| 153 | uint32_t m_largeScaleTile : 1; | |
| 154 | uint32_t m_reservedPicInfoBits : 15; | |
| 155 | } m_fields; | |
| 156 | uint32_t m_value; | |
| 157 | } m_picInfoFlags; | |
| 158 | ||
| 159 | uint16_t m_frameWidthMinus1; // [0..65535] //!< Super-Res downscaled resolution | |
| 160 | uint16_t m_frameHeightMinus1; // [0..65535] //!< Super-Res downscaled resolution | |
| 161 | ||
| 162 | CODEC_PICTURE m_refFrameMap[8]; | |
| 163 | uint8_t m_refFrameIdx[7]; // [0..7] | |
| 164 | uint8_t m_primaryRefFrame; // [0..7] | |
| 165 | ||
| 166 | uint16_t m_outputFrameWidthInTilesMinus1;// [0..65535] | |
| 167 | uint16_t m_outputFrameHeightInTilesMinus1;// [0..65535] | |
| 168 | uint32_t m_reserved32b2; | |
| 169 | ||
| 170 | // deblocking filter | |
| 171 | uint8_t m_filterLevel[2]; // [0..63] | |
| 172 | uint8_t m_filterLevelU; // [0..63] | |
| 173 | uint8_t m_filterLevelV; // [0..63] | |
| 174 | union | |
| 175 | { | |
| 176 | struct | |
| 177 | { | |
| 178 | uint8_t m_sharpnessLevel : 3; // [0..7] | |
| 179 | uint8_t m_modeRefDeltaEnabled : 1; | |
| 180 | uint8_t m_modeRefDeltaUpdate : 1; | |
| 181 | uint8_t m_reservedField : 3; // [0] | |
| 182 | } m_fields; | |
| 183 | uint8_t m_value; | |
| 184 | } m_loopFilterInfoFlags; | |
| 185 | ||
| 186 | uint8_t m_orderHint; | |
| 187 | uint8_t m_superresScaleDenominator; // [9..16] | |
| 188 | uint8_t m_interpFilter; // [0..9] | |
| 189 | ||
| 190 | int8_t m_refDeltas[8]; // [-63..63] | |
| 191 | int8_t m_modeDeltas[2]; // [-63..63] | |
| 192 | ||
| 193 | // quantization | |
| 194 | uint16_t m_baseQindex; // [0..255] | |
| 195 | int8_t m_yDcDeltaQ; // [-63..63] | |
| 196 | int8_t m_uDcDeltaQ; // [-63..63] | |
| 197 | int8_t m_uAcDeltaQ; // [-63..63] | |
| 198 | int8_t m_vDcDeltaQ; // [-63..63] | |
| 199 | int8_t m_vAcDeltaQ; // [-63..63] | |
| 200 | uint8_t m_reserved8b2; | |
| 201 | ||
| 202 | // quantization_matrix | |
| 203 | union | |
| 204 | { | |
| 205 | struct | |
| 206 | { | |
| 207 | uint16_t m_usingQmatrix : 1; | |
| 208 | // valid only when using_qmatrix is 1. | |
| 209 | uint16_t m_qmY : 4; // [0..15] | |
| 210 | uint16_t m_qmU : 4; // [0..15] | |
| 211 | uint16_t m_qmV : 4; // [0..15] | |
| 212 | uint16_t m_reservedField : 3; // [0] | |
| 213 | } m_fields; | |
| 214 | uint16_t m_value; | |
| 215 | } m_qMatrixFlags; | |
| 216 | ||
| 217 | union | |
| 218 | { | |
| 219 | struct | |
| 220 | { | |
| 221 | // delta_q parameters | |
| 222 | uint32_t m_deltaQPresentFlag : 1; // [0..1] | |
| 223 | uint32_t m_log2DeltaQRes : 2; // [0..3] | |
| 224 | ||
| 225 | // delta_lf parameters | |
| 226 | uint32_t m_deltaLfPresentFlag : 1; // [0..1] | |
| 227 | uint32_t m_log2DeltaLfRes : 2; // [0..3] | |
| 228 | uint32_t m_deltaLfMulti : 1; // [0..1] | |
| 229 | ||
| 230 | // read_tx_mode | |
| 231 | uint32_t m_txMode : 2; // [0..3] | |
| 232 | ||
| 233 | // read_frame_reference_mode | |
| 234 | uint32_t m_referenceMode : 2; // [0..3] will be replaced by reference_select | |
| 235 | uint32_t m_reducedTxSetUsed : 1; // [0..1] | |
| 236 | ||
| 237 | // tiles | |
| 238 | uint32_t m_skipModePresent : 1; // [0..1] | |
| 239 | uint32_t m_reservedField : 19; // [0] | |
| 240 | } m_fields; | |
| 241 | uint32_t m_value; | |
| 242 | } m_modeControlFlags; | |
| 243 | ||
| 244 | CodecAv1SegmentsParams m_av1SegData; //!< segment data | |
| 245 | ||
| 246 | uint8_t m_tileCols; | |
| 247 | uint16_t m_widthInSbsMinus1[64]; //!< note: 64 not 63 | |
| 248 | uint8_t m_tileRows; | |
| 249 | uint16_t m_heightInSbsMinus1[64]; | |
| 250 | ||
| 251 | uint16_t m_tileCountMinus1; | |
| 252 | uint16_t m_contextUpdateTileId; | |
| 253 | ||
| 254 | // CDEF | |
| 255 | uint8_t m_cdefDampingMinus3; // [0..3] | |
| 256 | uint8_t m_cdefBits; // [0..3] | |
| 257 | uint8_t m_cdefYStrengths[8]; // [0..63] | |
| 258 | uint8_t m_cdefUvStrengths[8]; // [0..63] | |
| 259 | ||
| 260 | union | |
| 261 | { | |
| 262 | struct | |
| 263 | { | |
| 264 | uint16_t m_yframeRestorationType : 2; // [0..3] | |
| 265 | uint16_t m_cbframeRestorationType : 2; // [0..3] | |
| 266 | uint16_t m_crframeRestorationType : 2; // [0..3] | |
| 267 | uint16_t m_lrUnitShift : 2; // [0..2] | |
| 268 | uint16_t m_lrUvShift : 1; // [0..1] | |
| 269 | uint16_t m_reservedField : 7; // [0] | |
| 270 | } m_fields; | |
| 271 | uint16_t m_value; | |
| 272 | } m_loopRestorationFlags; | |
| 273 | ||
| 274 | // global motion | |
| 275 | CodecAv1WarpedMotionParams m_wm[7]; | |
| 276 | CodecAv1FilmGrainParams m_filmGrainParams; | |
| 277 | ||
| 278 | uint32_t m_bsBytesInBuffer; | |
| 279 | uint32_t m_statusReportFeedbackNumber; | |
| 280 | ||
| 281 | // Below are parameters for driver internal use only, not corresponding to any DDI parameter | |
| 282 | bool m_losslessMode; //!< frame lossless mode | |
| 283 | uint16_t m_superResUpscaledWidthMinus1; //!< Super-Res upscaled width, [0..65535] | |
| 284 | uint16_t m_superResUpscaledHeightMinus1; //!< Super-Res upscaled height, [0..65535] | |
| 285 | uint8_t m_activeRefBitMaskMfmv[7]; //!< active reference bitmask for Motion Field Projection, [0]: LAST_FRAME, [6]: ALTREF | |
| 286 | uint8_t m_refFrameSide[8]; //!< ref_frame_side for each reference | |
| 287 | }; | |
| 288 | ||
| 289 | struct CodecAv1TileParams | |
| 290 | { | |
| 291 | uint32_t m_bsTileDataLocation; | |
| 292 | uint32_t m_bsTileBytesInBuffer; | |
| 293 | uint16_t m_badBSBufferChopping; | |
| 294 | uint16_t m_tileRow; | |
| 295 | uint16_t m_tileColumn; | |
| 296 | uint16_t m_tileIndex; | |
| 297 | uint16_t m_reserved16b; | |
| 298 | uint16_t m_startTileIdx; | |
| 299 | uint16_t m_endTileIdx; | |
| 300 | uint16_t m_tile_idx_in_tile_list; | |
| 301 | CODEC_PICTURE m_anchorFrameIdx; | |
| 302 | uint32_t m_bsTilePayloadSizeInBytes; | |
| 303 | }; | |
| 304 | ||
| 305 | #endif // __CODEC_DEF_DECODE_AV1_H__ | |
| 306 |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_decode_avc.h | |
| 23 | //! \brief Defines decode AVC types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to AVC decode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_DECODE_AVC_H__ | |
| 27 | #define __CODEC_DEF_DECODE_AVC_H__ | |
| 28 | ||
| 29 | #include "codec_def_common_avc.h" | |
| 30 | ||
| 31 | //Check whether interview prediction is used through POC | |
| 32 | #define CodecHal_IsInterviewPred(currPic, currPoc, avcRefListIdx) ( ((avcRefListIdx)!=(currPic).FrameIdx) && \ | |
| 33 | (!CodecHal_PictureIsTopField(currPic) && (ppAvcRefList[avcRefListIdx]->iFieldOrderCnt[1] == (currPoc)[1]) || \ | |
| 34 | !CodecHal_PictureIsBottomField(currPic) && (ppAvcRefList[avcRefListIdx]->iFieldOrderCnt[0] == (currPoc)[0])) && \ | |
| 35 | ((currPic).FrameIdx != 0x7f)) | |
| 36 | ||
| 37 | typedef struct _CODEC_AVC_DMV_LIST | |
| 38 | { | |
| 39 | uint8_t ucFrameId; | |
| 40 | bool bInUse; | |
| 41 | bool bReUse; | |
| 42 | } CODEC_AVC_DMV_LIST, *PCODEC_AVC_DMV_LIST; | |
| 43 | ||
| 44 | //! | |
| 45 | //! \enum AvcChromaFormatIdc | |
| 46 | //! \brief AVC chroma format Idc | |
| 47 | //! | |
| 48 | enum AvcChromaFormatIdc | |
| 49 | { | |
| 50 | avcChromaFormatMono = 0, | |
| 51 | avcChromaFormat420 = 1, | |
| 52 | avcChromaFormat422 = 2, | |
| 53 | avcChromaFormat444 = 3, | |
| 54 | }; | |
| 55 | ||
| 56 | // H.264 Picture Parameters Buffer | |
| 57 | typedef struct _CODEC_AVC_PIC_PARAMS | |
| 58 | { | |
| 59 | /*! \brief Uncompressed destination surface of the frame for the current decoded picture. | |
| 60 | * | |
| 61 | * The long_term_ref_flag has no meaning. The valid value range for Curr.FrameIdx is [0..126]. Value 127 or 0x7F can be treated as an invalid surface index. | |
| 62 | */ | |
| 63 | CODEC_PICTURE CurrPic; | |
| 64 | /*! \brief FrameIdx for each entry specifies the surface index for all pictures that are or will be referred to by the current or future pictures. | |
| 65 | * | |
| 66 | * The valid entries are indexed from 0 to 126, inclusive. The PicFlags of non-valid entries (including the picture of the entry which is not referred by current picture or future pictures) should take value PICTURE_INVALID. A PicFlags setting of PICTURE_LONG_TERM_REFERENCE indicates if the picture is a long term reference or not. | |
| 67 | * NOTE: for interlace (field) pictures, the FrameIdx field of two RefFrameList entries may have same value and point to same reference surface. And in this case, application should allocate buffer size with double picture height to hold the whole picture. | |
| 68 | */ | |
| 69 | CODEC_PICTURE RefFrameList[CODEC_AVC_MAX_NUM_REF_FRAME]; | |
| 70 | ||
| 71 | uint16_t pic_width_in_mbs_minus1; //!< Same as AVC syntax element. | |
| 72 | /*! \brief The height of the frame in MBs minus 1. | |
| 73 | * | |
| 74 | * Derived from pic_height_in_map_units_minus1: pic_height_in_map_units_minus1 << uint16_t(frame_mbs_only_flag == 0) | |
| 75 | */ | |
| 76 | uint16_t pic_height_in_mbs_minus1; | |
| 77 | uint8_t bit_depth_luma_minus8; //!< Same as AVC syntax element. | |
| 78 | uint8_t bit_depth_chroma_minus8; //!< Same as AVC syntax element. | |
| 79 | uint8_t num_ref_frames; //!< Same as AVC syntax element. | |
| 80 | /*! \brief Contains the picture order counts (POC) for the current frame | |
| 81 | * | |
| 82 | * If field_pic_flag is 0: | |
| 83 | * \n - CurrFieldOrderCnt[0] contains the top field order count for the current picture | |
| 84 | * \n - CurrFieldOrderCnt[1] contains the bottom field order count for the current picture | |
| 85 | * \n If field_pic_flag is 1 and CurrPic.PicFlags indicates that this is a top field: | |
| 86 | * \n - CurrFieldOrderCnt[0] contains the top field order count for the current picture | |
| 87 | * \n - CurrFieldOrderCnt[1] | |
| 88 | * \n If field_pic_flag is 1 and CurrPic.PicFlags indicates that this is a bottom field: | |
| 89 | * \n - CurrFieldOrderCnt[0] should be 0 or ignored | |
| 90 | * \n - CurrFieldOrderCnt[1] contains the bottom field order count for the current picture | |
| 91 | */ | |
| 92 | int32_t CurrFieldOrderCnt[2]; | |
| 93 | /*! \brief Contains the POCs for the reference frames in RefFrameList. | |
| 94 | * | |
| 95 | * For each entry FieldOrderCntList[i][j]: | |
| 96 | * \n - i: the picture index | |
| 97 | * \n - j: 0 specifies the top field order count and 1 specifies the bottom field order count | |
| 98 | * \n If a entry i in RefFrameList is not relevant (it is not used for reference) or valid, the entry FieldOrderCount[i][0 and 1] should be 0. | |
| 99 | */ | |
| 100 | int32_t FieldOrderCntList[16][2]; | |
| 101 | ||
| 102 | union | |
| 103 | { | |
| 104 | struct | |
| 105 | { | |
| 106 | uint32_t chroma_format_idc : 2; //!< Same as AVC syntax element. | |
| 107 | uint32_t residual_colour_transform_flag : 1; //!< Same as AVC syntax element. | |
| 108 | uint32_t frame_mbs_only_flag : 1; //!< Same as AVC syntax element. | |
| 109 | uint32_t mb_adaptive_frame_field_flag : 1; //!< Same as AVC syntax element. | |
| 110 | uint32_t direct_8x8_inference_flag : 1; //!< Same as AVC syntax element. | |
| 111 | uint32_t : 1; | |
| 112 | uint32_t log2_max_frame_num_minus4 : 4; //!< Same as AVC syntax element. | |
| 113 | uint32_t pic_order_cnt_type : 2; //!< Same as AVC syntax element. | |
| 114 | uint32_t log2_max_pic_order_cnt_lsb_minus4 : 4; //!< Same as AVC syntax element. | |
| 115 | uint32_t delta_pic_order_always_zero_flag : 1; //!< Same as AVC syntax element. | |
| 116 | }; | |
| 117 | uint32_t value; | |
| 118 | } seq_fields; | |
| 119 | ||
| 120 | uint8_t num_slice_groups_minus1; //!< Same as AVC syntax element. | |
| 121 | uint8_t slice_group_map_type; //!< Same as AVC syntax element. | |
| 122 | uint16_t slice_group_change_rate_minus1; //!< Same as AVC syntax element. | |
| 123 | char pic_init_qp_minus26; //!< Same as AVC syntax element. | |
| 124 | char chroma_qp_index_offset; //!< Same as AVC syntax element. | |
| 125 | char second_chroma_qp_index_offset; //!< Same as AVC syntax element. | |
| 126 | ||
| 127 | union | |
| 128 | { | |
| 129 | struct | |
| 130 | { | |
| 131 | uint32_t entropy_coding_mode_flag : 1; //!< Same as AVC syntax element. | |
| 132 | uint32_t weighted_pred_flag : 1; //!< Same as AVC syntax element. | |
| 133 | uint32_t weighted_bipred_idc : 2; //!< Same as AVC syntax element. | |
| 134 | uint32_t transform_8x8_mode_flag : 1; //!< Same as AVC syntax element. | |
| 135 | uint32_t field_pic_flag : 1; //!< Same as AVC syntax element. | |
| 136 | uint32_t constrained_intra_pred_flag : 1; //!< Same as AVC syntax element. | |
| 137 | uint32_t pic_order_present_flag : 1; //!< Same as AVC syntax element. | |
| 138 | uint32_t deblocking_filter_control_present_flag : 1; //!< Same as AVC syntax element. | |
| 139 | uint32_t redundant_pic_cnt_present_flag : 1; //!< Same as AVC syntax element. | |
| 140 | uint32_t reference_pic_flag : 1; //!< Same as AVC syntax element. | |
| 141 | uint32_t IntraPicFlag : 1; //!< All MBs in frame use intra prediction mode. | |
| 142 | }; | |
| 143 | uint32_t value; | |
| 144 | } pic_fields; | |
| 145 | ||
| 146 | // Short format specific | |
| 147 | uint8_t num_ref_idx_l0_active_minus1; //!< Same as AVC syntax element. | |
| 148 | uint8_t num_ref_idx_l1_active_minus1; //!< Same as AVC syntax element. | |
| 149 | /*! \brief Contains the value of FrameNum or LongTermRefIdx depending on the PicFlags for the frame. | |
| 150 | * | |
| 151 | * Each entry in FrameNumList has a corresponding entry in RefFrameList, if an entry in RefFrameList is not relevant (it is not used for reference) or valid, the entry in FrameNumList should be 0. | |
| 152 | */ | |
| 153 | uint16_t FrameNumList[16]; | |
| 154 | /*! \brief Denotes "non-existing" frames as defined in the AVC specification. | |
| 155 | * | |
| 156 | * The flag is accessed by: Flag(i) = (NonExistingFrameFlags >> i) & 1. If Flag(i) is 1, frame i is marked as "non-existing", otherwise the frame is existing. | |
| 157 | */ | |
| 158 | uint16_t NonExistingFrameFlags; | |
| 159 | /*! \brief Denotes "used for reference" frames as defined in the AVC specification. | |
| 160 | * | |
| 161 | * The flag is accessed by: | |
| 162 | * \n - FlagTop(i) = (UsedForReferenceFlags >> (2 * i)) & 1 | |
| 163 | * \n - FlagBottom(i) = (UsedForReferenceFlags >> (2 * i + 1)) & 1 | |
| 164 | * \n If FlagTop(i) is 1, the top field or frame numger i is marked as "used for reference"; if FlagBottom(i) is 1 then then bottom field of frame i is marked as "used for reference". If either is 0 then the frame is not marked as "used for reference". | |
| 165 | */ | |
| 166 | uint32_t UsedForReferenceFlags; | |
| 167 | uint16_t frame_num; //!< Same as AVC syntax element. | |
| 168 | ||
| 169 | /*! \brief Arbitrary number set by the host decoder to use as a tag in the status report feedback data. | |
| 170 | * | |
| 171 | * The value should not equal 0, and should be different in each call to Execute. | |
| 172 | */ | |
| 173 | uint32_t StatusReportFeedbackNumber; | |
| 174 | } CODEC_AVC_PIC_PARAMS, *PCODEC_AVC_PIC_PARAMS; | |
| 175 | ||
| 176 | // H.264 Decode Slice Parameter Buffer (Long/Short format) | |
| 177 | typedef struct _CODEC_AVC_SLICE_PARAMS | |
| 178 | { | |
| 179 | uint32_t slice_data_size; //!< Number of bytes in the bitstream buffer for this slice. | |
| 180 | uint32_t slice_data_offset; //!< The offset to the NAL start code for this slice. | |
| 181 | ||
| 182 | // Long format specific | |
| 183 | uint16_t slice_data_bit_offset; //!< Bit offset from NAL start code to the beginning of slice data. | |
| 184 | uint16_t first_mb_in_slice; //!< Same as AVC syntax element. | |
| 185 | uint16_t NumMbsForSlice; //!< Number of MBs in the bitstream associated with this slice. | |
| 186 | uint8_t slice_type; //!< Same as AVC syntax element. | |
| 187 | uint8_t direct_spatial_mv_pred_flag; //!< Same as AVC syntax element. | |
| 188 | uint8_t num_ref_idx_l0_active_minus1; //!< Same as AVC syntax element. | |
| 189 | uint8_t num_ref_idx_l1_active_minus1; //!< Same as AVC syntax element. | |
| 190 | uint8_t cabac_init_idc; //!< Same as AVC syntax element. | |
| 191 | char slice_qp_delta; //!< Same as AVC syntax element. | |
| 192 | uint8_t disable_deblocking_filter_idc; //!< Same as AVC syntax element. | |
| 193 | char slice_alpha_c0_offset_div2; //!< Same as AVC syntax element. | |
| 194 | char slice_beta_offset_div2; //!< Same as AVC syntax element. | |
| 195 | /*! \brief Specifies the reference picture lists 0 and 1 | |
| 196 | * | |
| 197 | * Contains field/frame information concerning the reference in PicFlags. RefPicList[i][j]: | |
| 198 | * \n - i: the reference picture list (0 or 1) | |
| 199 | * \n - j: if the PicFlags are not PICTURE_INVALID, the index variable j is a reference to entry j in teh reference picture list. | |
| 200 | */ | |
| 201 | CODEC_PICTURE RefPicList[2][32]; | |
| 202 | uint8_t luma_log2_weight_denom; //!< Same as AVC syntax element. | |
| 203 | uint8_t chroma_log2_weight_denom; //!< Same as AVC syntax element. | |
| 204 | /*! \brief Specifies the weights and offsets used for explicit mode weighted prediction. | |
| 205 | * | |
| 206 | * Weigths[i][j][k][m]: | |
| 207 | * \n - i: the reference picture list (0 or 1) | |
| 208 | * \n - j: reference to entry j in RefPicList (has range [0...31]) | |
| 209 | * \n - k: the YUV component (0 = luma, 1 = Cb chroma, 2 = Cr chroma) | |
| 210 | * \n - m: the weight or offset used in the weighted prediction process (0 = weight, 1 = offset) | |
| 211 | */ | |
| 212 | int16_t Weights[2][32][3][2]; | |
| 213 | uint16_t slice_id; //!< Same as AVC syntax element. | |
| 214 | uint16_t first_mb_in_next_slice; //!< If there is a subsequent slice, specifies first_mb_in_slice for the next slice, otherwise is 0. | |
| 215 | } CODEC_AVC_SLICE_PARAMS, *PCODEC_AVC_SLICE_PARAMS; | |
| 216 | ||
| 217 | // AVC MVC Extension Picture Parameter Set | |
| 218 | // (sent along with regular _CODEC_AVC_PIC_PARAMS) | |
| 219 | typedef struct _CODEC_MVC_EXT_PIC_PARAMS | |
| 220 | { | |
| 221 | uint16_t CurrViewID; | |
| 222 | uint8_t anchor_pic_flag; | |
| 223 | uint8_t inter_view_flag; | |
| 224 | uint8_t NumInterViewRefsL0; | |
| 225 | uint8_t NumInterViewRefsL1; | |
| 226 | union | |
| 227 | { | |
| 228 | uint8_t bPicFlags; | |
| 229 | struct | |
| 230 | { | |
| 231 | uint8_t SwitchToAVC : 1; | |
| 232 | uint8_t Reserved7Bits : 7; | |
| 233 | }; | |
| 234 | }; | |
| 235 | uint8_t Reserved8Bits; | |
| 236 | uint16_t ViewIDList[16]; | |
| 237 | uint16_t InterViewRefList[2][16]; | |
| 238 | } CODEC_MVC_EXT_PIC_PARAMS, *PCODEC_MVC_EXT_PIC_PARAMS; | |
| 239 | ||
| 240 | #endif // __CODEC_DEF_DECODE_AVC_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_decode_hevc.h | |
| 23 | //! \brief Defines decode HEVC types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to HEVC decode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_DECODE_HEVC_H__ | |
| 27 | #define __CODEC_DEF_DECODE_HEVC_H__ | |
| 28 | ||
| 29 | #include "codec_def_common_hevc.h" | |
| 30 | ||
| 31 | #define CODEC_NUM_REF_HEVC_MV_BUFFERS CODEC_MAX_NUM_REF_FRAME_HEVC | |
| 32 | #define CODEC_NUM_HEVC_MV_BUFFERS (CODEC_NUM_REF_HEVC_MV_BUFFERS + 1) | |
| 33 | #define CODEC_NUM_HEVC_INITIAL_MV_BUFFERS 6 | |
| 34 | #define HEVC_NUM_MAX_TILE_ROW 22 | |
| 35 | #define HEVC_NUM_MAX_TILE_COLUMN 20 | |
| 36 | #define CODECHAL_HEVC_MAX_NUM_SLICES_LVL_6 600 | |
| 37 | #define CODECHAL_HEVC_MAX_NUM_SLICES_LVL_5 200 | |
| 38 | #define CODECHAL_HEVC_NUM_DMEM_BUFFERS 32 | |
| 39 | ||
| 40 | #define CODEC_HEVC_NUM_SECOND_BB 32 | |
| 41 | ||
| 42 | #define CODECHAL_HEVC_MIN_LCU 16 | |
| 43 | #define CODECHAL_HEVC_MAX_DIM_FOR_MIN_LCU 4222 | |
| 44 | ||
| 45 | const uint8_t CODECHAL_DECODE_HEVC_Qmatrix_Scan_4x4[16] = { 0, 4, 1, 8, 5, 2, 12, 9, 6, 3, 13, 10, 7, 14, 11, 15 }; | |
| 46 | const uint8_t CODECHAL_DECODE_HEVC_Qmatrix_Scan_8x8[64] = | |
| 47 | { 0, 8, 1, 16, 9, 2, 24, 17, 10, 3, 32, 25, 18, 11, 4, 40, | |
| 48 | 33, 26, 19, 12, 5, 48, 41, 34, 27, 20, 13, 6, 56, 49, 42, 35, | |
| 49 | 28, 21, 14, 7, 57, 50, 43, 36, 29, 22, 15, 58, 51, 44, 37, 30, | |
| 50 | 23, 59, 52, 45, 38, 31, 60, 53, 46, 39, 61, 54, 47, 62, 55, 63 }; | |
| 51 | const uint8_t CODECHAL_DECODE_HEVC_Default_4x4[16] = { 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16 }; | |
| 52 | const uint8_t CODECHAL_DECODE_HEVC_Default_8x8_Intra[64] = | |
| 53 | { 16, 16, 16, 16, 17, 18, 21, 24, 16, 16, 16, 16, 17, 19, 22, 25, | |
| 54 | 16, 16, 17, 18, 20, 22, 25, 29, 16, 16, 18, 21, 24, 27, 31, 36, | |
| 55 | 17, 17, 20, 24, 30, 35, 41, 47, 18, 19, 22, 27, 35, 44, 54, 65, | |
| 56 | 21, 22, 25, 31, 41, 54, 70, 88, 24, 25, 29, 36, 47, 65, 88, 115 }; | |
| 57 | const uint8_t CODECHAL_DECODE_HEVC_Default_8x8_Inter[64] = | |
| 58 | { 16, 16, 16, 16, 17, 18, 20, 24, 16, 16, 16, 17, 18, 20, 24, 25, | |
| 59 | 16, 16, 17, 18, 20, 24, 25, 28, 16, 17, 18, 20, 24, 25, 28, 33, | |
| 60 | 17, 18, 20, 24, 25, 28, 33, 41, 18, 20, 24, 25, 28, 33, 41, 54, | |
| 61 | 20, 24, 25, 28, 33, 41, 54, 71, 24, 25, 28, 33, 41, 54, 71, 91 }; | |
| 62 | ||
| 63 | /*! \brief Picture-level parameters of a compressed picture for HEVC decoding. | |
| 64 | * | |
| 65 | * Note 1: Application only pass in the first num_tile_columns_minus1 tile column widths and first num_tile_rows_minus1 tile row heights. The last width and height need to be calculated by driver from the picture dimension. Values used for data type alignement. Their values should be set to 0, and can be ignored by decoder. | |
| 66 | * Note 2: HEVC host decoder should discard any NAL units with nal_unit_type in the range of [10 – 15, 22 – 63]. | |
| 67 | * Note 3: When tiles_enabled_flag equals 1 and uniform_spacing_flag takes value 1, driver may ignore the values passed in column_width_minus1[] and raw_height_minus1[]. Instead driver should generate and populate these tile dimension values based on picture resolution and num_tile_columns_minus1, num_tile_rows_minus1. It can be referred to formula (6-3) and (6-4) in HEVC spec. | |
| 68 | */ | |
| 69 | typedef struct _CODEC_HEVC_PIC_PARAMS | |
| 70 | { | |
| 71 | /*! \brief Width of decoded pictures in units of minimum luma coding block size. | |
| 72 | * | |
| 73 | * The decoded picture width in units of luma samples equals (PicWidthInMinCbsY) * (1 << (log2_min_coding_block_size_minus3 + 3)). | |
| 74 | */ | |
| 75 | uint16_t PicWidthInMinCbsY; | |
| 76 | /*! \brief Height of decoded pictures in units of minimum luma coding block size. | |
| 77 | * | |
| 78 | * The decoded picture height in units of luma samples equals (PicHeightInMinCbsY) * (1 << (log2_min_coding_block_size_minus3 + 3)). | |
| 79 | */ | |
| 80 | uint16_t PicHeightInMinCbsY; | |
| 81 | ||
| 82 | union | |
| 83 | { | |
| 84 | struct | |
| 85 | { | |
| 86 | uint16_t chroma_format_idc : 2; //!< Same as HEVC syntax element | |
| 87 | uint16_t separate_colour_plane_flag : 1; //!< Same as HEVC syntax element | |
| 88 | uint16_t bit_depth_luma_minus8 : 3; //!< Same as HEVC syntax element | |
| 89 | uint16_t bit_depth_chroma_minus8 : 3; //!< Same as HEVC syntax element | |
| 90 | uint16_t log2_max_pic_order_cnt_lsb_minus4 : 4; //!< Same as HEVC syntax element | |
| 91 | /*! \brief Indicates that no picture reordering is used in the coded video sequence. | |
| 92 | * | |
| 93 | * If equal to 1, the maximum allowed number of pictures preceding any picture in decoding order and succeeding that picture in output order is equal to 0. When NoPicReorderingFlag equal to 0, picture reordering may be used in the coded video sequence. This flag does not affect the decoding process. | |
| 94 | * Note: NoPicReorderingFlag may be set to 1 by the host software decoder when sps_max_num_reorder_pics is equal to 0. However, there is no requirement that NoPicReorderingFlag must be derived from sps_max_num_reorder_pics. | |
| 95 | */ | |
| 96 | uint16_t NoPicReorderingFlag : 1; | |
| 97 | /*! \brief Indicates that B slices are not used in the coded video sequence. | |
| 98 | * | |
| 99 | * This flag does not affect the decoding process. | |
| 100 | * Note: This flag does not correspond to any indication provided in the HEVC bitstream itself. Thus, a host software decoder would need some external information (e.g. as determined at the application level) to be able to set this flag to 1. In the absence of any such available indication, the host software decoder must set this flag to 0. | |
| 101 | */ | |
| 102 | uint16_t NoBiPredFlag : 1; | |
| 103 | uint16_t ReservedBits1 : 1; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 104 | }; | |
| 105 | ||
| 106 | uint16_t wFormatAndSequenceInfoFlags; | |
| 107 | }; | |
| 108 | ||
| 109 | /*! \brief Uncompressed destination surface of the frame for the current decoded picture. | |
| 110 | * | |
| 111 | * The long_term_ref_flag has no meaning. The valid value range for Curr.FrameIdx is [0..126]. Value 127 or 0x7F can be treated as an invalid surface index. | |
| 112 | */ | |
| 113 | CODEC_PICTURE CurrPic; | |
| 114 | ||
| 115 | /*! \brief Number of reference frames in the DPB buffer. | |
| 116 | * | |
| 117 | * Host decoder should set this value to be sps_max_dec_pic_buffering_minus1 of the temporal layer where the current decoding frame is of. The value should be between 0 and 15, inclusive. | |
| 118 | */ | |
| 119 | uint8_t sps_max_dec_pic_buffering_minus1; | |
| 120 | uint8_t log2_min_luma_coding_block_size_minus3; //!< Same as HEVC syntax element | |
| 121 | uint8_t log2_diff_max_min_luma_coding_block_size; //!< Same as HEVC syntax element | |
| 122 | uint8_t log2_min_transform_block_size_minus2; //!< Same as HEVC syntax element | |
| 123 | uint8_t log2_diff_max_min_transform_block_size; //!< Same as HEVC syntax element | |
| 124 | uint8_t max_transform_hierarchy_depth_inter; //!< Same as HEVC syntax element | |
| 125 | uint8_t max_transform_hierarchy_depth_intra; //!< Same as HEVC syntax element | |
| 126 | uint8_t num_short_term_ref_pic_sets; //!< Same as HEVC syntax element | |
| 127 | uint8_t num_long_term_ref_pic_sps; //!< Same as HEVC syntax element | |
| 128 | /*! \brief Same as HEVC syntax element. | |
| 129 | * | |
| 130 | * When long slice control data format is taken, hardware decoder should take values from num_ref_idx_l0_active_minus1 and num_ref_idx_l1_active_minus1 from slice control data structure. | |
| 131 | */ | |
| 132 | uint8_t num_ref_idx_l0_default_active_minus1; | |
| 133 | /*! \brief Same as HEVC syntax element. | |
| 134 | * | |
| 135 | * When long slice control data format is taken, hardware decoder should take values from num_ref_idx_l0_active_minus1 and num_ref_idx_l1_active_minus1 from slice control data structure. | |
| 136 | */ | |
| 137 | uint8_t num_ref_idx_l1_default_active_minus1; | |
| 138 | char init_qp_minus26; //!< Same as HEVC syntax element | |
| 139 | /*! \brief Decoder may ignore this value. | |
| 140 | * | |
| 141 | * This is an redundant parameter which serves as same purpose as wNumBitsForShortTermRPSInSlice. | |
| 142 | */ | |
| 143 | uint8_t ucNumDeltaPocsOfRefRpsIdx; | |
| 144 | /*! \brief Bit count in the bit stream for parsing short_term_ref_pic_set in slice segment header. | |
| 145 | * | |
| 146 | * If short_term_ref_pic_set_sps_flag takes value 1, wNumBitsForShortTermRPSInSlice should be 0. The bit count value is calculated when emulation prevention bytes are removed from raw elementary bit stream. | |
| 147 | */ | |
| 148 | uint16_t wNumBitsForShortTermRPSInSlice; | |
| 149 | uint16_t ReservedBits2; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 150 | ||
| 151 | union | |
| 152 | { | |
| 153 | struct | |
| 154 | { | |
| 155 | uint32_t scaling_list_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 156 | uint32_t amp_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 157 | uint32_t sample_adaptive_offset_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 158 | uint32_t pcm_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 159 | uint32_t pcm_sample_bit_depth_luma_minus1 : 4; //!< Same as HEVC syntax element | |
| 160 | uint32_t pcm_sample_bit_depth_chroma_minus1 : 4; //!< Same as HEVC syntax element | |
| 161 | uint32_t log2_min_pcm_luma_coding_block_size_minus3 : 2; //!< Same as HEVC syntax element | |
| 162 | uint32_t log2_diff_max_min_pcm_luma_coding_block_size : 2; //!< Same as HEVC syntax element | |
| 163 | uint32_t pcm_loop_filter_disabled_flag : 1; //!< Same as HEVC syntax element | |
| 164 | uint32_t long_term_ref_pics_present_flag : 1; //!< Same as HEVC syntax element | |
| 165 | uint32_t sps_temporal_mvp_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 166 | uint32_t strong_intra_smoothing_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 167 | uint32_t dependent_slice_segments_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 168 | uint32_t output_flag_present_flag : 1; //!< Same as HEVC syntax element | |
| 169 | uint32_t num_extra_slice_header_bits : 3; //!< Same as HEVC syntax element | |
| 170 | uint32_t sign_data_hiding_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 171 | uint32_t cabac_init_present_flag : 1; //!< Same as HEVC syntax element | |
| 172 | uint32_t ReservedBits3 : 5; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 173 | }; | |
| 174 | ||
| 175 | uint32_t dwCodingParamToolFlags; | |
| 176 | }; | |
| 177 | ||
| 178 | union | |
| 179 | { | |
| 180 | struct | |
| 181 | { | |
| 182 | uint32_t constrained_intra_pred_flag : 1; //!< Same as HEVC syntax element | |
| 183 | uint32_t transform_skip_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 184 | uint32_t cu_qp_delta_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 185 | uint32_t pps_slice_chroma_qp_offsets_present_flag : 1; //!< Same as HEVC syntax element | |
| 186 | uint32_t weighted_pred_flag : 1; //!< Same as HEVC syntax element | |
| 187 | uint32_t weighted_bipred_flag : 1; //!< Same as HEVC syntax element | |
| 188 | uint32_t transquant_bypass_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 189 | uint32_t tiles_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 190 | uint32_t entropy_coding_sync_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 191 | uint32_t uniform_spacing_flag : 1; //!< Same as HEVC syntax element | |
| 192 | uint32_t loop_filter_across_tiles_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 193 | uint32_t pps_loop_filter_across_slices_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 194 | uint32_t deblocking_filter_override_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 195 | uint32_t pps_deblocking_filter_disabled_flag : 1; //!< Same as HEVC syntax element | |
| 196 | /*! \brief Same as HEVC syntax element. | |
| 197 | * | |
| 198 | * Host decoder should set the value properly based on syntax element restricted_ref_pic_lists_flag. If restricted_ref_pic_lists_flag equals 0, lists_modification_present_flag should be set to 1. | |
| 199 | */ | |
| 200 | uint32_t lists_modification_present_flag : 1; | |
| 201 | uint32_t slice_segment_header_extension_present_flag : 1; //!< Same as HEVC syntax element | |
| 202 | /*! \brief Indicates whether the current picture is an IRAP picture. | |
| 203 | * | |
| 204 | * This flag shall be equal to 1 when the current picture is an IRAP picture and shall be equal to 0 when the current picture is not an IRAP picture. | |
| 205 | */ | |
| 206 | uint32_t IrapPicFlag : 1; | |
| 207 | /*! \brief Indicates whether the current picture is an IDR picture. | |
| 208 | * | |
| 209 | * This flag shall be equal to 1 when the current picture is an IDR picture and shall be equal to 0 when the current picture is not an IDR picture. | |
| 210 | */ | |
| 211 | uint32_t IdrPicFlag : 1; | |
| 212 | /*! \brief Takes value 1 when all the slices are intra slices, 0 otherwise. | |
| 213 | */ | |
| 214 | uint32_t IntraPicFlag : 1; | |
| 215 | /*! \brief CRC values are requested if set to 1. | |
| 216 | */ | |
| 217 | uint32_t RequestCRC : 1; | |
| 218 | /*! \brief Histogram array is requested if set to 1. | |
| 219 | * | |
| 220 | * If set, SFC should be enabled to generate the histogram array per channel. If other operations by SFC are required such as scaling, the histogram is generated against the final pixel buffer after the operation is performed. | |
| 221 | */ | |
| 222 | uint32_t RequestHistogram : 1; | |
| 223 | uint32_t ReservedBits4 : 11; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 224 | }; | |
| 225 | ||
| 226 | uint32_t dwCodingSettingPicturePropertyFlags; | |
| 227 | }; | |
| 228 | ||
| 229 | char pps_cb_qp_offset; //!< Same as HEVC syntax element | |
| 230 | char pps_cr_qp_offset; //!< Same as HEVC syntax element | |
| 231 | uint8_t num_tile_columns_minus1; //!< Same as HEVC syntax element | |
| 232 | uint8_t num_tile_rows_minus1; //!< Same as HEVC syntax element | |
| 233 | uint16_t column_width_minus1[19]; //!< Same as HEVC syntax element | |
| 234 | uint16_t row_height_minus1[21]; //!< Same as HEVC syntax element | |
| 235 | uint8_t diff_cu_qp_delta_depth; //!< Same as HEVC syntax element | |
| 236 | char pps_beta_offset_div2; //!< Same as HEVC syntax element | |
| 237 | char pps_tc_offset_div2; //!< Same as HEVC syntax element | |
| 238 | uint8_t log2_parallel_merge_level_minus2; //!< Same as HEVC syntax element | |
| 239 | ||
| 240 | /*! \brief Picture order count value for the current picture. | |
| 241 | * | |
| 242 | * Value range is -2^31 to 2^31-1, inclusive. | |
| 243 | */ | |
| 244 | int32_t CurrPicOrderCntVal; | |
| 245 | /*! \brief FrameIdx for each entry specifies the surface index for all pictures that are or will be referred to by the current or future pictures. | |
| 246 | * | |
| 247 | * The valid entries are indexed from 0 to 126, inclusive. The PicFlags of non-valid entries (including the picture of the entry which is not referred by current picture or future pictures) should take value PICTURE_INVALID. A PicFlags setting of PICTURE_LONG_TERM_REFERENCE indicates if the picture is a long term reference or not. | |
| 248 | * NOTE: for interlace (field) pictures, the FrameIdx field of two RefFrameList entries may have same value and point to same reference surface. And in this case, application should allocate buffer size with double picture height to hold the whole picture. | |
| 249 | */ | |
| 250 | CODEC_PICTURE RefFrameList[15]; | |
| 251 | /*! \brief Picture order count value for each of the reference pictures in the DPB buffer surface, corresponding to the entries of RefFrameList[15]. | |
| 252 | */ | |
| 253 | int32_t PicOrderCntValList[15]; | |
| 254 | /*! \brief Contain the indices to the RefFrameList[] used in inter predection. | |
| 255 | * | |
| 256 | * The indices to the RefFrameList[] indicate all the reference pictures that may be used in inter prediction of the current picture and that may be used in inter prediction of one or more of the pictures following the current picture in decoding order. | |
| 257 | * When an entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] is not valid, it shall be set to 0xff. Invalid entries shall not be present between valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[]. Valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall have values in the range of 0 to 7, inclusive, and each corresponding entry in RefFrameList[] referred to by a valid entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall not have PicFlags equal to PICTURE_INVALID. Any entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] that is not equal to 0xFF shall not be equal to the value of any other entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] or RefPicSetLtCurr[]. | |
| 258 | */ | |
| 259 | uint8_t RefPicSetStCurrBefore[8]; | |
| 260 | /*! \brief Contain the indices to the RefFrameList[] used in inter predection. | |
| 261 | * | |
| 262 | * The indices to the RefFrameList[] indicate all the reference pictures that may be used in inter prediction of the current picture and that may be used in inter prediction of one or more of the pictures following the current picture in decoding order. | |
| 263 | * When an entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] is not valid, it shall be set to 0xff. Invalid entries shall not be present between valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[]. Valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall have values in the range of 0 to 7, inclusive, and each corresponding entry in RefFrameList[] referred to by a valid entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall not have PicFlags equal to PICTURE_INVALID. Any entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] that is not equal to 0xFF shall not be equal to the value of any other entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] or RefPicSetLtCurr[]. | |
| 264 | */ | |
| 265 | uint8_t RefPicSetStCurrAfter[8]; | |
| 266 | /*! \brief Contain the indices to the RefFrameList[] used in inter predection. | |
| 267 | * | |
| 268 | * The indices to the RefFrameList[] indicate all the reference pictures that may be used in inter prediction of the current picture and that may be used in inter prediction of one or more of the pictures following the current picture in decoding order. | |
| 269 | * When an entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] is not valid, it shall be set to 0xff. Invalid entries shall not be present between valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[]. Valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall have values in the range of 0 to 7, inclusive, and each corresponding entry in RefFrameList[] referred to by a valid entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall not have PicFlags equal to PICTURE_INVALID. Any entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] that is not equal to 0xFF shall not be equal to the value of any other entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] or RefPicSetLtCurr[]. | |
| 270 | */ | |
| 271 | uint8_t RefPicSetLtCurr[8]; | |
| 272 | /*! \brief Is a 16 entry array indicating whether or not a picture is a field picture. | |
| 273 | * | |
| 274 | * Each bit of the low 15 bits indicats if the associated picture in DPB is a field picture or not. Specifically, if ((RefFieldPicFlag >> i) & 0x01) > 0, then the referencepicture specified by RefFrameList[i] is a field picture. Otherwise, it is frame picture. For field picture, coresponding bit of RefBottomFieldFlag indicates the field polarity. The MSB, (RefFieldPicFlag >> 15) & 0x01, indicates the field or frame status of current decoded picture, CurrPic. | |
| 275 | */ | |
| 276 | uint16_t RefFieldPicFlag; | |
| 277 | /*! \brief Is a 16 entry array indicating the polarity of a picture. | |
| 278 | * | |
| 279 | * Each bit of the low 15 bits indicats the polarity of the associated reference field picture. If ((RefBottomFieldFlag >> i) & 0x01) > 0, then the reference picture takes odd lines in the surface specified by RefFrameList[i]. And ((RefBottomFieldFlag >> i) & 0x01) = 0 indicates the reference picture takes even lines. The MSB, ((RefBottomFieldFlag >> i) & 0x01), indicates the polarity of the current decoded picture, CurrPic. | |
| 280 | */ | |
| 281 | uint16_t RefBottomFieldFlag; | |
| 282 | /*! \brief Arbitrary number set by the host decoder to use as a tag in the status report feedback data. | |
| 283 | * | |
| 284 | * The value should not equal 0, and should be different in each call to Execute. | |
| 285 | */ | |
| 286 | uint32_t StatusReportFeedbackNumber; | |
| 287 | uint32_t dwLastSliceEndPos; | |
| 288 | ||
| 289 | uint16_t TotalNumEntryPointOffsets; //!< Total entrypoint offset in subset buffer | |
| 290 | } CODEC_HEVC_PIC_PARAMS, *PCODEC_HEVC_PIC_PARAMS; | |
| 291 | ||
| 292 | /*! \brief Slice-level parameters of a compressed picture for HEVC decoding. | |
| 293 | * | |
| 294 | * The slice control buffer is accompanied by a raw bitstream data buffer. The total quantity of data in the bitstream buffer (and the amount of data reported by the host decoder) shall be an integer multiple of 128 bytes. | |
| 295 | */ | |
| 296 | typedef struct _CODEC_HEVC_SLICE_PARAMS | |
| 297 | { | |
| 298 | /*! \brief Number of bytes in the bitstream data buffer that are associated with this slice control data structure. | |
| 299 | * | |
| 300 | * Starting with the byte at the offset given in slice_data_offset. The bitstream data buffer shall not contain additional byte stream NAL units in the bytes following BSNALunitDataLocation up to the location slice_data_offset + slice_data_size. If slice_data_offset + slice_data_size exceeds the boundary of current bitstream data buffer, the excess slice bytes should continue from the first byte of next bitstream data buffer. | |
| 301 | */ | |
| 302 | uint32_t slice_data_size; | |
| 303 | /*! \brief This member locates the NAL unit with nal_unit_type equal to 1 .. 8 for the current slice. | |
| 304 | * | |
| 305 | * At least one bit stream data buffer should be present which is associated with the slice control data buffer. If necessary, multiple bit stream data buffers are allowed, but not suggested. The size of the data in the bitstream data buffer (and the amount of data reported by the host decoder) shall be an integer multiple of 128 bytes. When the end of the slice data is not an even multiple of 128 bytes, the decoder should pad the end of the buffer with zeroes. When more than one bitstream data buffers are present, these data buffers should be in sequential order. They should be treated as if concatenated linearly with no space in between. The value of slice_data_offset is the byte offset, from the start of the first bitstream data buffer, of the first byte of the start code prefix in the byte stream NAL unit that contains the NAL unit with nal_unit_type equal to 1 .. 8. The current slice is the slice associated with this slice control data structure. The bitstream data buffer shall not contain NAL units with values of nal_unit_type outside the range [1 .. 8]. However, the accelerator shall allow any such NAL units to be present and should ignore their content if present. | |
| 306 | * Note: The bitstream data buffer shall contain the full NAL unit byte stream, either encrpted or clear. This means that the buffer will contain emulation_prevention_three_byte syntax elements where those elements are required to be present in a NAL unit, as defined in the HEVC specification. The bitstream data buffer may or may not contrain leading_zero_8bits, zero_byte, and trailing_zero_8bits syntax elements. If present, the accelerator shall ignore these elements. | |
| 307 | */ | |
| 308 | uint32_t slice_data_offset; | |
| 309 | ||
| 310 | // Long format specific | |
| 311 | uint16_t NumEmuPrevnBytesInSliceHdr; //!< Number of emulation prevention bytes in slice head; ByteOffsetToSliceData doesn't include these bytes. | |
| 312 | /*! \brief Byte offset to the location of the first byte of slice_data() data structure for the current slice in the bitstream data buffer. | |
| 313 | * | |
| 314 | * This byte offset is the offset within the RBSP date for the slice, relative to the starting position of the slice_header() in the RBSP. That is, it represents a byte offset after the removal of any emulation_prevention_three_byte syntax elements that precedes the start of the slice_data() in the NAL unit. | |
| 315 | */ | |
| 316 | uint32_t ByteOffsetToSliceData; | |
| 317 | /*! \brief Same as HEVC syntax element. | |
| 318 | * | |
| 319 | * For first slice in the picture, slice_segment_address shall be set to 0. | |
| 320 | */ | |
| 321 | uint32_t slice_segment_address; | |
| 322 | /*! \brief Specifies the surfaces of reference pictures | |
| 323 | * | |
| 324 | * The value of FrameIdx specifies the index of RefFrameList structure. And valid value range is [0..14, 0x7F]. Invalid entries are indicated by setting PicFlags to PICTURE_INVALID and the PicFlags value of PICTURE_LONG_TERM_REFERENCE has no meaning. | |
| 325 | * RefPicIdx[0][] corresponds to reference list 0. | |
| 326 | * RefPicIdx[1][] corresponds to reference list 1. | |
| 327 | * Each list may contain duplicated reference picture indexes. | |
| 328 | */ | |
| 329 | CODEC_PICTURE RefPicList[2][15]; | |
| 330 | union | |
| 331 | { | |
| 332 | uint32_t value; | |
| 333 | struct | |
| 334 | { | |
| 335 | uint32_t LastSliceOfPic : 1; //!< Specifies if current slice is the last slice of picture. | |
| 336 | uint32_t dependent_slice_segment_flag : 1; //!< Same as HEVC syntax element | |
| 337 | uint32_t slice_type : 2; //!< Same as HEVC syntax element | |
| 338 | uint32_t color_plane_id : 2; //!< Same as HEVC syntax element | |
| 339 | uint32_t slice_sao_luma_flag : 1; //!< Same as HEVC syntax element | |
| 340 | uint32_t slice_sao_chroma_flag : 1; //!< Same as HEVC syntax element | |
| 341 | uint32_t mvd_l1_zero_flag : 1; //!< Same as HEVC syntax element | |
| 342 | uint32_t cabac_init_flag : 1; //!< Same as HEVC syntax element | |
| 343 | uint32_t slice_temporal_mvp_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 344 | uint32_t slice_deblocking_filter_disabled_flag : 1; //!< Same as HEVC syntax element | |
| 345 | uint32_t collocated_from_l0_flag : 1; //!< Same as HEVC syntax element | |
| 346 | uint32_t slice_loop_filter_across_slices_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 347 | uint32_t reserved : 18; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 348 | }fields; | |
| 349 | }LongSliceFlags; | |
| 350 | ||
| 351 | /*! \brief Index to the RefPicList[0][] or RefPicList[1][]. | |
| 352 | * | |
| 353 | * It should be derived from HEVC syntax element collocated_ref_idx. When the HEVC syntax element slice_temporal_mvp_enabled_flag takes value 0, collocated_ref_idx should take value 0xFF. Valid value range is [0.. num_ref_idx_l0_active_minus1] or [0..num_ref_idx_l1_active_minus1] depending on collocated_from_l0_flag. If collocated_ref_idx takes a valid value, the corresponding entry of RefFrameList[] must contain a valid surface index. | |
| 354 | */ | |
| 355 | uint8_t collocated_ref_idx; | |
| 356 | /*! \brief Same as HEVC syntax element. | |
| 357 | * | |
| 358 | * If num_ref_idx_active_override_flag == 0, host decoder shall set their values with num_ref_idx_l0_default_minus1, and num_ref_idx_l1_default_minus1. | |
| 359 | */ | |
| 360 | uint8_t num_ref_idx_l0_active_minus1; | |
| 361 | /*! \brief Same as HEVC syntax element. | |
| 362 | * | |
| 363 | * If num_ref_idx_active_override_flag == 0, host decoder shall set their values with num_ref_idx_l0_default_minus1, and num_ref_idx_l1_default_minus1. | |
| 364 | */ | |
| 365 | uint8_t num_ref_idx_l1_active_minus1; | |
| 366 | char slice_qp_delta; //!< Same as HEVC syntax element | |
| 367 | char slice_cb_qp_offset; //!< Same as HEVC syntax element | |
| 368 | char slice_cr_qp_offset; //!< Same as HEVC syntax element | |
| 369 | char slice_beta_offset_div2; //!< Same as HEVC syntax element | |
| 370 | char slice_tc_offset_div2; //!< Same as HEVC syntax element | |
| 371 | /*! \brief Same as HEVC syntax element. | |
| 372 | * | |
| 373 | * Specifies the base 2 logarithm of the denominator for all luma weighting factors. Value range: 0 to 7, inclusive. | |
| 374 | */ | |
| 375 | uint8_t luma_log2_weight_denom; | |
| 376 | /*! \brief Same as HEVC syntax element. | |
| 377 | * | |
| 378 | * Specifies the base 2 logarithm of the denominator for all chroma weighting factors. Value range of luma_log2_weight_denom + delta_chroma_log2_weight_denom: 0 to 7, inclusive. | |
| 379 | */ | |
| 380 | uint8_t delta_chroma_log2_weight_denom; | |
| 381 | ||
| 382 | /*! \brief Same as HEVC syntax element. | |
| 383 | * | |
| 384 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 385 | */ | |
| 386 | char delta_luma_weight_l0[15]; | |
| 387 | /*! \brief Same as HEVC syntax element. | |
| 388 | * | |
| 389 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 390 | */ | |
| 391 | char luma_offset_l0[15]; | |
| 392 | /*! \brief Same as HEVC syntax element. | |
| 393 | * | |
| 394 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 395 | */ | |
| 396 | char delta_chroma_weight_l0[15][2]; | |
| 397 | /*! \brief Same as HEVC syntax element. | |
| 398 | * | |
| 399 | * If the corresponding chroma weight flags are 0, the value should also be set to 0. Please note that for range extension profiles other than main, main10, and their related intra or still image profiles, the data types are defined differrently. | |
| 400 | */ | |
| 401 | char ChromaOffsetL0[15][2]; | |
| 402 | ||
| 403 | /*! \brief Same as HEVC syntax element. | |
| 404 | * | |
| 405 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 406 | */ | |
| 407 | char delta_luma_weight_l1[15]; | |
| 408 | /*! \brief Same as HEVC syntax element. | |
| 409 | * | |
| 410 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 411 | */ | |
| 412 | char luma_offset_l1[15]; | |
| 413 | /*! \brief Same as HEVC syntax element. | |
| 414 | * | |
| 415 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 416 | */ | |
| 417 | char delta_chroma_weight_l1[15][2]; | |
| 418 | /*! \brief Same as HEVC syntax element. | |
| 419 | * | |
| 420 | * If the corresponding chroma weight flags are 0, the value should also be set to 0. Please note that for range extension profiles other than main, main10, and their related intra or still image profiles, the data types are defined differrently. | |
| 421 | */ | |
| 422 | char ChromaOffsetL1[15][2]; | |
| 423 | ||
| 424 | /*! \brief Same as HEVC syntax element. | |
| 425 | * | |
| 426 | * HEVC spec variable MaxNumMergeCand can be derived by 5 - five_minus_max_num_merge_cand, and specifies the maximum number of merging MVP candidates supported in the slice. Value range: 0 to 4 inclusive. | |
| 427 | */ | |
| 428 | uint8_t five_minus_max_num_merge_cand; | |
| 429 | uint16_t num_entry_point_offsets; // [0..540] | |
| 430 | uint16_t EntryOffsetToSubsetArray; // [0..540] | |
| 431 | } CODEC_HEVC_SLICE_PARAMS, *PCODEC_HEVC_SLICE_PARAMS; | |
| 432 | ||
| 433 | ||
| 434 | /*! \brief Additional picture-level parameters of a compressed picture for HEVC decoding. | |
| 435 | * | |
| 436 | * Defined for profiles main12, main4:2:2 10, main4:2:2 12, main4:4:4, main4:4:4 10, main4:4:4 12 and their related intra and still picture profiles. | |
| 437 | */ | |
| 438 | typedef struct _CODEC_HEVC_EXT_PIC_PARAMS | |
| 439 | { | |
| 440 | union | |
| 441 | { | |
| 442 | struct | |
| 443 | { | |
| 444 | uint32_t transform_skip_rotation_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 445 | uint32_t transform_skip_context_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 446 | uint32_t implicit_rdpcm_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 447 | uint32_t explicit_rdpcm_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 448 | uint32_t extended_precision_processing_flag : 1; //!< Same as HEVC syntax element | |
| 449 | uint32_t intra_smoothing_disabled_flag : 1; //!< Same as HEVC syntax element | |
| 450 | uint32_t high_precision_offsets_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 451 | uint32_t persistent_rice_adaptation_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 452 | uint32_t cabac_bypass_alignment_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 453 | uint32_t cross_component_prediction_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 454 | uint32_t chroma_qp_offset_list_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 455 | uint32_t BitDepthLuma16 : 1; //!< Same as HEVC syntax element | |
| 456 | uint32_t BitDepthChroma16 : 1; //!< Same as HEVC syntax element | |
| 457 | uint32_t ReservedBits5 : 19; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 458 | } fields; | |
| 459 | uint32_t dwRangeExtensionPropertyFlags; | |
| 460 | } PicRangeExtensionFlags; | |
| 461 | ||
| 462 | uint8_t diff_cu_chroma_qp_offset_depth; //!< Same as HEVC syntax element, [0..3] | |
| 463 | uint8_t chroma_qp_offset_list_len_minus1; //!< Same as HEVC syntax element, [0..5] | |
| 464 | uint8_t log2_sao_offset_scale_luma; //!< Same as HEVC syntax element, [0..6] | |
| 465 | uint8_t log2_sao_offset_scale_chroma; //!< Same as HEVC syntax element, [0..6] | |
| 466 | uint8_t log2_max_transform_skip_block_size_minus2; //!< Same as HEVC syntax element | |
| 467 | char cb_qp_offset_list[6]; //!< Same as HEVC syntax element, [-12..12] | |
| 468 | char cr_qp_offset_list[6]; //!< Same as HEVC syntax element, [-12..12] | |
| 469 | } CODEC_HEVC_EXT_PIC_PARAMS, *PCODEC_HEVC_EXT_PIC_PARAMS; | |
| 470 | ||
| 471 | ||
| 472 | /*! \brief Additional range extention slice-level parameters of a compressed picture for HEVC decoding. | |
| 473 | * | |
| 474 | * HEVC range extension profiles extend the luma and chroma offset values from 8 bits to 16 bits. | |
| 475 | */ | |
| 476 | typedef struct _CODEC_HEVC_EXT_SLICE_PARAMS | |
| 477 | { | |
| 478 | /*! \brief Same as HEVC syntax element. | |
| 479 | * | |
| 480 | * These set of values are the most significant 8-bit part of the corresponding luma_offset_l0[]. Combining with the luma_offset_l0[] will give the final values respectively. The sign for each parameter is determined by the sign of corresponding luma_offset_l0[]. | |
| 481 | */ | |
| 482 | int16_t luma_offset_l0[15]; | |
| 483 | /*! \brief Same as HEVC syntax element. | |
| 484 | * | |
| 485 | * These set of values are the most significant 8-bit part of the corresponding chroma_offset_l0[]. Combining with the chroma_offset_l0[] will give the final values respectively. The sign for each parameter is determined by the sign of corresponding chroma_offset_l0[]. | |
| 486 | */ | |
| 487 | int16_t ChromaOffsetL0[15][2]; | |
| 488 | /*! \brief Same as HEVC syntax element. | |
| 489 | * | |
| 490 | * These set of values are the most significant 8-bit part of the corresponding luma_offset_l1[]. Combining with the luma_offset_l1[] will give the final values respectively. The sign for each parameter is determined by the sign of corresponding luma_offset_l1[]. | |
| 491 | */ | |
| 492 | int16_t luma_offset_l1[15]; | |
| 493 | /*! \brief Same as HEVC syntax element. | |
| 494 | * | |
| 495 | * These set of values are the most significant 8-bit part of the corresponding chroma_offset_l1[]. Combining with the chroma_offset_l1[] will give the final values respectively. The sign for each parameter is determined by the sign of corresponding chroma_offset_l1[]. | |
| 496 | */ | |
| 497 | int16_t ChromaOffsetL1[15][2]; | |
| 498 | ||
| 499 | bool cu_chroma_qp_offset_enabled_flag; //!< Same as HEVC syntax element | |
| 500 | ||
| 501 | // For Screen Content Extension | |
| 502 | char slice_act_y_qp_offset; // [-12..12] | |
| 503 | char slice_act_cb_qp_offset; // [-12..12] | |
| 504 | char slice_act_cr_qp_offset; // [-12..12] | |
| 505 | unsigned char use_integer_mv_flag; | |
| 506 | } CODEC_HEVC_EXT_SLICE_PARAMS, *PCODEC_HEVC_EXT_SLICE_PARAMS; | |
| 507 | ||
| 508 | typedef struct _CODEC_HEVC_SUBSET_PARAMS | |
| 509 | { | |
| 510 | uint32_t entry_point_offset_minus1[440]; | |
| 511 | } CODEC_HEVC_SUBSET_PARAMS, *PCODEC_HEVC_SUBSET_PARAMS; | |
| 512 | #endif // __CODEC_DEF_DECODE_HEVC_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_decode_vc1.h | |
| 23 | //! \brief Defines decode VC1 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to JPEG decode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_DECODE_VC1_H__ | |
| 27 | #define __CODEC_DEF_DECODE_VC1_H__ | |
| 28 | ||
| 29 | // VC1 reference flags | |
| 30 | #define CODECHAL_WMV9_RANGE_ADJUSTMENT 0x00100000 | |
| 31 | #define CODECHAL_VC1_PROGRESSIVE 0x00200000 | |
| 32 | #define CODECHAL_VC1_TOP_FIELD_COMP 0x00010000 | |
| 33 | #define CODECHAL_VC1_TOP_FIELD_COMP_2 0x00020000 | |
| 34 | #define CODECHAL_VC1_BOT_FIELD_COMP 0x00040000 | |
| 35 | #define CODECHAL_VC1_BOT_FIELD_COMP_2 0x00080000 | |
| 36 | #define CODECHAL_VC1_FRAME_COMP (CODECHAL_VC1_TOP_FIELD_COMP | CODECHAL_VC1_BOT_FIELD_COMP) | |
| 37 | #define CODECHAL_VC1_ALL_COMP 0x000F0000 | |
| 38 | ||
| 39 | //! | |
| 40 | //! \enum Vc1FramPictureType | |
| 41 | //! \brief VC1 fram picture Types | |
| 42 | //! | |
| 43 | enum Vc1FramPictureType | |
| 44 | { | |
| 45 | vc1IFrame = 0, | |
| 46 | vc1PFrame, | |
| 47 | vc1BFrame, | |
| 48 | vc1BIFrame, | |
| 49 | vc1SkippedFrame | |
| 50 | }; | |
| 51 | ||
| 52 | //! | |
| 53 | //! \enum Vc1FieldPictureType | |
| 54 | //! \brief VC1 field picture Types | |
| 55 | //! | |
| 56 | enum Vc1FieldPictureType | |
| 57 | { | |
| 58 | vc1IIField = 0, | |
| 59 | vc1IPField, | |
| 60 | vc1PIField, | |
| 61 | vc1PPField, | |
| 62 | vc1BBField, | |
| 63 | vc1BBIField, | |
| 64 | vc1BIBField, | |
| 65 | vc1BIBIField | |
| 66 | }; | |
| 67 | ||
| 68 | //! | |
| 69 | //! \enum Vc1QuantizerType | |
| 70 | //! \brief VC-1 Spec Table 259: Quantizer Specification | |
| 71 | //! | |
| 72 | enum Vc1QuantizerType | |
| 73 | { | |
| 74 | vc1QuantizerImplicit = 0, // specified at frame level | |
| 75 | vc1QuantizerExplicit, // specified at frame level | |
| 76 | vc1QuantizerNonuniform, // used for all frames | |
| 77 | vc1QuantizerUniform // used for all frames | |
| 78 | }; | |
| 79 | ||
| 80 | typedef struct _CODEC_VC1_PIC_PARAMS | |
| 81 | { | |
| 82 | CODEC_PICTURE CurrPic; | |
| 83 | uint16_t DeblockedPicIdx; | |
| 84 | uint16_t ForwardRefIdx; | |
| 85 | uint16_t BackwardRefIdx; | |
| 86 | ||
| 87 | /* sequence layer for AP or meta data for SP and MP */ | |
| 88 | union | |
| 89 | { | |
| 90 | struct | |
| 91 | { | |
| 92 | uint32_t pulldown : 1; /* SEQUENCE_LAYER::PULLDOWN */ | |
| 93 | uint32_t interlace : 1; /* SEQUENCE_LAYER::INTERLACE */ | |
| 94 | uint32_t tfcntrflag : 1; /* SEQUENCE_LAYER::TFCNTRFLAG */ | |
| 95 | uint32_t finterpflag : 1; /* SEQUENCE_LAYER::FINTERPFLAG */ | |
| 96 | uint32_t psf : 1; /* SEQUENCE_LAYER::PSF */ | |
| 97 | uint32_t multires : 1; /* METADATA::MULTIRES */ | |
| 98 | uint32_t overlap : 1; /* METADATA::OVERLAP */ | |
| 99 | uint32_t syncmarker : 1; /* METADATA::SYNCMARKER */ | |
| 100 | uint32_t rangered : 1; /* METADATA::RANGERED */ | |
| 101 | uint32_t max_b_frames : 3; /* METADATA::MAXBFRAMES */ | |
| 102 | uint32_t AdvancedProfileFlag : 1; | |
| 103 | }; | |
| 104 | uint32_t value; | |
| 105 | } sequence_fields; | |
| 106 | ||
| 107 | uint16_t coded_width; /* ENTRY_POINT_LAYER::CODED_WIDTH */ | |
| 108 | uint16_t coded_height; /* ENTRY_POINT_LAYER::CODED_HEIGHT */ | |
| 109 | union | |
| 110 | { | |
| 111 | struct | |
| 112 | { | |
| 113 | uint32_t broken_link : 1; /* ENTRY_POINT_LAYER::BROKEN_LINK */ | |
| 114 | uint32_t closed_entry : 1; /* ENTRY_POINT_LAYER::CLOSED_ENTRY */ | |
| 115 | uint32_t panscan_flag : 1; /* ENTRY_POINT_LAYER::PANSCAN_FLAG */ | |
| 116 | uint32_t loopfilter : 1; /* ENTRY_POINT_LAYER::LOOPFILTER */ | |
| 117 | }; | |
| 118 | uint32_t value; | |
| 119 | } entrypoint_fields; | |
| 120 | uint8_t conditional_overlap_flag; /* ENTRY_POINT_LAYER::CONDOVER */ | |
| 121 | uint8_t fast_uvmc_flag; /* ENTRY_POINT_LAYER::FASTUVMC */ | |
| 122 | union | |
| 123 | { | |
| 124 | struct | |
| 125 | { | |
| 126 | uint32_t luma_flag : 1; /* ENTRY_POINT_LAYER::RANGE_MAPY_FLAG */ | |
| 127 | uint32_t luma : 3; /* ENTRY_POINT_LAYER::RANGE_MAPY */ | |
| 128 | uint32_t chroma_flag : 1; /* ENTRY_POINT_LAYER::RANGE_MAPUV_FLAG */ | |
| 129 | uint32_t chroma : 3; /* ENTRY_POINT_LAYER::RANGE_MAPUV */ | |
| 130 | }; | |
| 131 | uint32_t range_mapping_enabled; | |
| 132 | } range_mapping_fields; | |
| 133 | ||
| 134 | uint8_t UpsamplingFlag; | |
| 135 | uint8_t ScaleFactor; /* derived from BFRACTION*/ | |
| 136 | uint8_t b_picture_fraction; /* PICTURE_LAYER::BFRACTION */ | |
| 137 | uint8_t cbp_table; /* PICTURE_LAYER::CBPTAB/ICBPTAB */ | |
| 138 | uint8_t mb_mode_table; /* PICTURE_LAYER::MBMODETAB */ | |
| 139 | uint8_t range_reduction_frame; /* PICTURE_LAYER::RANGEREDFRM */ | |
| 140 | uint8_t rounding_control; /* PICTURE_LAYER::RNDCTRL */ | |
| 141 | uint8_t post_processing; /* PICTURE_LAYER::POSTPROC */ | |
| 142 | uint8_t picture_resolution_index; /* PICTURE_LAYER::RESPIC */ | |
| 143 | uint16_t luma_scale; /* PICTURE_LAYER::LUMSCALE */ | |
| 144 | uint16_t luma_shift; /* PICTURE_LAYER::LUMSHIFT */ | |
| 145 | union | |
| 146 | { | |
| 147 | struct | |
| 148 | { | |
| 149 | uint32_t picture_type : 3; /* PICTURE_LAYER::PTYPE */ | |
| 150 | uint32_t frame_coding_mode : 3; /* PICTURE_LAYER::FCM */ | |
| 151 | uint32_t top_field_first : 1; /* PICTURE_LAYER::TFF */ | |
| 152 | uint32_t is_first_field : 1; /* set to 1 if it is the first field */ | |
| 153 | uint32_t intensity_compensation : 1; /* PICTURE_LAYER::INTCOMP */ | |
| 154 | }; | |
| 155 | uint32_t value; | |
| 156 | } picture_fields; | |
| 157 | union | |
| 158 | { | |
| 159 | struct | |
| 160 | { | |
| 161 | uint32_t bitplane_present : 1; | |
| 162 | uint32_t mv_type_mb : 1; /* PICTURE::MVTYPEMB */ | |
| 163 | uint32_t direct_mb : 1; /* PICTURE::DIRECTMB */ | |
| 164 | uint32_t skip_mb : 1; /* PICTURE::SKIPMB */ | |
| 165 | uint32_t field_tx : 1; /* PICTURE::FIELDTX */ | |
| 166 | uint32_t forward_mb : 1; /* PICTURE::FORWARDMB */ | |
| 167 | uint32_t ac_pred : 1; /* PICTURE::ACPRED */ | |
| 168 | uint32_t overflags : 1; /* PICTURE::OVERFLAGS */ | |
| 169 | }; | |
| 170 | uint32_t value; | |
| 171 | } raw_coding; | |
| 172 | ||
| 173 | union | |
| 174 | { | |
| 175 | struct | |
| 176 | { | |
| 177 | uint32_t reference_distance_flag : 1; /* PICTURE_LAYER::REFDIST_FLAG */ | |
| 178 | uint32_t reference_distance : 5; /* PICTURE_LAYER::REFDIST */ | |
| 179 | uint32_t BwdReferenceDistance : 5; | |
| 180 | uint32_t num_reference_pictures : 1; /* PICTURE_LAYER::NUMREF */ | |
| 181 | uint32_t reference_field_pic_indicator : 1; /* PICTURE_LAYER::REFFIELD */ | |
| 182 | uint32_t reference_picture_flag : 1; /* set to 1 if it will be used as a reference picture */ | |
| 183 | }; | |
| 184 | uint32_t value; | |
| 185 | } reference_fields; | |
| 186 | union | |
| 187 | { | |
| 188 | struct | |
| 189 | { | |
| 190 | uint32_t MvMode : 4; | |
| 191 | uint32_t UnifiedMvMode : 3; /* Combination of MVMODE and MVMODE1 */ | |
| 192 | uint32_t mv_table : 3; /* PICTURE_LAYER::MVTAB/IMVTAB */ | |
| 193 | uint32_t two_mv_block_pattern_table : 2; /* PICTURE_LAYER::2MVBPTAB */ | |
| 194 | uint32_t four_mv_switch : 1; /* PICTURE_LAYER::4MVSWITCH */ | |
| 195 | uint32_t four_mv_block_pattern_table : 2; /* PICTURE_LAYER::4MVBPTAB */ | |
| 196 | uint32_t extended_mv_flag : 1; /* ENTRY_POINT_LAYER::EXTENDED_MV */ | |
| 197 | uint32_t extended_mv_range : 2; /* PICTURE_LAYER::MVRANGE */ | |
| 198 | uint32_t extended_dmv_flag : 1; /* ENTRY_POINT_LAYER::EXTENDED_DMV */ | |
| 199 | uint32_t extended_dmv_range : 2; /* PICTURE_LAYER::DMVRANGE */ | |
| 200 | uint32_t four_mv_allowed : 1; /* PICTURE_LAYER::4MVSWITCH */ | |
| 201 | }; | |
| 202 | uint32_t value; | |
| 203 | } mv_fields; | |
| 204 | union | |
| 205 | { | |
| 206 | struct | |
| 207 | { | |
| 208 | uint32_t dquant : 2; /* ENTRY_POINT_LAYER::DQUANT */ | |
| 209 | uint32_t quantizer : 2; /* ENTRY_POINT_LAYER::QUANTIZER */ | |
| 210 | uint32_t half_qp : 1; /* PICTURE_LAYER::HALFQP */ | |
| 211 | uint32_t AltPQuantEdgeMask : 4; /* Derived from DQUANT, DQUANTTFRM, DQPROFILE, DDQSBEDGE, DQDBEDGE, DQBILEVEL*/ | |
| 212 | uint32_t AltPQuantConfig : 2; /* Derived from DQUANT, DQUANTTFRM, DQPROFILE, DDQSBEDGE, DQDBEDGE, DQBILEVEL*/ | |
| 213 | uint32_t pic_quantizer_scale : 5; /* PICTURE_LAYER::PQUANT */ | |
| 214 | uint32_t pic_quantizer_type : 1; /* PICTURE_LAYER::PQUANTIZER */ | |
| 215 | uint32_t alt_pic_quantizer : 5; /* VOPDQUANT::ALTPQUANT */ | |
| 216 | }; | |
| 217 | uint32_t value; | |
| 218 | } pic_quantizer_fields; | |
| 219 | union | |
| 220 | { | |
| 221 | struct | |
| 222 | { | |
| 223 | uint32_t variable_sized_transform_flag : 1; /* ENTRY_POINT_LAYER::VSTRANSFORM */ | |
| 224 | uint32_t mb_level_transform_type_flag : 1; /* PICTURE_LAYER::TTMBF */ | |
| 225 | uint32_t frame_level_transform_type : 2; /* PICTURE_LAYER::TTFRM */ | |
| 226 | uint32_t transform_ac_codingset_idx1 : 2; /* PICTURE_LAYER::TRANSACFRM */ | |
| 227 | uint32_t transform_ac_codingset_idx2 : 2; /* PICTURE_LAYER::TRANSACFRM2 */ | |
| 228 | uint32_t intra_transform_dc_table : 1; /* PICTURE_LAYER::TRANSDCTAB */ | |
| 229 | }; | |
| 230 | uint32_t value; | |
| 231 | } transform_fields; | |
| 232 | ||
| 233 | uint32_t StatusReportFeedbackNumber; | |
| 234 | } CODEC_VC1_PIC_PARAMS, *PCODEC_VC1_PIC_PARAMS; | |
| 235 | ||
| 236 | typedef struct _CODEC_VC1_SLICE_PARAMS | |
| 237 | { | |
| 238 | uint32_t slice_data_size; /* number of bytes in the slice data buffer for this slice */ | |
| 239 | uint32_t slice_data_offset; /* the offset to the first byte of slice data */ | |
| 240 | uint32_t macroblock_offset; /* the offset to the first bit of MB from the first byte of slice data */ | |
| 241 | uint32_t slice_vertical_position; | |
| 242 | uint32_t b_picture_fraction; /* BFRACTION */ | |
| 243 | uint32_t number_macroblocks; /* number of macroblocks in the slice */ | |
| 244 | } CODEC_VC1_SLICE_PARAMS, *PCODEC_VC1_SLICE_PARAMS; | |
| 245 | ||
| 246 | typedef struct _CODEC_VC1_MB_PARAMS | |
| 247 | { | |
| 248 | uint16_t mb_address; | |
| 249 | uint8_t mb_skips_following; /* the number of skipped macroblocks to be generated following the current macroblock */ | |
| 250 | uint8_t num_coef[CODEC_NUM_BLOCK_PER_MB]; /* the number of coefficients in the residual difference data buffer for each block i of the macroblock */ | |
| 251 | uint32_t data_offset; /* data offset in the residual data buffer, byte offset (32-bit multiple index) */ | |
| 252 | uint32_t data_length; /* length of the residual data for the macroblock */ | |
| 253 | union | |
| 254 | { | |
| 255 | struct | |
| 256 | { | |
| 257 | uint16_t intra_mb : 1; | |
| 258 | uint16_t motion_forward : 1; | |
| 259 | uint16_t motion_backward : 1; | |
| 260 | uint16_t motion_4mv : 1; | |
| 261 | uint16_t h261_loopfilter : 1; | |
| 262 | uint16_t field_residual : 1; | |
| 263 | uint16_t mb_scan_method : 2; | |
| 264 | uint16_t motion_type : 2; | |
| 265 | uint16_t host_resid_diff : 1; | |
| 266 | uint16_t reserved : 1; | |
| 267 | uint16_t mvert_field_sel_0 : 1; | |
| 268 | uint16_t mvert_field_sel_1 : 1; | |
| 269 | uint16_t mvert_field_sel_2 : 1; | |
| 270 | uint16_t mvert_field_sel_3 : 1; | |
| 271 | }; | |
| 272 | uint16_t value; | |
| 273 | } mb_type; | |
| 274 | union | |
| 275 | { | |
| 276 | struct | |
| 277 | { | |
| 278 | uint16_t block_coded_pattern : 6; | |
| 279 | uint16_t block_luma_intra : 4; | |
| 280 | uint16_t block_chroma_intra : 1; | |
| 281 | uint16_t : 5; | |
| 282 | }; | |
| 283 | uint16_t value; | |
| 284 | } pattern_code; | |
| 285 | union | |
| 286 | { | |
| 287 | struct | |
| 288 | { | |
| 289 | uint16_t mv_x : 16; | |
| 290 | uint16_t mv_y : 16; | |
| 291 | }; | |
| 292 | uint32_t value; | |
| 293 | } motion_vector[4]; | |
| 294 | } CODEC_VC1_MB_PARAMS, *PCODEC_VC1_MB_PARAMS; | |
| 295 | ||
| 296 | #endif // __CODEC_DEF_DECODE_VC1_H__ | |
| 297 |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_decode_vp9.h | |
| 23 | //! \brief Defines decode VP9 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to VP9 decode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_DECODE_VP9_H__ | |
| 27 | #define __CODEC_DEF_DECODE_VP9_H__ | |
| 28 | ||
| 29 | #include "codec_def_common.h" | |
| 30 | #include "codec_def_common_vp9.h" | |
| 31 | ||
| 32 | #define CODEC_VP9_MAX_SEGMENTS 8 | |
| 33 | #define CODECHAL_MAX_CUR_NUM_REF_FRAME_VP9 3 | |
| 34 | #define CODECHAL_DECODE_VP9_MAX_NUM_REF_FRAME 8 | |
| 35 | #define CODECHAL_VP9_NUM_MV_BUFFERS 2 | |
| 36 | #define VP9_CENC_PRIMITIVE_CMD_OFFSET_IN_DW 16 | |
| 37 | ||
| 38 | //! | |
| 39 | //! \enum CODECHAL_DECODE_VP9_SEG_LVL_FEATURES | |
| 40 | //! VP9 decode segment level | |
| 41 | //! | |
| 42 | typedef enum | |
| 43 | { | |
| 44 | CODECHAL_DECODE_VP9_SEG_LVL_ALT_Q = 0, //!< Use alternate Quantizer | |
| 45 | CODECHAL_DECODE_VP9_SEG_LVL_ALT_LF = 1, //!< Use alternate loop filter value | |
| 46 | CODECHAL_DECODE_VP9_SEG_LVL_REF_FRAME = 2, //!< Optional Segment reference frame | |
| 47 | CODECHAL_DECODE_VP9_SEG_LVL_SKIP = 3, //!< Optional Segment (0,0) + skip mode | |
| 48 | CODECHAL_DECODE_VP9_SEG_LVL_MAX = 4 //!< Number of features supported | |
| 49 | } CODECHAL_DECODE_VP9_SEG_LVL_FEATURES; | |
| 50 | ||
| 51 | //! | |
| 52 | //! \enum CODECHAL_DECODE_VP9_MV_REFERENCE_FRAME | |
| 53 | //! VP9 decode mv reference | |
| 54 | //! | |
| 55 | typedef enum | |
| 56 | { | |
| 57 | CODECHAL_DECODE_VP9_NONE = -1, | |
| 58 | CODECHAL_DECODE_VP9_INTRA_FRAME = 0, | |
| 59 | CODECHAL_DECODE_VP9_LAST_FRAME = 1, | |
| 60 | CODECHAL_DECODE_VP9_GOLDEN_FRAME = 2, | |
| 61 | CODECHAL_DECODE_VP9_ALTREF_FRAME = 3, | |
| 62 | CODECHAL_DECODE_VP9_MAX_REF_FRAMES = 4 | |
| 63 | } CODECHAL_DECODE_VP9_MV_REFERENCE_FRAME; | |
| 64 | ||
| 65 | // VP9 Decode Slice Parameter Buffer | |
| 66 | typedef struct _CODEC_VP9_SLICE_PARAMS { | |
| 67 | uint32_t BSNALunitDataLocation; | |
| 68 | uint32_t SliceBytesInBuffer; | |
| 69 | uint16_t wBadSliceChopping; | |
| 70 | } CODEC_VP9_SLICE_PARAMS, *PCODEC_VP9_SLICE_PARAMS; | |
| 71 | ||
| 72 | // VP9 Picture Parameters Buffer | |
| 73 | typedef struct _CODEC_VP9_PIC_PARAMS | |
| 74 | { | |
| 75 | uint16_t FrameHeightMinus1; // [0..65535] | |
| 76 | uint16_t FrameWidthMinus1; // [0..65535] | |
| 77 | ||
| 78 | union | |
| 79 | { | |
| 80 | struct | |
| 81 | { | |
| 82 | uint32_t frame_type : 1; // [0..1] | |
| 83 | uint32_t show_frame : 1; // [0..1] | |
| 84 | uint32_t error_resilient_mode : 1; // [0..1] | |
| 85 | uint32_t intra_only : 1; // [0..1] | |
| 86 | uint32_t LastRefIdx : 3; // [0..7] | |
| 87 | uint32_t LastRefSignBias : 1; // [0..1] | |
| 88 | uint32_t GoldenRefIdx : 3; // [0..7] | |
| 89 | uint32_t GoldenRefSignBias : 1; // [0..1] | |
| 90 | uint32_t AltRefIdx : 3; // [0..7] | |
| 91 | uint32_t AltRefSignBias : 1; // [0..1] | |
| 92 | uint32_t allow_high_precision_mv : 1; // [0..1] | |
| 93 | uint32_t mcomp_filter_type : 3; // [0..7] | |
| 94 | uint32_t frame_parallel_decoding_mode : 1; // [0..1] | |
| 95 | uint32_t segmentation_enabled : 1; // [0..1] | |
| 96 | uint32_t segmentation_temporal_update : 1; // [0..1] | |
| 97 | uint32_t segmentation_update_map : 1; // [0..1] | |
| 98 | uint32_t reset_frame_context : 2; // [0..3] | |
| 99 | uint32_t refresh_frame_context : 1; // [0..1] | |
| 100 | uint32_t frame_context_idx : 2; // [0..3] | |
| 101 | uint32_t LosslessFlag : 1; // [0..1] | |
| 102 | uint32_t ReservedField : 2; // [0] | |
| 103 | } fields; | |
| 104 | uint32_t value; | |
| 105 | } PicFlags; | |
| 106 | ||
| 107 | CODEC_PICTURE RefFrameList[8]; // [0..127, 0xFF] | |
| 108 | CODEC_PICTURE CurrPic; // [0..127] | |
| 109 | uint8_t filter_level; // [0..63] | |
| 110 | uint8_t sharpness_level; // [0..7] | |
| 111 | uint8_t log2_tile_rows; // [0..2] | |
| 112 | uint8_t log2_tile_columns; // [0..5] | |
| 113 | uint8_t UncompressedHeaderLengthInBytes; // [0..255] | |
| 114 | uint16_t FirstPartitionSize; // [0..65535] | |
| 115 | uint8_t SegTreeProbs[7]; | |
| 116 | uint8_t SegPredProbs[3]; | |
| 117 | ||
| 118 | uint32_t BSBytesInBuffer; | |
| 119 | ||
| 120 | uint32_t StatusReportFeedbackNumber; | |
| 121 | ||
| 122 | uint8_t profile; // [0..3] | |
| 123 | uint8_t BitDepthMinus8; // [0, 2, 4] | |
| 124 | uint8_t subsampling_x; // [0..1] | |
| 125 | uint8_t subsampling_y; // [0..1] | |
| 126 | } CODEC_VP9_PIC_PARAMS, *PCODEC_VP9_PIC_PARAMS; | |
| 127 | ||
| 128 | typedef struct _CODEC_VP9_SEGMENT_PARAMS | |
| 129 | { | |
| 130 | CODEC_VP9_SEG_PARAMS SegData[8]; | |
| 131 | } CODEC_VP9_SEGMENT_PARAMS, *PCODEC_VP9_SEGMENT_PARAMS; | |
| 132 | ||
| 133 | #endif |
| 0 | /* | |
| 1 | * Copyright (c) 2018-2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_encode.h | |
| 23 | //! \brief Defines encode types and macros shared by CodecHal and DDI layer | |
| 24 | //! \details Applies to encode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | ||
| 27 | #ifndef __CODEC_DEF_ENCODE_H__ | |
| 28 | #define __CODEC_DEF_ENCODE_H__ | |
| 29 | #include "mos_os.h" | |
| 30 | ||
| 31 | //! | |
| 32 | //! \struct CodechalEncodeSeiData | |
| 33 | //! \brief Indicate the SeiData parameters | |
| 34 | //! | |
| 35 | struct CodechalEncodeSeiData | |
| 36 | { | |
| 37 | bool newSEIData; | |
| 38 | uint32_t dwSEIDataSize; | |
| 39 | uint32_t dwSEIBufSize; | |
| 40 | uint8_t* pSEIBuffer; | |
| 41 | }; | |
| 42 | ||
| 43 | struct MetaDataOffset | |
| 44 | { | |
| 45 | uint32_t dwEncodeErrorFlags = 0; | |
| 46 | uint32_t dwEncodedBitstreamWrittenBytesCount = 0; | |
| 47 | uint32_t dwWrittenSubregionsCount = 0; | |
| 48 | ||
| 49 | uint32_t dwEncodeStats = 0; | |
| 50 | uint32_t dwAverageQP = 0; | |
| 51 | uint32_t dwIntraCodingUnitsCount = 0; | |
| 52 | uint32_t dwInterCodingUnitsCount = 0; | |
| 53 | uint32_t dwSkipCodingUnitsCount = 0; | |
| 54 | uint32_t dwAverageMotionEstimationXDirection = 0; | |
| 55 | uint32_t dwAverageMotionEstimationYDirection = 0; | |
| 56 | ||
| 57 | uint32_t dwbSize = 0; | |
| 58 | uint32_t dwbStartOffset = 0; | |
| 59 | uint32_t dwbHeaderSize = 0; | |
| 60 | ||
| 61 | uint32_t dwMetaDataSize = 0; | |
| 62 | uint32_t dwMetaDataSubRegionSize = 0; | |
| 63 | }; | |
| 64 | ||
| 65 | //! | |
| 66 | //! \struct EncoderParams | |
| 67 | //! \brief Encoder parameters | |
| 68 | //! | |
| 69 | struct EncoderParams | |
| 70 | { | |
| 71 | CODECHAL_FUNCTION ExecCodecFunction; //!< High level codec functionality requested. | |
| 72 | ||
| 73 | PMOS_SURFACE psRawSurface; //!< Raw surface | |
| 74 | PMOS_SURFACE psReconSurface; //!< reconstructed surface | |
| 75 | PMOS_RESOURCE presBitstreamBuffer; //!< Output buffer for bitstream data. | |
| 76 | PMOS_RESOURCE presMetadataBuffer; //!< Output buffer for meta data. | |
| 77 | PMOS_RESOURCE presMbCodeSurface; //!< PAK objects provided by framework. | |
| 78 | PMOS_SURFACE psMbSegmentMapSurface; //!< [VP9] | |
| 79 | /* \brief [AVC & MPEG2] MB QP data provided by framework. | |
| 80 | * | |
| 81 | * When in CQP mode, the framework can provide this surface that contains a single QpY value for each macroblock to be used for encoding. If it is not provided, the frame level QpY(QpY + slice_qp_delta) will be used for all macroblocks. | |
| 82 | */ | |
| 83 | PMOS_SURFACE psMbQpDataSurface; //!< pointer to surface of Mb QP Data | |
| 84 | PCODEC_ENCODE_MB_CONTROL pMbCtrlBuffer; //!< [AVC] MB contrl map provided by framework | |
| 85 | PMOS_SURFACE psMbDisableSkipMapSurface; //!< [AVC] MB disable skip map provided by framework | |
| 86 | PMOS_SURFACE psCoeffSurface; //!< [VP9] | |
| 87 | PMOS_RESOURCE presCoeffProbabilityBuffer; //!< [VP9] Coefficient probabilities provided by framework. | |
| 88 | bool bNewSeq; //!< Indicates the start of a new sequence. | |
| 89 | bool bPicQuant; //!< Indicates whether the scaling list is for SPS (0) or PPS (1). | |
| 90 | bool bNewQmatrixData; //!< Indicates that new QM data was provided by framework. | |
| 91 | CodechalEncodeSeiData *pSeiData; //!< [AVC & HEVC] Information pertaining to pSeiParamBuffer. | |
| 92 | uint32_t dwSEIDataOffset; //!< [AVC & HEVC] Offset to the first SEI message within pSeiParamBuffer. | |
| 93 | uint8_t *pSeiParamBuffer; //!< [AVC & HEVC] Packed SEI messages provided by the framework | |
| 94 | uint32_t dwNumSlices; //!< Number of slice data structures in pSliceParams. | |
| 95 | uint32_t dwAppDataSize; //!< [JPEG] | |
| 96 | uint32_t dwNumHuffBuffers; //!< [JPEG] | |
| 97 | uint32_t dwMbDataBufferSize; //!< Size of the data contained in presMbCodeSurface | |
| 98 | uint32_t dwBitstreamSize; //!< Maximum amount of data to be output to presBitstreamBuffer. | |
| 99 | bool bNewVuiData; //!< [AVC & MPEG2] Indicates that pVuiParams is present and expected to be valid. | |
| 100 | bool bJpegQuantMatrixSent; //!< [JPEG] Indicates whether a quant matrix was sent by the framework. | |
| 101 | PBSBuffer pBSBuffer; //!< Packed header data provided by the framework to be inserted in the bitstream. | |
| 102 | PCODECHAL_NAL_UNIT_PARAMS *ppNALUnitParams; //!< Information about the packed header data in pBSBuffer. | |
| 103 | uint32_t uiNumNalUnits; //!< Number of NAL units in ppNALUnitParams. | |
| 104 | void *pSlcHeaderData; //!< [AVC, HEVC, & MPEG2] Packed slice header data provided by the framework. | |
| 105 | bool bAcceleratorHeaderPackingCaps; //!< [AVC] Indicates whether or not the driver is packing the slice headers. | |
| 106 | uint32_t uiSlcStructCaps; //!< [AVC] Slice capability information, formatted as CODEC_SLICE_STRUCTS | |
| 107 | bool bMADEnabled; //!< MAD is enabled | |
| 108 | bool bMbQpDataEnabled; //!< [AVC & MPEG2] Indicates that psMbQpDataSurface is present. | |
| 109 | bool bMbDisableSkipMapEnabled; //!< [AVC] Indicates that psMbDisableSkipMapSurface is present. | |
| 110 | bool bReportStatisticsEnabled; //!< [HEVC] Indicates whether statistic reporting is enabled, disabled by default. | |
| 111 | bool bQualityImprovementEnable; //!< [HEVC] Indicates whether quality improvement is enabled, disabled by default. | |
| 112 | bool newSeqHeader; //!< [AVC] Flag for new Sequence Header. | |
| 113 | bool newPpsHeader; //!< [AVC] Flag for new PPS Header. | |
| 114 | bool arbitraryNumMbsInSlice; //!< [AVC] Flag to indicate if the sliceMapSurface needs to be programmed or not. | |
| 115 | ||
| 116 | void *pSeqParams; //!< Sequence parameter set structure defined per standard. | |
| 117 | void *pPicParams; //!< Picture parameter set structure defined per standard. | |
| 118 | void *pVuiParams; //!< [AVC & MPEG2] Picture parameter set structure defined per standard. | |
| 119 | void *pSliceParams; //!< Slice data array defined per standard, expect dwNumSlices entries. | |
| 120 | void *pSegmentParams; //!< [VP9] | |
| 121 | void *pIQMatrixBuffer; //!< [AVC, HEVC, & MPEG2] IQ parameter structure defined per standard. | |
| 122 | ||
| 123 | // AVC Specific Parameters | |
| 124 | void *pIQWeightScaleLists; //!< list of IQ Weight scale | |
| 125 | void *pAVCQCParams; //!< AVC QC parameters | |
| 126 | void *pAVCRoundingParams; //!< AVC rounding parameters | |
| 127 | ||
| 128 | void *pQuantData; | |
| 129 | PMOS_RESOURCE presDistortionDataSurface; | |
| 130 | uint32_t uiFrameRate; | |
| 131 | ||
| 132 | bool bSegmentMapProvided; //!< [VP9] | |
| 133 | ||
| 134 | void *pMpeg2UserDataListHead; //!< [MPEG2] | |
| 135 | ||
| 136 | void *pHuffmanTable; //!< [JPEG] | |
| 137 | void *pQuantizationTable; //!< [JPEG] | |
| 138 | void *pApplicationData; //!< [JPEG] | |
| 139 | ||
| 140 | void *pFeiPicParams; //!< [FEI] | |
| 141 | void *pPreEncParams; //!< [FEI] | |
| 142 | ||
| 143 | // HEVC Specific Parameters | |
| 144 | bool bVdencActive; //!< Indicate if vdenc is active | |
| 145 | bool advanced; //!< Indicate if vdenc is active | |
| 146 | ||
| 147 | MOS_SURFACE rawSurface; //!< Raw surface | |
| 148 | MOS_SURFACE reconSurface; //!< reconstructed surface | |
| 149 | MOS_RESOURCE resBitstreamBuffer; //!< Output buffer for bitstream data. | |
| 150 | MOS_SURFACE mbQpSurface; | |
| 151 | MOS_SURFACE disableSkipMapSurface; //!< [AVC] MB disable skip map provided by framework | |
| 152 | HANDLE gpuAppTaskEvent; // MSDK event handling | |
| 153 | //Call back to application. This informs the application all ENC kernel workload is submitted(in case of HEVC VME) | |
| 154 | //such that Application can make use of render engine when encoder is working on PAK. this helps in efficient utilisation of | |
| 155 | //Render engine for improving the performance as the render engine will be idle when encoder is working on PAK. | |
| 156 | void * plastEncKernelSubmissionCompleteCallback; | |
| 157 | ||
| 158 | ||
| 159 | bool bStreamOutEnable; | |
| 160 | PMOS_RESOURCE pStreamOutBuffer; // StreamOut buffer | |
| 161 | bool bCoeffRoundTag; | |
| 162 | uint32_t uiRoundIntra; | |
| 163 | uint32_t uiRoundInter; | |
| 164 | ||
| 165 | PMOS_RESOURCE presMbInlineData; | |
| 166 | PMOS_RESOURCE presMbConstSurface; | |
| 167 | PMOS_RESOURCE presVMEOutSurface; | |
| 168 | uint32_t uiMVoffset; // App provides PAK objects and MV data in the same surface. This is offset to MV Data. | |
| 169 | bool fullHeaderInAppData; //!< [JPEG] | |
| 170 | uint32_t uiOverallNALPayload; | |
| 171 | MetaDataOffset metaDataOffset; | |
| 172 | void * pSliceHeaderParams; //!< [HEVC] | |
| 173 | ||
| 174 | PMOS_RESOURCE m_presPredication = nullptr; //! \brief [Predication] Resource for predication | |
| 175 | uint64_t m_predicationResOffset = 0; //! \brief [Predication] Offset for Predication resource | |
| 176 | bool m_predicationNotEqualZero = false; //! \brief [Predication] Predication mode | |
| 177 | bool m_predicationEnabled = false; //! \brief [Predication] Indicates whether or not Predication is enabled | |
| 178 | PMOS_RESOURCE *m_tempPredicationBuffer = nullptr; //! \brief [Predication] Temp buffer for Predication | |
| 179 | ||
| 180 | bool m_setMarkerEnabled = false; //! \brief [SetMarker] Indicates whether or not SetMarker is enabled | |
| 181 | PMOS_RESOURCE m_presSetMarker = nullptr; //! \brief [SetMarker] Resource for SetMarker | |
| 182 | }; | |
| 183 | ||
| 184 | #endif // !__CODEC_DEF_ENCODE_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_encode_avc.h | |
| 23 | //! \brief Defines encode AVC types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to AVC encode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_ENCODE_AVC_H__ | |
| 27 | #define __CODEC_DEF_ENCODE_AVC_H__ | |
| 28 | ||
| 29 | #include "codec_def_common_avc.h" | |
| 30 | #include "codec_def_common_encode.h" | |
| 31 | #include "codec_def_common.h" | |
| 32 | ||
| 33 | #define CODEC_AVC_NUM_MAX_DIRTY_RECT 4 | |
| 34 | #define CODEC_AVC_NUM_QP 52 | |
| 35 | ||
| 36 | #define CODEC_AVC_NUM_WP_FRAME 8 | |
| 37 | #define CODEC_AVC_MAX_FORWARD_WP_FRAME 6 | |
| 38 | #define CODEC_AVC_MAX_BACKWARD_WP_FRAME 2 | |
| 39 | #define CODEC_AVC_WP_OUTPUT_L0_START 0 | |
| 40 | #define CODEC_AVC_WP_OUTPUT_L1_START 6 | |
| 41 | ||
| 42 | #define ENCODE_VDENC_AVC_MAX_ROI_NUMBER_G9 3 // Max 4 regions including non-ROI - used from DDI | |
| 43 | #define ENCODE_VDENC_AVC_MAX_ROI_NUMBER_ADV 16 // Max 16 regions including non-ROI - used from DDI | |
| 44 | #define ENCODE_VDENC_AVC_MIN_ROI_DELTA_QP_G9 -8 // Min delta QP for VDEnc ROI | |
| 45 | #define ENCODE_VDENC_AVC_MAX_ROI_DELTA_QP_G9 7 // Max delta QP for VDEnc ROI | |
| 46 | ||
| 47 | #define ENCODE_DP_AVC_MAX_ROI_NUMBER 4 | |
| 48 | #define ENCODE_DP_AVC_MAX_ROI_NUM_BRC 8 | |
| 49 | ||
| 50 | #define ENCODE_VDENC_AVC_MAX_ROI_NUMBER 3 | |
| 51 | ||
| 52 | #define ENCODE_AVC_MAX_SLICES_SUPPORTED 256 // Limted to 256 due to memory constraints. | |
| 53 | ||
| 54 | //AVC | |
| 55 | #define CODECHAL_ENCODE_AVC_ROI_WIDTH_SCALE_FACTOR 16 | |
| 56 | #define CODECHAL_ENCODE_AVC_ROI_FRAME_HEIGHT_SCALE_FACTOR 16 | |
| 57 | #define CODECHAL_ENCODE_AVC_ROI_FIELD_HEIGHT_SCALE_FACTOR 32 | |
| 58 | #define CODECHAL_ENCODE_AVC_MAX_ROI_NUMBER 4 | |
| 59 | ||
| 60 | typedef struct _CODECHAL_ENCODE_AVC_ROUNDING_PARAMS | |
| 61 | { | |
| 62 | bool bEnableCustomRoudingIntra; | |
| 63 | bool bEnableCustomRoudingInter; | |
| 64 | uint32_t dwRoundingIntra; | |
| 65 | uint32_t dwRoundingInter; | |
| 66 | } CODECHAL_ENCODE_AVC_ROUNDING_PARAMS, *PCODECHAL_ENCODE_AVC_ROUNDING_PARAMS; | |
| 67 | ||
| 68 | // video quality control parameters | |
| 69 | typedef struct _CODECHAL_ENCODE_AVC_QUALITY_CTRL_PARAMS | |
| 70 | { | |
| 71 | union | |
| 72 | { | |
| 73 | struct | |
| 74 | { | |
| 75 | // Disables skip check for ENC. | |
| 76 | unsigned int skipCheckDisable : 1; | |
| 77 | // Indicates app will override default driver FTQ settings using FTQEnable. | |
| 78 | unsigned int FTQOverride : 1; | |
| 79 | // Enables/disables FTQ. | |
| 80 | unsigned int FTQEnable : 1; | |
| 81 | // Indicates the app will provide the Skip Threshold LUT to use when FTQ is | |
| 82 | // enabled (FTQSkipThresholdLUT), else default driver thresholds will be used. | |
| 83 | unsigned int FTQSkipThresholdLUTInput : 1; | |
| 84 | // Indicates the app will provide the Skip Threshold LUT to use when FTQ is | |
| 85 | // disabled (NonFTQSkipThresholdLUT), else default driver thresholds will be used. | |
| 86 | unsigned int NonFTQSkipThresholdLUTInput : 1; | |
| 87 | // Control to enable the ENC mode decision algorithm to bias to fewer B Direct/Skip types. | |
| 88 | // Applies only to B frames, all other frames will ignore this setting. | |
| 89 | unsigned int directBiasAdjustmentEnable : 1; | |
| 90 | // Enables global motion bias. | |
| 91 | unsigned int globalMotionBiasAdjustmentEnable : 1; | |
| 92 | // MV cost scaling ratio for HME predictors. It is used when | |
| 93 | // globalMotionBiasAdjustmentEnable == 1, else it is ignored. Values are: | |
| 94 | // 0: set MV cost to be 0 for HME predictor. | |
| 95 | // 1: scale MV cost to be ? of the default value for HME predictor. | |
| 96 | // 2: scale MV cost to be ? of the default value for HME predictor. | |
| 97 | // 3: scale MV cost to be 1/8 of the default value for HME predictor. | |
| 98 | unsigned int HMEMVCostScalingFactor : 2; | |
| 99 | //disable HME | |
| 100 | unsigned int HMEDisable : 1; | |
| 101 | //disable Super HME | |
| 102 | unsigned int SuperHMEDisable : 1; | |
| 103 | //disable Ultra HME | |
| 104 | unsigned int UltraHMEDisable : 1; | |
| 105 | // Force RepartitionCheck | |
| 106 | unsigned int ForceRepartitionCheck : 2; | |
| 107 | ||
| 108 | }; | |
| 109 | unsigned int encControls; | |
| 110 | }; | |
| 111 | ||
| 112 | // Maps QP to skip thresholds when FTQ is enabled. Valid range is 0-255. | |
| 113 | unsigned char FTQSkipThresholdLUT[CODEC_AVC_NUM_QP]; | |
| 114 | // Maps QP to skip thresholds when FTQ is disabled. Valid range is 0-65535. | |
| 115 | unsigned short NonFTQSkipThresholdLUT[CODEC_AVC_NUM_QP]; | |
| 116 | // Reserved for future use. | |
| 117 | unsigned int reserved[8]; | |
| 118 | } CODECHAL_ENCODE_AVC_QUALITY_CTRL_PARAMS, *PCODECHAL_ENCODE_AVC_QUALITY_CTRL_PARAMS; | |
| 119 | ||
| 120 | // AVC VUI Parameters | |
| 121 | typedef struct _CODECHAL_ENCODE_AVC_VUI_PARAMS | |
| 122 | { | |
| 123 | uint32_t aspect_ratio_info_present_flag : 1; | |
| 124 | uint32_t overscan_info_present_flag : 1; | |
| 125 | uint32_t overscan_appropriate_flag : 1; | |
| 126 | uint32_t video_signal_type_present_flag : 1; | |
| 127 | uint32_t video_full_range_flag : 1; | |
| 128 | uint32_t colour_description_present_flag : 1; | |
| 129 | uint32_t chroma_loc_info_present_flag : 1; | |
| 130 | uint32_t timing_info_present_flag : 1; | |
| 131 | uint32_t fixed_frame_rate_flag : 1; | |
| 132 | uint32_t nal_hrd_parameters_present_flag : 1; | |
| 133 | uint32_t vcl_hrd_parameters_present_flag : 1; | |
| 134 | uint32_t low_delay_hrd_flag : 1; | |
| 135 | uint32_t pic_struct_present_flag : 1; | |
| 136 | uint32_t bitstream_restriction_flag : 1; | |
| 137 | uint32_t motion_vectors_over_pic_boundaries_flag : 1; | |
| 138 | uint32_t : 17; | |
| 139 | uint16_t sar_width; | |
| 140 | uint16_t sar_height; | |
| 141 | uint8_t aspect_ratio_idc; | |
| 142 | uint8_t video_format; | |
| 143 | uint8_t colour_primaries; | |
| 144 | uint8_t transfer_characteristics; | |
| 145 | uint8_t matrix_coefficients; | |
| 146 | uint8_t chroma_sample_loc_type_top_field; | |
| 147 | uint8_t chroma_sample_loc_type_bottom_field; | |
| 148 | uint8_t max_bytes_per_pic_denom; | |
| 149 | uint8_t max_bits_per_mb_denom; | |
| 150 | uint8_t log2_max_mv_length_horizontal; | |
| 151 | uint8_t log2_max_mv_length_vertical; | |
| 152 | uint8_t num_reorder_frames; | |
| 153 | uint32_t num_units_in_tick; | |
| 154 | uint32_t time_scale; | |
| 155 | uint8_t max_dec_frame_buffering; | |
| 156 | ||
| 157 | //HRD parameters | |
| 158 | uint8_t cpb_cnt_minus1; | |
| 159 | uint8_t bit_rate_scale; | |
| 160 | uint8_t cpb_size_scale; | |
| 161 | uint32_t bit_rate_value_minus1[32]; | |
| 162 | uint32_t cpb_size_value_minus1[32]; | |
| 163 | uint32_t cbr_flag; // bit 0 represent SchedSelIdx 0 and so on | |
| 164 | uint8_t initial_cpb_removal_delay_length_minus1; | |
| 165 | uint8_t cpb_removal_delay_length_minus1; | |
| 166 | uint8_t dpb_output_delay_length_minus1; | |
| 167 | uint8_t time_offset_length; | |
| 168 | } CODECHAL_ENCODE_AVC_VUI_PARAMS, *PCODECHAL_ENCODE_AVC_VUI_PARAMS; | |
| 169 | ||
| 170 | typedef enum | |
| 171 | { | |
| 172 | CODECHAL_ENCODE_AVC_NAL_UT_RESERVED = 0x00, // Unspecified | |
| 173 | CODECHAL_ENCODE_AVC_NAL_UT_SLICE = 0x01, // Coded Slice - slice_layer_no_partioning_rbsp | |
| 174 | CODECHAL_ENCODE_AVC_NAL_UT_DPA = 0x02, // Coded Data partition A - dpa_layer_rbsp | |
| 175 | CODECHAL_ENCODE_AVC_NAL_UT_DPB = 0x03, // Coded Data partition B - dpa_layer_rbsp | |
| 176 | CODECHAL_ENCODE_AVC_NAL_UT_DPC = 0x04, // Coded Data partition C - dpa_layer_rbsp | |
| 177 | CODECHAL_ENCODE_AVC_NAL_UT_IDR_SLICE = 0x05, // Coded Slice of a IDR Picture - slice_layer_no_partioning_rbsp | |
| 178 | CODECHAL_ENCODE_AVC_NAL_UT_SEI = 0x06, // Supplemental Enhancement Information - sei_rbsp | |
| 179 | CODECHAL_ENCODE_AVC_NAL_UT_SPS = 0x07, // Sequence Parameter Set - seq_parameter_set_rbsp | |
| 180 | CODECHAL_ENCODE_AVC_NAL_UT_PPS = 0x08, // Picture Parameter Set - pic_parameter_set_rbsp | |
| 181 | CODECHAL_ENCODE_AVC_NAL_UT_AUD = 0x09, // Access Unit Delimiter - access_unit_delimiter_rbsp | |
| 182 | CODECHAL_ENCODE_AVC_NAL_UT_EOSEQ = 0x0a, // End of sequence - end_of_seq_rbsp | |
| 183 | CODECHAL_ENCODE_AVC_NAL_UT_EOSTREAM = 0x0b, // End of stream - end_of_stream_rbsp | |
| 184 | CODECHAL_ENCODE_AVC_NAL_UT_FILL = 0x0c, // Filler data - filler_data_rbsp | |
| 185 | CODECHAL_ENCODE_AVC_NAL_UT_SEQEXT = 0x0d, // Sequence parameter set extension - seq_parameter_set_extension_rbsp | |
| 186 | CODECHAL_ENCODE_AVC_NAL_UT_PREFIX = 0x0e, // Prefix NAL unit in scalable extension - prefix_nal_unit_rbsp | |
| 187 | CODECHAL_ENCODE_AVC_NAL_UT_SUBSEQ = 0x0f, // Subset sequence parameter set - subset_seq_parameter_set_rbsp | |
| 188 | /* 0x10..0x12 - Reserved */ | |
| 189 | CODECHAL_ENCODE_AVC_NAL_UT_LAYERNOPART = 0x13, // Coded slice of an auxiliary coded picture without paritioning - slice_layer_without_partitioning_rbsp | |
| 190 | CODECHAL_ENCODE_AVC_NAL_UT_LAYERSCALEEXT = 0x14, // Coded slice in scalable extension - slice_layer_in_scalable_extension_rbsp | |
| 191 | /* 0x15..0x17 - Reserved */ | |
| 192 | /* 0x18..0x1f - Unspcified */ | |
| 193 | ||
| 194 | //this should be the last element of this enum | |
| 195 | //chagne this value if NAL unit type increased | |
| 196 | CODECHAL_ENCODE_AVC_MAX_NAL_TYPE = 0x1f, | |
| 197 | } CODECHAL_ENCODE_AVC_NAL_UNIT_TYPE; | |
| 198 | ||
| 199 | enum | |
| 200 | { | |
| 201 | SLICE_P = 0, | |
| 202 | SLICE_B = 1, | |
| 203 | SLICE_I = 2, | |
| 204 | SLICE_SP = 3, | |
| 205 | SLICE_SI = 4 | |
| 206 | }; | |
| 207 | typedef enum | |
| 208 | { | |
| 209 | CODECHAL_ENCODE_AVC_SINGLE_PASS = 0, | |
| 210 | CODECHAL_ENCODE_AVC_ICHAT = 1, | |
| 211 | CODECHAL_ENCODE_AVC_CAPTURE = 4, | |
| 212 | CODECHAL_ENCODE_AVC_APM = 20 | |
| 213 | } CODECHAL_ENCODE_AVC_ENCODER_USAGE; | |
| 214 | ||
| 215 | const uint8_t Slice_Type[10] = { SLICE_P, SLICE_B, SLICE_I, SLICE_SP, SLICE_SI, SLICE_P, SLICE_B, SLICE_I, SLICE_SP, SLICE_SI }; | |
| 216 | ||
| 217 | typedef struct _CODEC_ROI_MAP | |
| 218 | { | |
| 219 | char PriorityLevelOrDQp; // [-3..3] or [-51..51] | |
| 220 | uint8_t NumRect; | |
| 221 | CODEC_ROI Rect[16]; // disconnected areas which have same PriorityLevelOrDQp | |
| 222 | } CODEC_ROI_MAP, *PCODEC_ROI_MAP; | |
| 223 | ||
| 224 | typedef struct _CODEC_ENCODE_MB_CONTROL | |
| 225 | { | |
| 226 | union | |
| 227 | { | |
| 228 | struct | |
| 229 | { | |
| 230 | uint32_t bForceIntra : 1; | |
| 231 | uint32_t Reserved : 31; | |
| 232 | }; | |
| 233 | uint32_t value; | |
| 234 | } MBParams; | |
| 235 | } CODEC_ENCODE_MB_CONTROL, *PCODEC_ENCODE_MB_CONTROL; | |
| 236 | ||
| 237 | typedef struct _CODEC_PIC_REORDER | |
| 238 | { | |
| 239 | uint32_t PicNum; | |
| 240 | uint32_t POC; | |
| 241 | uint8_t ReorderPicNumIDC; | |
| 242 | uint8_t DiffPicNumMinus1; | |
| 243 | CODEC_PICTURE Picture; | |
| 244 | } CODEC_PIC_REORDER, *PCODEC_PIC_REORDER; | |
| 245 | ||
| 246 | /*! \brief Provides the sequence-level parameters of a compressed picture for AVC encoding. | |
| 247 | * | |
| 248 | * The framework is expected to only send a sequence parameter compressed buffer for the first picture(first Execute() call) in a sequence, associated with a RAP(IDR, CRA, BLA) picture. | |
| 249 | */ | |
| 250 | typedef struct _CODEC_AVC_ENCODE_SEQUENCE_PARAMS | |
| 251 | { | |
| 252 | uint16_t FrameWidth; //!< Width of the frame in pixels. | |
| 253 | uint16_t FrameHeight; //!< Height of the frame in pixels. | |
| 254 | uint8_t Profile; //!< Same as AVC syntax parameter profile_idc. | |
| 255 | uint8_t Level; //!< Same as AVC syntax parameter level_idc. | |
| 256 | ||
| 257 | uint16_t GopPicSize; //!< Distance between IRAP pictures. | |
| 258 | /*! \brief Distance between anchor frames (I or P). | |
| 259 | * | |
| 260 | * Here, P may also means low delay B (GPB) frames. | |
| 261 | * Programming Note: GopPicSize > GopRefDist should be ensured by application. It is required by BRC. | |
| 262 | */ | |
| 263 | uint16_t GopRefDist; | |
| 264 | uint16_t GopOptFlag : 2; | |
| 265 | uint16_t : 6; | |
| 266 | ||
| 267 | uint8_t TargetUsage; | |
| 268 | /*! \brief Specifies rate control method. | |
| 269 | * | |
| 270 | * \n 0: CQP, if set, internal BRC, multi-pass and panic mode will be disabled | |
| 271 | * \n 1: CBR | |
| 272 | * \n 2: VBR | |
| 273 | * \n 3: CQP, see above | |
| 274 | * \n 4: AVBR, if set, HRD compliance is not guaranteed. Buffering period SEI and picture timing SEI messages are not necessary for AVBR. | |
| 275 | * \n 5: Reserved | |
| 276 | * \n 6: Reserved | |
| 277 | * \n 7: Reserved | |
| 278 | * \n 8: LA, look ahead | |
| 279 | * \n 9: ICQ (Intelligent Constant Quality) | |
| 280 | * \n 10: VCM, defined for video converencing | |
| 281 | * \n 11: LA_ICQ | |
| 282 | * \n 12: LA_EXT, defined for server transcoding usage, 1 input video sequence generates several sequences with different bitrate | |
| 283 | * \n 13: LA_HRD, defined for server and client usage, lookahead with HRD and strict handling of maximum bitrate window | |
| 284 | * \n 14: QVBR (Quality Regulated VBR) | |
| 285 | * \n Programming note: Define the minimum value as indicated above for AVBR accuracy & convergence, clamp any value that is less than the minimum value to the minimum value. Define the maximum value for AVBR accuracy as 100 (10%) and for AVBR convergence as 500, clamp any value that is greater than the maximum value to the maximum value. The maximum & minimum value may be adjusted when necessary. If bResetBRC is set to 1 for a non-I picture, driver shall not insert SPS into bitstream. Driver needs to calculate the maximum allowed frame size per profile/level for all RateControlMethod except CQP, and use the calculated value to program kernel for non AVBR modes; for AVBR mode, driver needs to clamp the upper bound of UserMaxFrameSize to the calculated value and use the clamped UserMaxFrameSize to program kernel. If IWD_VBR is set, driver programs it the same as VBR except not to enable panic mode. | |
| 286 | */ | |
| 287 | uint8_t RateControlMethod; | |
| 288 | uint32_t TargetBitRate; //!< Target bit rate Kbit per second | |
| 289 | uint32_t MaxBitRate; //!< Maximum bit rate Kbit per second | |
| 290 | /*! \brief Minimun bit rate Kbit per second. | |
| 291 | * | |
| 292 | * This is used in VBR control. For CBR control, this field is ignored. | |
| 293 | */ | |
| 294 | uint32_t MinBitRate; | |
| 295 | uint16_t FramesPer100Sec; //!< Total frames per 100 second (frame rate fps * 100). | |
| 296 | uint32_t InitVBVBufferFullnessInBit; //!< Initial VBV buffer fullness in bits. | |
| 297 | /*! \brief VBV buffer size in bit unit. | |
| 298 | * | |
| 299 | * The AVC spec defines a max coded picture buffer size for each level. | |
| 300 | */ | |
| 301 | uint32_t VBVBufferSizeInBit; | |
| 302 | /*! \brief Specifies number of reference frames. | |
| 303 | * | |
| 304 | * Should not be greater than driver reported max number of references. | |
| 305 | */ | |
| 306 | uint8_t NumRefFrames; | |
| 307 | ||
| 308 | /*! \brief Same as AVC syntax element. | |
| 309 | * | |
| 310 | * Should not be greater than max SPS set reported by driver. | |
| 311 | */ | |
| 312 | uint8_t seq_parameter_set_id; | |
| 313 | uint8_t chroma_format_idc; //!< Same as AVC syntax element. | |
| 314 | uint8_t bit_depth_luma_minus8; //!< Same as AVC syntax element. | |
| 315 | uint8_t bit_depth_chroma_minus8; //!< Same as AVC syntax element. | |
| 316 | uint8_t log2_max_frame_num_minus4; //!< Same as AVC syntax element. | |
| 317 | uint8_t pic_order_cnt_type; //!< Same as AVC syntax element. | |
| 318 | uint8_t log2_max_pic_order_cnt_lsb_minus4; //!< Same as AVC syntax element. | |
| 319 | uint8_t num_ref_frames_in_pic_order_cnt_cycle; //!< Same as AVC syntax element. | |
| 320 | int32_t offset_for_non_ref_pic; //!< Same as AVC syntax element. | |
| 321 | int32_t offset_for_top_to_bottom_field; //!< Same as AVC syntax element. | |
| 322 | int32_t offset_for_ref_frame[256]; //!< Same as AVC syntax element. | |
| 323 | uint16_t frame_crop_left_offset; //!< Same as AVC syntax element. | |
| 324 | uint16_t frame_crop_right_offset; //!< Same as AVC syntax element. | |
| 325 | uint16_t frame_crop_top_offset; //!< Same as AVC syntax element. | |
| 326 | uint16_t frame_crop_bottom_offset; //!< Same as AVC syntax element. | |
| 327 | ||
| 328 | uint16_t seq_scaling_list_present_flag[12]; //!< Same as AVC syntax element. | |
| 329 | uint16_t seq_scaling_matrix_present_flag : 1; //!< Same as AVC syntax element. | |
| 330 | uint16_t delta_pic_order_always_zero_flag : 1; //!< Same as AVC syntax element. | |
| 331 | uint16_t frame_mbs_only_flag : 1; //!< Same as AVC syntax element. | |
| 332 | uint16_t direct_8x8_inference_flag : 1; //!< Same as AVC syntax element. | |
| 333 | uint16_t vui_parameters_present_flag : 1; //!< Same as AVC syntax element. | |
| 334 | uint16_t frame_cropping_flag : 1; //!< Same as AVC syntax element. | |
| 335 | /*! \brief Specifies that encoded slices returned fit within the slice size specified in the picture parameter set for AVC. | |
| 336 | * | |
| 337 | * When enabled, this overrides the slice structures specified by the application using slice level parameters. | |
| 338 | */ | |
| 339 | uint16_t EnableSliceLevelRateCtrl : 1; | |
| 340 | uint16_t : 8; | |
| 341 | union | |
| 342 | { | |
| 343 | struct | |
| 344 | { | |
| 345 | uint32_t bInitBRC : 1; | |
| 346 | /*! \brief Indicate if a BRC reset is desired to set a new bit rate or frame rate. | |
| 347 | * | |
| 348 | * This setting is only valid if RateControlMethod is AVBR, VBR, CBR, VCM, ICQ, CQL or QVBR and the current picture is an I picture. If the frame resolution is changed, it should be set with IDR picture. It should not be set when RateControlMethod is CBR or CQP. The following table indicates which BRC parameters can be changed via a BRC reset. | |
| 349 | * | |
| 350 | * \n BRC Parameters Changes allowed via reset | |
| 351 | * \n Profile & Level Yes | |
| 352 | * \n UserMaxFrameSize Yes | |
| 353 | * \n InitVBVBufferFullnessInBit No | |
| 354 | * \n TargetBitRate Yes | |
| 355 | * \n VBVBufferSizeInBit No | |
| 356 | * \n MaxBitRate Yes | |
| 357 | * \n FramesPer100Sec * No | |
| 358 | * \n RateControlMethod No | |
| 359 | * \n GopPicSize No | |
| 360 | * \n GopRefDist No | |
| 361 | * \n GopOptFlag Yes | |
| 362 | * \n FrameWidth No | |
| 363 | * \n FrameHeight No | |
| 364 | * \n Note: when resolution (FrameWidth and/or FrameHeight) changes, framework should re-start a new bit stream and not using BRC reset. | |
| 365 | */ | |
| 366 | uint32_t bResetBRC : 1; | |
| 367 | /*! \brief Indicates that current SPS is just a BRC parameter update, not a SPS change to be inserted into the bitstream. | |
| 368 | * | |
| 369 | * When set to 1, current SPS will not be packed and inserted into bitstream by the driver. | |
| 370 | */ | |
| 371 | uint32_t bNoAcceleratorSPSInsertion : 1; | |
| 372 | /*! \brief Indicates the global search options. | |
| 373 | * | |
| 374 | * It is only valid if EnhancedEncInput is reported during capability checking: | |
| 375 | * \n - 0: Default - option internally selected based on target usage | |
| 376 | * \n - 1: Long - SHME enabled | |
| 377 | * \n - 2: Medium - HME only enabled, SHME disabled | |
| 378 | * \n - 3: Short - SHME/HME disabled | |
| 379 | */ | |
| 380 | uint32_t GlobalSearch : 2; | |
| 381 | /*! \brief Indicates the local search options. | |
| 382 | * | |
| 383 | * It is only valid if EnhancedEncInput is reported during capability checking: | |
| 384 | * \n - 0: Default - option internally selected based on target usage | |
| 385 | * \n - 1: Tiny – MaxLenSP = 4, Reference Window = 24x24 SP = Spiral | |
| 386 | * \n - 2: Small – MaxLenSP = 9, Reference Window = 28x28 SP = Spiral | |
| 387 | * \n - 3: Square – MaxLenSP = 16, Reference Window = 32x32 SP = Spiral | |
| 388 | * \n - 4: Diamond – MaxLenSP = 16, Reference Window = 48x40 SP = Diamond | |
| 389 | * \n - 5: Large Diamond – MaxLenSP = 30, Reference Window = 48x40 SP = Diamond | |
| 390 | * \n - 6: Exhaustive – MaxLenSP = 57, Reference Window = 48x40 SP = Spiral | |
| 391 | * \n - 7: Heavy Horizontal – MaxLenSP = 57, Reference Window = 64x32 SP = Spiral | |
| 392 | * \n - 8: Heavy Vertical – MaxLenSP = 57, Reference Window = 32x64 SP = Spiral | |
| 393 | */ | |
| 394 | uint32_t LocalSearch : 4; | |
| 395 | /*! \brief Indicates early skip control. | |
| 396 | * | |
| 397 | * It is only valid if EnhancedEncInput is reported during capability checking: | |
| 398 | * \n - 0: Default, decided internally | |
| 399 | * \n - 1: EarlySkip enabled | |
| 400 | * \n - 2: EarlySkip disabled | |
| 401 | */ | |
| 402 | uint32_t EarlySkip : 2; | |
| 403 | uint32_t Reserved0 : 1; | |
| 404 | /*! \brief Indicates that MB BRC is enabled. | |
| 405 | * | |
| 406 | * It is only valid if MBBRCSupport is reported during capability checking: | |
| 407 | * \n - 0: Default, decided internally based on target usage. | |
| 408 | * \n - 1: MB BRC enabled. | |
| 409 | * \n - 2: MB BRC disabled. | |
| 410 | * \n - Other values are Reserved. | |
| 411 | * \n Currently MB BRC can be applied to all bit rate control methods except CQP. | |
| 412 | */ | |
| 413 | uint32_t MBBRC : 4; | |
| 414 | /*! \brief Indicates trellis control. | |
| 415 | * | |
| 416 | * The Trellis_I, Trellis_P and Trellis_B settings may be combined using bitwise OR like "Trellis_I | Trellis_P" to enable Trellis for I & P. If Trellis_Disabled is set with any combination, Trellis will be disabled. | |
| 417 | * \n - 0: Trellis_Default – Trellis decided internally. | |
| 418 | * \n - 1: Trellis_Disabled – Trellis disabled for all frames/fields. | |
| 419 | * \n - 2: Trellis_I – Trellis enabled for I frames/fields. | |
| 420 | * \n - 4: Trellis_P – Trellis enabled for P frames/fields. | |
| 421 | * \n - 8: Trellis_B – Trellis enabled for B frames/fields. | |
| 422 | */ | |
| 423 | uint32_t Trellis : 4; | |
| 424 | /*! \brief Indicates current sequence is encoded for Temporal Scalability. | |
| 425 | * The driver may or may not use this flag. For example, for VME+PAK AVC encoder MSDK handles all header insertion to indicate a temporal id in the SVC ext slice header and this flag is not used. However, for VDEnc AVC encoder in certain cases BRC is required to know if the current frames are being encoded for temporal scalability and therefore will have extra SVC ext added in the slice header. | |
| 426 | * \n - 0: Default, current sequence is not encoded for Temporal Scalability. | |
| 427 | * \n - 1: current sequence is encoded is encoded for Temporal Scalability. | |
| 428 | */ | |
| 429 | uint32_t bTemporalScalability : 1; | |
| 430 | /*! \brief Indicates ROI[] value is in delta QP or priority. | |
| 431 | * | |
| 432 | * It is valid only when parameter NumROI is greater than 0 and either ROIDeltaQPSupport or ROIBRCPriorityLevelSupport equals to 1. | |
| 433 | * \n - 0: Default, ROI[] value is in priority. | |
| 434 | * \n - 1: ROI[] value is in delta QP. | |
| 435 | * \n Currently only ROIValueInDeltaQP equal 1 is validated for CQP | |
| 436 | */ | |
| 437 | uint32_t ROIValueInDeltaQP : 1; | |
| 438 | /*! \brief Indicates larger P/B frame size than UserMaxPBFrameSize may be used. | |
| 439 | * | |
| 440 | * if enabled, BRC may decide a larger P or B frame size than what UserMaxPBFrameSize dictates when the scene change is detected. | |
| 441 | * \n - 0: Default, normal BRC. | |
| 442 | * \n - 1: BRC may decide larger P/B frame size. | |
| 443 | */ | |
| 444 | uint32_t bAutoMaxPBFrameSizeForSceneChange : 1; | |
| 445 | /* Control the force panic mode through DDI other than user feature key */ | |
| 446 | uint32_t bForcePanicModeControl : 1; | |
| 447 | uint32_t bPanicModeDisable : 1; | |
| 448 | ||
| 449 | /*! \brief Enables streaming buffer in LLC | |
| 450 | * | |
| 451 | * \n - 0 : streaming buffer by LLC is disabled. | |
| 452 | * \n - 1 : streaming buffer by LLC is enabled. | |
| 453 | */ | |
| 454 | uint32_t EnableStreamingBufferLLC : 1; | |
| 455 | /*! \brief Enables streaming buffer in DDR | |
| 456 | * | |
| 457 | * \n - 0 : streaming buffer by DDR is disabled. | |
| 458 | * \n - 1 : streaming buffer by DDR is enabled. | |
| 459 | */ | |
| 460 | uint32_t EnableStreamingBufferDDR : 1; | |
| 461 | /*! \brief Indicates whether or not the encoding is in hierarchical GOP structure, for both RA B and LD B frame types | |
| 462 | * | |
| 463 | * \n - 0 : BRC would treat it as flat structure. | |
| 464 | * \n - 1 : hierarchical structure. | |
| 465 | * \n In another word, this flag is equivalent to Qp Modulation enabling flag. If HierarchicalFlag == 1, app would enable Qp modulation for either random access or low delay hierarchical structure. | |
| 466 | */ | |
| 467 | uint32_t HierarchicalFlag : 1; | |
| 468 | /*! \brief Indicates whether or not the encoding is in low delay mode. | |
| 469 | * | |
| 470 | * \n - 0 : the non-base temporal layers should be coded as random access B frames. | |
| 471 | * \n - 1 : no random access B will be coded. And the coding type could be only I or P. | |
| 472 | * \n Note: this flag only indicates the frame coding type, and is not related to BRC low delay mode. | |
| 473 | */ | |
| 474 | uint32_t LowDelayMode : 1; | |
| 475 | /*! \brief Indicates if current encodin gis lookahead pass. | |
| 476 | * | |
| 477 | * \n - 0 : the current encoding is in the actual encoding pass, and one of the BRC modes (CBR, VBR, etc.) should be selected. | |
| 478 | * \n - 1 : the current encoding is in the lookahead pass. | |
| 479 | * \n Valid only when LookAheadAnalysisSupport in CAP is on and LookAheadDepth > 0. | |
| 480 | */ | |
| 481 | uint32_t bLookAheadPhase : 1; | |
| 482 | uint32_t Reserved1 : 2; | |
| 483 | }; | |
| 484 | uint32_t sFlags; | |
| 485 | }; | |
| 486 | /*! \brief Framework defined maximum frame size in bytes for I frames. | |
| 487 | * | |
| 488 | * Applicable for all RateControlMethod values except CQP; guarantees that the compressed frame size will be less than this value. If UserMaxPBFrameSize equals 0, UserMaxIFrameSize will be used for all frame types. Maximum allowed frame size per profile/level will be calculated in driver and be used when UserMaxIFrameSize and UserMaxPBFrameSize are both set to 0. | |
| 489 | */ | |
| 490 | uint32_t UserMaxFrameSize; | |
| 491 | /*! \brief Framework defined maximum frame size in bytes for P & B frames. | |
| 492 | * | |
| 493 | * Applicable for all RateControlMethod values except CQP; guarantees that the compressed frame size will be less than this value. If UserMaxPBFrameSize equals 0, UserMaxIFrameSize will be used for all frame types. Maximum allowed frame size per profile/level will be calculated in driver and be used when UserMaxIFrameSize and UserMaxPBFrameSize are both set to 0. | |
| 494 | */ | |
| 495 | uint32_t UserMaxPBFrameSize; | |
| 496 | /*! \brief Indicates the measure of quality for ICQ and QVBR | |
| 497 | * | |
| 498 | * The range is from 1 – 51, with 1 being the best quality. | |
| 499 | */ | |
| 500 | uint16_t ICQQualityFactor; | |
| 501 | /*! \brief Indicates the bitrate accuracy for AVBR | |
| 502 | * | |
| 503 | * The range is [1, 100], 1 means one percent, and so on. | |
| 504 | */ | |
| 505 | uint32_t AVBRAccuracy; | |
| 506 | /*! \brief Indicates the bitrate convergence period for AVBR | |
| 507 | * | |
| 508 | * The unit is frame. | |
| 509 | */ | |
| 510 | uint32_t AVBRConvergence; | |
| 511 | ||
| 512 | /*! \brief Indicates the uncompressed input color space | |
| 513 | * | |
| 514 | * Valid only when input is ARGB format. | |
| 515 | */ | |
| 516 | ENCODE_INPUT_COLORSPACE InputColorSpace; | |
| 517 | /*! \brief Provides a hint to encoder about the scenario for the encoding session. | |
| 518 | * | |
| 519 | * BRC algorithm may tune differently based on this info. | |
| 520 | */ | |
| 521 | ENCODE_SCENARIO ScenarioInfo; | |
| 522 | ENCODE_CONTENT ContentInfo; //!< Provides a hint to encoder about the content for the encoding session. | |
| 523 | ||
| 524 | /*! \brief Indicates the tolerance the application has to variations in the frame size. | |
| 525 | * | |
| 526 | * It affects the BRC algorithm used, but may or may not have an effect based on the combination of other BRC parameters. Only valid when the driver reports support for FrameSizeToleranceSupport. | |
| 527 | */ | |
| 528 | ENCODE_FRAMESIZE_TOLERANCE FrameSizeTolerance; | |
| 529 | ||
| 530 | /*! \brief Indicates BRC Sliding window size in terms of number of frames. | |
| 531 | * | |
| 532 | * Defined for CBR and VBR. For other BRC modes or CQP, values are ignored. | |
| 533 | */ | |
| 534 | uint16_t SlidingWindowSize; | |
| 535 | ||
| 536 | /*! \brief Indicates maximun bit rate Kbit per second within the sliding window during. | |
| 537 | * | |
| 538 | * Defined for CBR and VBR. For other BRC modes or CQP, values are ignored. | |
| 539 | */ | |
| 540 | uint32_t MaxBitRatePerSlidingWindow; | |
| 541 | ||
| 542 | /*! \brief Indicates minimun bit rate Kbit per second within the sliding window during. | |
| 543 | * | |
| 544 | * Defined for CBR and VBR. For other BRC modes or CQP, values are ignored. | |
| 545 | */ | |
| 546 | uint32_t MinBitRatePerSlidingWindow; | |
| 547 | ||
| 548 | /*! \brief Indicates number of frames to lookahead. | |
| 549 | * | |
| 550 | * Range is [0~127]. Default is 0 which means lookahead disabled. Valid only when LookaheadBRCSupport is 1. When not 0, application should send LOOKAHEADDATA buffer to driver. | |
| 551 | */ | |
| 552 | uint8_t LookaheadDepth; | |
| 553 | ||
| 554 | uint8_t constraint_set0_flag : 1; //!< Same as AVC syntax element. | |
| 555 | uint8_t constraint_set1_flag : 1; //!< Same as AVC syntax element. | |
| 556 | uint8_t constraint_set2_flag : 1; //!< Same as AVC syntax element. | |
| 557 | uint8_t constraint_set3_flag : 1; //!< Same as AVC syntax element. | |
| 558 | uint8_t : 4; | |
| 559 | uint8_t separate_colour_plane_flag; //!< Same as AVC syntax element. | |
| 560 | bool qpprime_y_zero_transform_bypass_flag; //!< Same as AVC syntax element. | |
| 561 | bool gaps_in_frame_num_value_allowed_flag; //!< Same as AVC syntax element. | |
| 562 | uint16_t pic_width_in_mbs_minus1; //!< Same as AVC syntax element. | |
| 563 | uint16_t pic_height_in_map_units_minus1; //!< Same as AVC syntax element. | |
| 564 | bool mb_adaptive_frame_field_flag; //!< Same as AVC syntax element. | |
| 565 | } CODEC_AVC_ENCODE_SEQUENCE_PARAMS, *PCODEC_AVC_ENCODE_SEQUENCE_PARAMS; | |
| 566 | ||
| 567 | typedef struct _CODEC_AVC_ENCODE_USER_FLAGS | |
| 568 | { | |
| 569 | union | |
| 570 | { | |
| 571 | struct | |
| 572 | { | |
| 573 | /*! \brief Indicates that raw pictures should be used as references instead of recon pictures. | |
| 574 | * | |
| 575 | * Setting to 1 may improve performance at the cost of image quality. The accelerator may or may not support toggling this value on a per frame basis. | |
| 576 | */ | |
| 577 | uint32_t bUseRawPicForRef : 1; | |
| 578 | /*! \brief Indicates whether or not the driver will pack non-slice headers. | |
| 579 | * | |
| 580 | * Applies to ENC + PAK mode only. This flag is only valid only when AcceleratorHeaderPacking = 1, and driver does the header packing. | |
| 581 | * \n - 0: Accelerator will pack AU delimiter, SPS (including VUI if present), PPS, SEI messages if present, end of sequence if indicated, and end of stream if indicated, along with coded slice to form a complete bitstream. | |
| 582 | * \n - 1: Accelerator will just pack coded slice (slice header + data), like in PAK only mode, and the application will pack the rest of the headers. | |
| 583 | */ | |
| 584 | uint32_t bDisableAcceleratorHeaderPacking : 1; | |
| 585 | uint32_t : 5; | |
| 586 | uint32_t bDisableSubMBPartition : 1; //!< Indicates that sub MB partitioning should be disabled. | |
| 587 | /*! \brief Inidicates whether or not emulation byte are inserted. | |
| 588 | * | |
| 589 | * If 1, accelerator will perform start code prefix (0x 00 00 01/02/03/00) search and emulation byte (0x 03) insertion on packed header data. This doesn’t apply to packed slice header data. Packed slice header data must not have emulation byte inserted, accelerator will always perform start code prefix search and emulation byte (0x 03) insertion on packed slice header data. | |
| 590 | * Note: If cabac_zero_word insertion compliance is required, this value should be set to 0. This means the application must perform emulation prevention byte insertion in the frame header. This is due to the restriction in MFX_PAK_INSERT_OBJECT HeaderLengthExcludeFrmSize cannot allow EmulationFlag to be true. | |
| 591 | */ | |
| 592 | uint32_t bEmulationByteInsertion : 1; | |
| 593 | /*! \brief Specifies the type of intra refresh used. | |
| 594 | * | |
| 595 | * Effective only when RollingINtraRefresh capability in use. Applies to P pictures only (not valid with IBP). When used field encoding, B frames, and multiple references are not allowed. | |
| 596 | * \n - 0 : disabled | |
| 597 | * \n - 1 : enabled in colum | |
| 598 | * \n - 2 : enabled in row | |
| 599 | * \n - 3 : enabled in region | |
| 600 | */ | |
| 601 | uint32_t bEnableRollingIntraRefresh : 2; | |
| 602 | ||
| 603 | /*! \brief Specifies if Slice Level Reporitng may be requested for this frame | |
| 604 | * | |
| 605 | * If this flag is set, then slice level parameter reporting will be set up for this frame. Only valid if SliceLevelReportSupport is reported in ENCODE_CAPS, else this flag is ignored. | |
| 606 | * | |
| 607 | */ | |
| 608 | uint32_t bEnableSliceLevelReport : 1; | |
| 609 | ||
| 610 | /*! \brief Specifies if integer mode searching is performed | |
| 611 | * | |
| 612 | * when set to 1, integer mode searching is performed | |
| 613 | * | |
| 614 | */ | |
| 615 | uint32_t bDisableSubpixel : 1; | |
| 616 | ||
| 617 | /*! \brief Specifies if the overlapped operation of intra refresh is disabled | |
| 618 | * | |
| 619 | * It is valid only when bEnableRollingIntraRefresh is on. | |
| 620 | * \n - 0 : default, overlapped Intra refresh is applied | |
| 621 | * \n - 1 : intra refresh without overlap operation | |
| 622 | * | |
| 623 | */ | |
| 624 | uint32_t bDisableRollingIntraRefreshOverlap : 1; | |
| 625 | ||
| 626 | /*! \brief Specifies whether extra partition decision refinement is done after the initial partition decision candidate is determined. | |
| 627 | * | |
| 628 | * It has performance tradeoff for better quality. | |
| 629 | * \n - 0 : DEFAULT - Follow driver default settings. | |
| 630 | * \n - 1 : FORCE_ENABLE - Enable this feature totally for all cases. | |
| 631 | * \n - 2 : FORCE_DISABLE - Disable this feature totally for all cases. | |
| 632 | */ | |
| 633 | uint32_t ForceRepartitionCheck : 2; | |
| 634 | uint32_t bReserved : 16; | |
| 635 | }; | |
| 636 | uint32_t Value; | |
| 637 | }; | |
| 638 | } CODEC_AVC_ENCODE_USER_FLAGS, *PCODEC_AVC_ENCODE_USER_FLAGS; | |
| 639 | ||
| 640 | typedef struct _CODEC_AVC_ENCODE_FORCE_SKIP_PARAMS | |
| 641 | { | |
| 642 | uint32_t Enable; | |
| 643 | uint32_t Xpos; | |
| 644 | uint32_t Ypos; | |
| 645 | uint32_t Width; | |
| 646 | uint32_t Height; | |
| 647 | ||
| 648 | } CODEC_AVC_ENCODE_FORCE_SKIP_PARAMS, *PCODEC_AVC_ENCODE_FORCE_SKIP_PARAMS; | |
| 649 | ||
| 650 | /*! \brief Provides the picture-level parameters of a compressed picture for AVC encoding. | |
| 651 | */ | |
| 652 | typedef struct _CODEC_AVC_ENCODE_PIC_PARAMS | |
| 653 | { | |
| 654 | /*! \brief Specifies the uncompressed source surface of the frame for the current picture to be encode. | |
| 655 | * | |
| 656 | * The PicFlags regarding reference usage are expected to be valid at this time. | |
| 657 | */ | |
| 658 | CODEC_PICTURE CurrOriginalPic; | |
| 659 | /*! \brief Specifies the uncompressed surface of the reconstructed frame for the current encoded picture. | |
| 660 | * | |
| 661 | * The PicFlags regarding reference usage are expected to be valid at this time. | |
| 662 | * The recon surface may be of different format and different bit depth from that of source. | |
| 663 | * The framework needs to specify it through chroma_format_idc and bit_depth_luma_minus8 and | |
| 664 | * bit_depth_chroma_minus8 in SPS data structure. | |
| 665 | */ | |
| 666 | CODEC_PICTURE CurrReconstructedPic; | |
| 667 | /*! \brief Specifies picture coding type. | |
| 668 | * | |
| 669 | * \n 1: I picture | |
| 670 | * \n 2: P picture | |
| 671 | * \n 3: B picture | |
| 672 | */ | |
| 673 | uint8_t CodingType; | |
| 674 | /*! \brief Specifies that field mode coding is in use. | |
| 675 | * | |
| 676 | * Top or bottom field indicated by CurrOriginalPic.PicFlags. | |
| 677 | */ | |
| 678 | uint8_t FieldCodingFlag : 1; | |
| 679 | /*! \brief Specifies that MBAFF coding mode is in use. | |
| 680 | * | |
| 681 | * It shall not be set if NoFieldFrame flag is reported in CodingLimit during capability checking. | |
| 682 | */ | |
| 683 | uint8_t FieldFrameCodingFlag : 1; | |
| 684 | uint8_t : 6; | |
| 685 | /*! \brief Specifies the number of slices per frame or per field in field coding. | |
| 686 | * | |
| 687 | * Note the restriction on slice based on the SliceStructure reported during capability checking. | |
| 688 | */ | |
| 689 | uint32_t NumSlice; | |
| 690 | ||
| 691 | /*! \brief Quantization parameter for Y. | |
| 692 | * | |
| 693 | * Valid range is 0 - 51. If QpY is set to -1, driver will use an internal default value when CQP is not set, otherwise, driver will return error. Please note that, QpY is a frame level QP. QP for each slice is determined by QpY + slice_qp_delta. And QpY + slice_qp_delta should be also in the range of 0 – 51, inclusive. | |
| 694 | */ | |
| 695 | char QpY; | |
| 696 | /*! \brief Each entry of the list specifies the frame index of the reference pictures. | |
| 697 | * | |
| 698 | * The value of FrameIdx specifies the index of RefFrameList structure. And valid value range is [0..14, 0x7F]. Invalid entries are indicated by setting PicFlags to PICTURE_INVALID. | |
| 699 | * RefFrameList[] should include all the reference pictures in DPB, which means either the picture is referred by current picture or future pictures, it should have a valid entry in it. | |
| 700 | */ | |
| 701 | CODEC_PICTURE RefFrameList[CODEC_AVC_MAX_NUM_REF_FRAME]; | |
| 702 | /*! \brief Denotes "used for reference" frames as defined in the AVC specification. | |
| 703 | * | |
| 704 | * The flag is accessed by: | |
| 705 | * \n - FlagTop(i) = (UsedForReferenceFlags >> (2 * i)) & 1 | |
| 706 | * \n - FlagBottom(i) = (UsedForReferenceFlags >> (2 * i + 1)) & 1 | |
| 707 | * \n If FlagTop(i) is 1, the top field or frame numger i is marked as "used for reference"; if FlagBottom(i) is 1 then then bottom field of frame i is marked as "used for reference". If either is 0 then the frame is not marked as "used for reference". | |
| 708 | */ | |
| 709 | uint32_t UsedForReferenceFlags; | |
| 710 | /*! \brief Contains the picture order counts (POC) for the current frame | |
| 711 | * | |
| 712 | * If field_pic_flag is 0: | |
| 713 | * \n - CurrFieldOrderCnt[0] contains the top field order count for the current picture | |
| 714 | * \n - CurrFieldOrderCnt[1] contains the bottom field order count for the current picture | |
| 715 | * \n If field_pic_flag is 1 and CurrPic.PicFlags indicates that this is a top field: | |
| 716 | * \n - CurrFieldOrderCnt[0] contains the top field order count for the current picture | |
| 717 | * \n - CurrFieldOrderCnt[1] | |
| 718 | * \n If field_pic_flag is 1 and CurrPic.PicFlags indicates that this is a bottom field: | |
| 719 | * \n - CurrFieldOrderCnt[0] should be 0 or ignored | |
| 720 | * \n - CurrFieldOrderCnt[1] contains the bottom field order count for the current picture | |
| 721 | */ | |
| 722 | int32_t CurrFieldOrderCnt[2]; | |
| 723 | /*! \brief Contains the POCs for the reference frames in RefFrameList. | |
| 724 | * | |
| 725 | * For each entry FieldOrderCntList[i][j]: | |
| 726 | * \n - i: the picture index | |
| 727 | * \n - j: 0 specifies the top field order count and 1 specifies the bottom field order count | |
| 728 | * \n If a entry i in RefFrameList is not relevant (it is not used for reference) or valid, the entry FieldOrderCount[i][0 and 1] should be 0. | |
| 729 | */ | |
| 730 | int32_t FieldOrderCntList[16][2]; | |
| 731 | uint16_t frame_num; //!< Same as AVC syntax element. | |
| 732 | bool bLastPicInSeq; //!< Indicate whether to insert sequence closing NAL unit. | |
| 733 | bool bLastPicInStream; //!< Indicate whether to insert stream closing NAL unit. | |
| 734 | ||
| 735 | CODEC_AVC_ENCODE_USER_FLAGS UserFlags; | |
| 736 | CODEC_AVC_ENCODE_FORCE_SKIP_PARAMS ForceSkip; | |
| 737 | bool bStreamOutEnbleSinglePassvdenc; | |
| 738 | bool bHMEActiveCtrlFrmApp; | |
| 739 | bool bHMEActive; | |
| 740 | ||
| 741 | /*! \brief Arbitrary number set by the host decoder to use as a tag in the status report feedback data. | |
| 742 | * | |
| 743 | * The value should not equal 0, and should be different in each call to Execute. | |
| 744 | */ | |
| 745 | uint32_t StatusReportFeedbackNumber; | |
| 746 | ||
| 747 | uint8_t bIdrPic; //!< Indicates that the current picture is IDR. | |
| 748 | uint8_t pic_parameter_set_id; //!< Same as AVC syntax element. | |
| 749 | uint8_t seq_parameter_set_id; //!< Same as AVC syntax element. | |
| 750 | uint8_t num_ref_idx_l0_active_minus1; //!< Same as AVC syntax element. | |
| 751 | uint8_t num_ref_idx_l1_active_minus1; //!< Same as AVC syntax element. | |
| 752 | char chroma_qp_index_offset; //!< Same as AVC syntax element. | |
| 753 | char second_chroma_qp_index_offset; //!< Same as AVC syntax element. | |
| 754 | ||
| 755 | uint16_t pic_scaling_list_present_flag[12]; //!< Same as AVC syntax element. | |
| 756 | uint16_t entropy_coding_mode_flag : 1; //!< Same as AVC syntax element. | |
| 757 | uint16_t pic_order_present_flag : 1; //!< Same as AVC syntax element. | |
| 758 | uint16_t weighted_pred_flag : 1; //!< Same as AVC syntax element. | |
| 759 | uint16_t weighted_bipred_idc : 2; //!< Same as AVC syntax element. | |
| 760 | uint16_t constrained_intra_pred_flag : 1; //!< Same as AVC syntax element. | |
| 761 | uint16_t transform_8x8_mode_flag : 1; //!< Same as AVC syntax element. | |
| 762 | uint16_t pic_scaling_matrix_present_flag : 1; //!< Same as AVC syntax element. | |
| 763 | uint16_t RefPicFlag : 1; //!< Indicates that the current picture (raw or recon) may be used as a reference for encoding other pictures. | |
| 764 | /*! \brief Indicates how precise the framework would like BRC to be to reach the ideal requested framesize. | |
| 765 | * | |
| 766 | * The driver will internally make programming decisions based on this parameter, it will be a tradeoff between performance and precision. This flag is ignored if BRC is not enabled (CQP mode). | |
| 767 | * \n - 0: default precision (normal) | |
| 768 | * \n - 1: lowest precision | |
| 769 | * \n - 2: normal precision | |
| 770 | * \n - 3: highest precision | |
| 771 | */ | |
| 772 | uint16_t BRCPrecision : 2; | |
| 773 | /*! \brief Indicates that the allocated source buffer format is a swizzle format from display. | |
| 774 | * | |
| 775 | * Framework still allocates the buffer as a standard FOURCC format. The swizzled format will be reported as supported for the encoder configuration during capability reporting. | |
| 776 | * \n Source/Raw Allocated Buffer Format, DisplayFormatSwizzle, Layout Format in Buffer | |
| 777 | * \n - YUY2, 0, YUY2 | |
| 778 | * \n - YUY2, 1, 2YUY (Y0U0Y1V0) | |
| 779 | * \n - AYUV, 0, AYUV | |
| 780 | * \n - AYUV, 1, YUXV | |
| 781 | */ | |
| 782 | uint16_t bDisplayFormatSwizzle : 1; | |
| 783 | uint16_t : 3; | |
| 784 | ||
| 785 | uint8_t num_slice_groups_minus1; //!< Same as AVC syntax element. | |
| 786 | char pic_init_qp_minus26; //!< Same as AVC syntax element. | |
| 787 | char pic_init_qs_minus26; //!< Same as AVC syntax element. | |
| 788 | bool deblocking_filter_control_present_flag; //!< Same as AVC syntax element. | |
| 789 | bool redundant_pic_cnt_present_flag; //!< Same as AVC syntax element. | |
| 790 | ||
| 791 | // Parameters for RollingI feature | |
| 792 | bool bDisableRollingIntraRefreshOverlap; | |
| 793 | uint8_t EnableRollingIntraRefresh; | |
| 794 | uint8_t IntraRefreshMBNum; | |
| 795 | uint8_t IntraRefreshMBx; | |
| 796 | uint8_t IntraRefreshMBy; | |
| 797 | uint8_t IntraRefreshUnitinMB; | |
| 798 | char IntraRefreshQPDelta; | |
| 799 | uint32_t FirstPFrameIntraInsertionSize; | |
| 800 | ||
| 801 | /*! \brief Indicates the maximum size of each slice in Bytes. | |
| 802 | * | |
| 803 | * This is valid only when EnableSliceLevelRateCtrl is enabled in the sequence level. | |
| 804 | */ | |
| 805 | uint32_t SliceSizeInBytes; | |
| 806 | ||
| 807 | /*! \brief Number of Region Of Interest (ROI). | |
| 808 | * | |
| 809 | * Value range is 0 to 16 inclusively. If no ROI to be set, this value shall be set to 0. | |
| 810 | */ | |
| 811 | uint8_t NumROI; | |
| 812 | uint8_t NumDirtyROI; //!< Number of dirty ROIs [0...4] | |
| 813 | uint8_t NumDeltaQpForNonRectROI; //!< Number of DeltaQP for non-rectangular ROIs [0...16] | |
| 814 | /*! \brief Dictates the value of delta QP for any ROI should be within [MinDeltaQp..MaxDeltaQp] | |
| 815 | * | |
| 816 | * Applies only to BRC case. | |
| 817 | */ | |
| 818 | char MaxDeltaQp; | |
| 819 | /*! \brief Dictates the value of delta QP for any ROI should be within [MinDeltaQp..MaxDeltaQp] | |
| 820 | * | |
| 821 | * Applies only to BRC case. | |
| 822 | */ | |
| 823 | char MinDeltaQp; | |
| 824 | /*! \brief Determine possible DeltaQP values for NonRectROI. For BRC case values should be within [MinDeltaQp..MaxDeltaQp] | |
| 825 | * | |
| 826 | * QP value for the MB is represented by NonRectROIDeltaQpList[QpData - 1], | |
| 827 | * where QpData - UCHAR in ENCODE_MBQPDATA structure. | |
| 828 | * if QpData == 0, the block is in the background, and slice QP (QpY + slice_qp_delta) is applied on this MB. | |
| 829 | */ | |
| 830 | char NonRectROIDeltaQpList[16]; | |
| 831 | /*! \brief Defines ROI settings. | |
| 832 | * | |
| 833 | * Value entries are ROI[0] up to ROI[NumROI – 1], inclusively, if NumROI > 0. And it can be ignored otherwise. | |
| 834 | */ | |
| 835 | CODEC_ROI ROI[16]; | |
| 836 | /*! \brief Distinct delta QP values assigned to the ROI | |
| 837 | * | |
| 838 | * Value entries are distinct and within [MinDeltaQp..MaxDeltaQp]. | |
| 839 | */ | |
| 840 | int8_t ROIDistinctDeltaQp[16]; | |
| 841 | /*! \brief Number of distinct delta QP values assigned to the ROI | |
| 842 | */ | |
| 843 | int8_t NumROIDistinctDeltaQp; | |
| 844 | /*! \brief indicate native ROI / force QP ROI to be used. | |
| 845 | */ | |
| 846 | bool bNativeROI; | |
| 847 | /*! \brief Defines dirty ROI settings. | |
| 848 | * | |
| 849 | * Value entries are DirtyROI[0] up DirtyROI ROI[NumROI – 1], inclusively, if NumDirtyROI > 0. And it can be ignored otherwise. | |
| 850 | */ | |
| 851 | CODEC_ROI DirtyROI[CODEC_AVC_NUM_MAX_DIRTY_RECT]; | |
| 852 | ||
| 853 | CODEC_ROI_MAP ROIMapArray[16]; | |
| 854 | ||
| 855 | /*! \brief Specifies skip frames. | |
| 856 | * | |
| 857 | * 0: Encode as normal, no skip. | |
| 858 | * 1: One or more frames were skipped prior to the current frame, encode the current frame as normal. The driver will pass the NumSkipFrames and SizeSkipFrames to BRC for adjustment. | |
| 859 | */ | |
| 860 | uint8_t SkipFrameFlag; | |
| 861 | /*! \brief The number of frames skipped prior to the current frame. | |
| 862 | * | |
| 863 | * Valid when SkipFlag = 1. | |
| 864 | */ | |
| 865 | uint8_t NumSkipFrames; | |
| 866 | /*! \brief Differs in meaning based on value of SkipFrameFlag | |
| 867 | * | |
| 868 | * SkipFrameFlag = 1, the size of the skipped frames in bits. | |
| 869 | * Note: Currently kernel only supports 16 bits for SizeSkipFrames. | |
| 870 | */ | |
| 871 | uint32_t SizeSkipFrames; | |
| 872 | ||
| 873 | /*! \brief Specifies the minimum Qp to be used for BRC. | |
| 874 | * | |
| 875 | * BRCMaxQp and BRCMinQp may be set at a per frame type (I, P, B) granularity. | |
| 876 | * BRCMaxQp and BRCMinQp should be set to zero if Qp control is not desired. | |
| 877 | * If non-zero min/max QP is passed for I-frame, it will be used for I, P and B frames. | |
| 878 | * If non-zero min/max QP is passed for P-frame also, then P and B frame will be updated to this. I-frame remains unchanged. | |
| 879 | * If non-zero min/max QP is passed for B-frame also, then B-frame will be updated to this. I and P frame remains unchanged. | |
| 880 | * If new QP values are passed in between the sequence, then it will be updated for that frame-type and any other frame types that are not explicitly set. Eg. if min/max QP for P-frame was passed separately, and an update for I-frame is received, then only I-frame values are updated. P and B will continue to use old values. But, if P-frame and B-frame were never explicitly set then updating I-frame will also update P and B. | |
| 881 | * If the application wants to keep the current non-zero min/max QP settings, then min/max QP should be set to zero, so the driver will not change previously set values and continue to use them. | |
| 882 | * Min QP is expected to be less than or equal to Max QP. Driver clamps max QP to [1, 51] and min QP to [1, max QP]. Zero QP is not used. | |
| 883 | * Only single PAK pass is supported plus the IPCM pass. Panic mode is disabled. This is because min/maxQP requirement conflicts with the HRD compliancy requirement, so the HRD compliancy restriction is relaxed. | |
| 884 | */ | |
| 885 | uint8_t ucMinimumQP; | |
| 886 | uint8_t ucMaximumQP; //!< Specifies the maximum Qp to be used for BRC. | |
| 887 | ||
| 888 | uint32_t dwZMvThreshold; //!< Used for static frame detection. | |
| 889 | ||
| 890 | /*! \brief Indicates that an HMEOffset will be sent by the application in HMEOffset for each reference. | |
| 891 | * | |
| 892 | * This offset will be added to the co-located (0, 0) location before HME search is performed. This is only valid if HMEOffsetSupport is reported as supported as a capability, else this flag is ignored. | |
| 893 | */ | |
| 894 | bool bEnableHMEOffset; | |
| 895 | /*! \brief Specifies the HME offsets. | |
| 896 | * | |
| 897 | * Curently the supported range is -128 to +127, programmed in 4x downscaled HME precision, not the original size. HMEOffset[i][j] where: | |
| 898 | * \n - i – RefFrameList Index | |
| 899 | * \n - j – 0 = x, 1 = y Coordinates | |
| 900 | * \n So for example, HMEOffset[i] specifies the (x, y) offset corresponding to the ith entry in RefFrameList. | |
| 901 | * Programming Note: The HME offset must be a multiple of 4x4 to align to the 4x4 HME block, so the driver must align the application supplied value. | |
| 902 | */ | |
| 903 | int16_t HMEOffset[16][2][2]; | |
| 904 | ||
| 905 | /*! \brief Specifies Inter MB partition modes that will be disabled. | |
| 906 | * | |
| 907 | * SubMbPartMask is only valid when bEnableSubMbPartMask is true. Bit0~6 indicate inter 16x16, 16x8, 8x16, 8x8, 8x4, 4x8, 4x4. | |
| 908 | */ | |
| 909 | bool bEnableSubMbPartMask; | |
| 910 | uint8_t SubMbPartMask; | |
| 911 | ||
| 912 | /*! \brief Specifies motion search modes that will be used. | |
| 913 | * | |
| 914 | * SubPelMode is only valid when bEnableSubPelMode is true. Following are valid values of SubPelMode: | |
| 915 | * 0:Integer mode searching | |
| 916 | * 1:Half-pel mode searching | |
| 917 | * 2:Reserved | |
| 918 | * 3:Quarter-pel mode searching | |
| 919 | */ | |
| 920 | bool bEnableSubPelMode; | |
| 921 | uint8_t SubPelMode; | |
| 922 | ||
| 923 | /*! \brief Specifies whether extra partition decision refinement is done after the initial partition decision candidate is determined. | |
| 924 | * | |
| 925 | * It has performance tradeoff for better quality. | |
| 926 | * \n - 0 : DEFAULT - Follow driver default settings. | |
| 927 | * \n - 1 : FORCE_ENABLE - Enable this feature totally for all cases. | |
| 928 | * \n - 2 : FORCE_DISABLE - Disable this feature totally for all cases. | |
| 929 | */ | |
| 930 | uint32_t ForceRepartitionCheck; | |
| 931 | ||
| 932 | /*! \brief Specifies force-to-skip for HRD compliance in BRC kernel that will be disabled. | |
| 933 | * | |
| 934 | * bDisableFrameSkip is only valid for P/B frames | |
| 935 | * 0: force-to-skip will be enabled as required in BRC kernel. Default value. | |
| 936 | * 1: force-to-skip will be disabled in BRC kernel. | |
| 937 | */ | |
| 938 | bool bDisableFrameSkip; | |
| 939 | ||
| 940 | /*! \brief Maximum frame size for all frame types in bytes. | |
| 941 | * | |
| 942 | * Applicable for CQP and multi PAK. If dwMaxFrameSize > 0, driver will do multiple PAK and adjust QP | |
| 943 | * (frame level QP + slice_qp_delta) to make the compressed frame size to be less than this value. | |
| 944 | * If dwMaxFrameSize equals 0, driver will not do multiple PAK and do not adjust QP. | |
| 945 | */ | |
| 946 | uint32_t dwMaxFrameSize; | |
| 947 | ||
| 948 | /*! \brief Total pass number for multiple PAK. | |
| 949 | * | |
| 950 | * Valid range is 0 - 4. If dwNumPasses is set to 0, driver will not do multiple PAK and do not adjust | |
| 951 | * QP (frame level QP + slice_qp_delta), otherwise, driver will do multiple times PAK and in each time | |
| 952 | * the QP will be adjust according deltaQp parameters. | |
| 953 | */ | |
| 954 | uint32_t dwNumPasses; | |
| 955 | ||
| 956 | /*! \brief Delta QP array for each PAK pass. | |
| 957 | * | |
| 958 | * This pointer points to an array of deltaQp, the max array size for AVC encoder is 4. The valid range | |
| 959 | * for each deltaQp is 0 - 51. If the value is out of this valid range, driver will return error. | |
| 960 | * Otherwise, driver will adjust QP (frame level QP + slice_qp_delta) by adding this value in each PAK pass. | |
| 961 | */ | |
| 962 | uint8_t *pDeltaQp; | |
| 963 | ||
| 964 | /*! \brief Specifies target frame size in TCBRC mode. | |
| 965 | * | |
| 966 | * If TCBRCSupport == 1, this parameter enables "Transport Controlled BRC mode" and indicates the desired frame size in bytes. | |
| 967 | * - If the value equals 0, the BRC mode defined in RateControlMethod will take control for that certain frame. | |
| 968 | * If TCBRCSupport == 0, this parameter will be ignored and should be set to 0. The BRC mode defined in RateControlMethod will be applied. | |
| 969 | */ | |
| 970 | uint32_t TargetFrameSize; | |
| 971 | ||
| 972 | /*! \brief Indicates if GPU polling based sync is enabled. | |
| 973 | * | |
| 974 | * Applicaiton sets to 1 to enable GPU polling based sync in driver. | |
| 975 | */ | |
| 976 | bool bEnableSync; | |
| 977 | ||
| 978 | /*! \brief Indicates if the current frame is repeat frame. | |
| 979 | * | |
| 980 | * Applicaiton sets to 1 if current frame is repeat frame. | |
| 981 | */ | |
| 982 | bool bRepeatFrame; | |
| 983 | ||
| 984 | /*! \brief Indicates if enable QP adjustment for current frame. | |
| 985 | * | |
| 986 | * Applicaiton sets to 1 to enable QP adjustment for current frame in CQP mode. | |
| 987 | * When QP adjustment is enabled, driver calls MBBRC kernel to adjust per MB QP for perceptual quality in CQP mode. | |
| 988 | */ | |
| 989 | bool bEnableQpAdjustment; | |
| 990 | ||
| 991 | /*! \brief Indicates marker coordinates in raw surface for GPU polling based sync. | |
| 992 | * | |
| 993 | * In unite of bytes. Valid for encoders which report SyncSupport capability as true. | |
| 994 | */ | |
| 995 | uint16_t SyncMarkerX; | |
| 996 | uint16_t SyncMarkerY; | |
| 997 | ||
| 998 | /*! \brief Point to marker value for GPU polling based sync. | |
| 999 | * | |
| 1000 | * Valid for encoders which report SyncSupport capability as true. | |
| 1001 | */ | |
| 1002 | uint8_t *pSyncMarkerValue; | |
| 1003 | ||
| 1004 | /*! \brief Indicates marker value for GPU polling based sync. | |
| 1005 | * | |
| 1006 | * In unit of bytes. Should be larger than or equal to 4. Valid for encoders which report SyncSupport capability as true. | |
| 1007 | */ | |
| 1008 | uint32_t SyncMarkerSize; | |
| 1009 | ||
| 1010 | /*! \brief hierarchical level plus one for pyramid encoding. | |
| 1011 | * | |
| 1012 | * When HierarchLevelPlus1 > 0, HierarchLevelPlus1 – 1 indicates the current frame’s hierarchical level. | |
| 1013 | * And it is for both random access and low delay hierarchical structure. | |
| 1014 | * HierarchLevelPlus1 == 0 can be treated as meaningless. It is defined as a legacy reason for HEVC. | |
| 1015 | */ | |
| 1016 | uint8_t HierarchLevelPlus1; | |
| 1017 | ||
| 1018 | /*! \brief QP modulation strength for BRC | |
| 1019 | * | |
| 1020 | * Suggestion of the strength of applying Qp delta for the frame specified when Qp modulation is enabled (HierarchicalFlag == 1). | |
| 1021 | * This is a relative number. BRC could use it to infer final delta Qp values for hierarchical frames in mini Gop structure. | |
| 1022 | * Default value 0 means no suggestion for Qp modulation | |
| 1023 | */ | |
| 1024 | uint8_t QpModulationStrength; | |
| 1025 | ||
| 1026 | } CODEC_AVC_ENCODE_PIC_PARAMS, *PCODEC_AVC_ENCODE_PIC_PARAMS; | |
| 1027 | ||
| 1028 | /*! \brief Slice-level parameters of a compressed picture for AVC encoding. | |
| 1029 | */ | |
| 1030 | typedef struct _CODEC_AVC_ENCODE_SLICE_PARAMS | |
| 1031 | { | |
| 1032 | /*! \brief Specifies the number of macroblocks for this slice. | |
| 1033 | * | |
| 1034 | * Note the slice height restriction in picture parameter structure. | |
| 1035 | */ | |
| 1036 | uint32_t NumMbsForSlice; | |
| 1037 | /*! \brief Specifies the reference picture lists 0 and 1 | |
| 1038 | * | |
| 1039 | * Contains field/frame information concerning the reference in PicFlags. RefPicList[i][j]: | |
| 1040 | * \n - i: the reference picture list (0 or 1) | |
| 1041 | * \n - j: if the PicFlags are not PICTURE_INVALID, the index variable j is a reference to entry j in teh reference picture list. | |
| 1042 | */ | |
| 1043 | CODEC_PICTURE RefPicList[CODEC_AVC_NUM_REF_LISTS][CODEC_MAX_NUM_REF_FIELD]; | |
| 1044 | /*! \brief Specifies the weights and offsets used for explicit mode weighted prediction. | |
| 1045 | * | |
| 1046 | * Weigths[i][j][k][m]: | |
| 1047 | * \n - i: the reference picture list (0 or 1) | |
| 1048 | * \n - j: reference to entry j in RefPicList (has range [0...31]) | |
| 1049 | * \n - k: the YUV component (0 = luma, 1 = Cb chroma, 2 = Cr chroma) | |
| 1050 | * \n - m: the weight or offset used in the weighted prediction process (0 = weight, 1 = offset) | |
| 1051 | */ | |
| 1052 | int16_t Weights[2][32][3][2]; | |
| 1053 | ||
| 1054 | uint32_t first_mb_in_slice; //!< Same as AVC syntax element. | |
| 1055 | uint8_t slice_type; //!< Same as AVC syntax element. | |
| 1056 | uint8_t pic_parameter_set_id; //!< Same as AVC syntax element. | |
| 1057 | uint16_t direct_spatial_mv_pred_flag : 1; //!< Same as AVC syntax element. | |
| 1058 | uint16_t num_ref_idx_active_override_flag : 1; //!< Same as AVC syntax element. | |
| 1059 | uint16_t long_term_reference_flag : 1; //!< Same as AVC syntax element. | |
| 1060 | uint16_t : 13; | |
| 1061 | uint16_t idr_pic_id; //!< Same as AVC syntax element. | |
| 1062 | uint16_t pic_order_cnt_lsb; //!< Same as AVC syntax element. | |
| 1063 | int32_t delta_pic_order_cnt_bottom; //!< Same as AVC syntax element. | |
| 1064 | int32_t delta_pic_order_cnt[2]; //!< Same as AVC syntax element. | |
| 1065 | uint8_t num_ref_idx_l0_active_minus1; //!< Same as AVC syntax element. | |
| 1066 | uint8_t num_ref_idx_l1_active_minus1; //!< Same as AVC syntax element. | |
| 1067 | uint8_t num_ref_idx_l0_active_minus1_from_DDI; | |
| 1068 | uint8_t num_ref_idx_l1_active_minus1_from_DDI; | |
| 1069 | uint8_t luma_log2_weight_denom; //!< Same as AVC syntax element. | |
| 1070 | uint8_t chroma_log2_weight_denom; //!< Same as AVC syntax element. | |
| 1071 | uint8_t cabac_init_idc; //!< Same as AVC syntax element. | |
| 1072 | char slice_qp_delta; //!< Same as AVC syntax element. | |
| 1073 | uint8_t disable_deblocking_filter_idc; //!< Same as AVC syntax element. | |
| 1074 | char slice_alpha_c0_offset_div2; //!< Same as AVC syntax element. | |
| 1075 | char slice_beta_offset_div2; //!< Same as AVC syntax element. | |
| 1076 | uint32_t slice_id; //!< Same as AVC syntax element. | |
| 1077 | /*! \brief Indicates that the weighting factors for the luma component are present. | |
| 1078 | * | |
| 1079 | * luma_weight_flag[i] is interpreted as corresponding to L0 when i=0 and L1 when i=1. Each bit n of luma_weight_flag[i] corresponds to the nth entry in reference list i. The framework must obey the caps the driver reported in MaxNum_WeightedPredL0/L1. | |
| 1080 | */ | |
| 1081 | uint32_t luma_weight_flag[2]; | |
| 1082 | /*! \brief Indicates that the weighting factors for the chroma component are present. | |
| 1083 | * | |
| 1084 | * chroma_weight_flag[i] is interpreted as corresponding to L0 when i=0 and L1 when i=1. Each bit n of chroma_weight_flag[i] corresponds to the nth entry in reference list i. The framework must obey the caps the driver reported in MaxNum_WeightedPredL0/L1. | |
| 1085 | */ | |
| 1086 | uint32_t chroma_weight_flag[2]; | |
| 1087 | ||
| 1088 | CODEC_PIC_REORDER PicOrder[2][32]; //!< Set by the driver | |
| 1089 | ||
| 1090 | uint8_t colour_plane_id; //!< Same as AVC syntax element. | |
| 1091 | uint32_t frame_num; //!< Same as AVC syntax element. | |
| 1092 | bool field_pic_flag; //!< Same as AVC syntax element. | |
| 1093 | bool bottom_field_flag; //!< Same as AVC syntax element. | |
| 1094 | uint8_t redundant_pic_cnt; //!< Same as AVC syntax element. | |
| 1095 | char sp_for_switch_flag; //!< Same as AVC syntax element. | |
| 1096 | char slice_qs_delta; //!< Same as AVC syntax element. | |
| 1097 | uint8_t ref_pic_list_reordering_flag_l0 : 1; //!< Same as AVC syntax element. | |
| 1098 | uint8_t ref_pic_list_reordering_flag_l1 : 1; //!< Same as AVC syntax element. | |
| 1099 | uint8_t no_output_of_prior_pics_flag : 1; //!< Same as AVC syntax element. | |
| 1100 | uint8_t adaptive_ref_pic_marking_mode_flag : 1; //!< Same as AVC syntax element. | |
| 1101 | uint8_t : 3; | |
| 1102 | uint32_t MaxFrameNum; //!< Set by the driver: 1 << (pSeqParams[pPicParams->seq_parameter_set_id].log2_max_frame_num_minus4 + 4); | |
| 1103 | uint8_t NumReorder; //!< Set by the driver | |
| 1104 | } CODEC_AVC_ENCODE_SLICE_PARAMS, *PCODEC_AVC_ENCODE_SLICE_PARAMS; | |
| 1105 | ||
| 1106 | // H.264 Inverse Quantization Weight Scale | |
| 1107 | typedef struct _CODEC_AVC_ENCODE_IQ_WEIGTHSCALE_LISTS | |
| 1108 | { | |
| 1109 | uint8_t WeightScale4x4[6][16]; | |
| 1110 | uint8_t WeightScale8x8[2][64]; | |
| 1111 | } CODEC_AVC_ENCODE_IQ_WEIGTHSCALE_LISTS, *PCODEC_AVC_ENCODE_IQ_WEIGTHSCALE_LISTS; | |
| 1112 | ||
| 1113 | // used for PAFF case, 0: frame, 1: tff field, 2: invalid, 3: bff field | |
| 1114 | typedef enum _CODEC_AVC_PIC_CODING_TYPE_VALUE | |
| 1115 | { | |
| 1116 | CODEC_AVC_PIC_CODING_TYPE_FRAME = 0x0, | |
| 1117 | CODEC_AVC_PIC_CODING_TYPE_TFF_FIELD = 0x1, | |
| 1118 | CODEC_AVC_PIC_CODING_TYPE_INVALID = 0x2, | |
| 1119 | CODEC_AVC_PIC_CODING_TYPE_BFF_FIELD = 0x3 | |
| 1120 | } CODEC_AVC_PIC_CODING_TYPE_VALUE; | |
| 1121 | ||
| 1122 | //! | |
| 1123 | //! \struct CodecEncodeAvcFeiPicParams | |
| 1124 | //! \brief Codec encode AVC FEI pic params | |
| 1125 | //! | |
| 1126 | struct CodecEncodeAvcFeiPicParams | |
| 1127 | { | |
| 1128 | MOS_RESOURCE resMBCtrl; // input MB control buffer | |
| 1129 | MOS_RESOURCE resMVData; // ENC MV output buffer or PAK MV input buffer | |
| 1130 | MOS_RESOURCE resMBCode; // ENC MBCode output buffer or PAK MBCode input buffer | |
| 1131 | MOS_RESOURCE resMVPredictor; // input MV predictor surface | |
| 1132 | MOS_RESOURCE resMBQp; // input QP per MB surface | |
| 1133 | MOS_RESOURCE resDistortion; // ENC or ENC_PAK Distortion output surface | |
| 1134 | uint32_t NumMVPredictorsL0; | |
| 1135 | uint32_t NumMVPredictorsL1; | |
| 1136 | ||
| 1137 | bool MbCodeMvEnable; | |
| 1138 | bool DistortionEnable; | |
| 1139 | ||
| 1140 | /** \brief control parameters */ | |
| 1141 | uint32_t SearchPath; | |
| 1142 | uint32_t LenSP; | |
| 1143 | ||
| 1144 | uint32_t SubMBPartMask; | |
| 1145 | uint32_t IntraPartMask; | |
| 1146 | bool MultiPredL0; | |
| 1147 | bool MultiPredL1; | |
| 1148 | uint32_t SubPelMode; | |
| 1149 | uint32_t InterSAD; | |
| 1150 | uint32_t IntraSAD; | |
| 1151 | uint32_t DistortionType; | |
| 1152 | bool RepartitionCheckEnable; | |
| 1153 | bool AdaptiveSearch; | |
| 1154 | bool MVPredictorEnable; | |
| 1155 | bool bMBQp; | |
| 1156 | bool bPerMBInput; | |
| 1157 | bool bMBSizeCtrl; | |
| 1158 | uint32_t RefWidth; | |
| 1159 | uint32_t RefHeight; | |
| 1160 | uint32_t SearchWindow; | |
| 1161 | ||
| 1162 | //add for mutlple pass pak | |
| 1163 | uint32_t dwMaxFrameSize; | |
| 1164 | uint32_t dwNumPasses; //number of QPs | |
| 1165 | uint8_t *pDeltaQp; //list of detla QPs | |
| 1166 | }; | |
| 1167 | #endif // __CODEC_DEF_ENCODE_AVC_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_encode_jpeg.h | |
| 23 | //! \brief Defines encode JPEG types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to JPEG encode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | ||
| 27 | #ifndef __CODEC_DEF_ENCODE_JPEG_H__ | |
| 28 | #define __CODEC_DEF_ENCODE_JPEG_H__ | |
| 29 | ||
| 30 | #include "codec_def_common_jpeg.h" | |
| 31 | #include "codec_def_common_encode.h" | |
| 32 | ||
| 33 | #define JPEG_MAX_NUM_QUANT_TABLE_INDEX 3 // Max 3 quant tables are allowed for encode | |
| 34 | #define JPEG_MAX_QUANT_TABLE 3 // MAx Number of Quantization tables that can be sent by the application | |
| 35 | #define JPEG_NUM_ENCODE_HUFF_BUFF 4 // Total number of Huffman tables that app can send for JPEG encode (2AC and 2DC tables allowed per frame) | |
| 36 | ||
| 37 | // Max supported resolution for JPEG encode is 16K X 16K | |
| 38 | #define ENCODE_JPEG_MAX_PIC_WIDTH 16384 | |
| 39 | #define ENCODE_JPEG_MAX_PIC_HEIGHT 16384 | |
| 40 | ||
| 41 | #define JPEG_MAX_NUM_HUFF_TABLES 2 // Max 2 sets of Huffman Tables are allowed (2AC and 2 DC) | |
| 42 | ||
| 43 | //! | |
| 44 | //! \struct CodecEncodeJpegQuantTable | |
| 45 | //! \brief Define JPEG Quant Table | |
| 46 | //! | |
| 47 | struct CodecEncodeJpegQuantTable | |
| 48 | { | |
| 49 | struct | |
| 50 | { | |
| 51 | uint32_t m_tableID; //!< Table ID | |
| 52 | uint32_t m_precision; //!< Precision | |
| 53 | uint16_t m_qm[JPEG_NUM_QUANTMATRIX]; //!< Quant Matrix | |
| 54 | } m_quantTable[JPEG_MAX_NUM_QUANT_TABLE_INDEX]; //!< Quant table array | |
| 55 | }; | |
| 56 | ||
| 57 | //! | |
| 58 | //! \struct CodecEncodeJpegHuffData | |
| 59 | //! \brief Define Huffman data for JPEG encode | |
| 60 | //! | |
| 61 | struct CodecEncodeJpegHuffData | |
| 62 | { | |
| 63 | uint32_t m_tableClass; //!< table class | |
| 64 | uint32_t m_tableID; //!< table ID | |
| 65 | uint8_t m_bits[JPEG_NUM_HUFF_TABLE_AC_BITS]; //!< AC bits | |
| 66 | uint8_t m_huffVal[JPEG_NUM_HUFF_TABLE_AC_HUFFVAL]; //!< AC Huffman value | |
| 67 | }; | |
| 68 | ||
| 69 | //! | |
| 70 | //! \struct CodecEncodeJpegHuffmanDataArray | |
| 71 | //! \brief Define Huffman data array for JPEG encode | |
| 72 | //! | |
| 73 | struct CodecEncodeJpegHuffmanDataArray | |
| 74 | { | |
| 75 | //!< huffmanData[0] --> Table for DC component of luma | |
| 76 | //!< huffmanData[1] --> Table for AC component of luma | |
| 77 | //!< huffmanData[2] --> Table for DC component of chroma | |
| 78 | //!< huffmanData[3] --> Table for AC component of chroma | |
| 79 | CodecEncodeJpegHuffData m_huffmanData[JPEG_NUM_ENCODE_HUFF_BUFF]; | |
| 80 | }; | |
| 81 | ||
| 82 | //! | |
| 83 | //! \enum CodecEncodeJpegInputSurfaceFormat | |
| 84 | //! \brief matches up with InputSurfaceFormats | |
| 85 | //! (converted from MOS format in ConvertMediaFormatToInputSurfaceFormat()) | |
| 86 | //! May want to unify enums instead of casting | |
| 87 | //! | |
| 88 | enum CodecEncodeJpegInputSurfaceFormat | |
| 89 | { | |
| 90 | codechalJpegNV12 = 1, //!< NV12 surface format | |
| 91 | codechalJpegUYVY = 2, //!< UYVY surface format | |
| 92 | codechalJpegYUY2 = 3, //!< YUY2 surface format | |
| 93 | codechalJpegY8 = 4, //!< Y8 surface format | |
| 94 | codechalJpegRGB = 5 //!< RGB surface format | |
| 95 | }; | |
| 96 | ||
| 97 | //! | |
| 98 | //! \struct CodecEncodeJpegPictureParams | |
| 99 | //! \brief Picture Parameter Set for JPEG Encode | |
| 100 | //! | |
| 101 | struct CodecEncodeJpegPictureParams | |
| 102 | { | |
| 103 | uint32_t m_profile : 2; //!< Profile. 0 -Baseline, 1 - Extended, 2 - Lossless, 3 - Hierarchical | |
| 104 | uint32_t m_progressive : 1; //!< Progressive flag. 1- Progressive, 0 - Sequential | |
| 105 | uint32_t m_huffman : 1; //!< Huffman flag. 1 - Huffman , 0 - Arithmetic | |
| 106 | uint32_t m_interleaved : 1; //!< Interleaved flag. 1 - Interleaved, 0 - NonInterleaved | |
| 107 | uint32_t m_differential : 1; //!< Differential flag. 1 - Differential, 0 - NonDifferential | |
| 108 | ||
| 109 | uint32_t m_picWidth; //!< Picture Width | |
| 110 | uint32_t m_picHeight; //!< Picture Height | |
| 111 | ||
| 112 | uint32_t m_inputSurfaceFormat; //!< Input surface format | |
| 113 | uint32_t m_sampleBitDepth; //!< Sample bit depth | |
| 114 | ||
| 115 | uint32_t m_numComponent; //!< Component Number | |
| 116 | uint8_t m_componentID[4]; //!< Component ID | |
| 117 | uint8_t m_quantTableSelector[4]; //!< Quant table selector | |
| 118 | ||
| 119 | uint32_t m_quality; //!< Quality | |
| 120 | ||
| 121 | uint32_t m_numScan; //!< Scan number | |
| 122 | uint32_t m_numQuantTable; //!< Quant table number | |
| 123 | uint32_t m_numCodingTable; //!< Coding table number | |
| 124 | ||
| 125 | uint32_t m_statusReportFeedbackNumber; //!< Status report feedback number | |
| 126 | ||
| 127 | }; | |
| 128 | ||
| 129 | //! | |
| 130 | //! \struct CodecEncodeJpegScanHeader | |
| 131 | //! \brief Scan Header structure for JPEG Encode | |
| 132 | //! | |
| 133 | struct CodecEncodeJpegScanHeader | |
| 134 | { | |
| 135 | uint32_t m_restartInterval; //!< Restart Interval | |
| 136 | ||
| 137 | uint32_t m_numComponent; //!< Component number | |
| 138 | uint8_t m_componentSelector[4]; //!< Component selector | |
| 139 | uint8_t m_dcCodingTblSelector[4]; //!< DC coding table selector | |
| 140 | uint8_t m_acCodingTblSelector[4]; //!< AC coding table selector | |
| 141 | ||
| 142 | }; | |
| 143 | ||
| 144 | // matrix required to read in the quantization matrix | |
| 145 | static const uint8_t jpeg_qm_scan_8x8[64] = | |
| 146 | { | |
| 147 | // Zig-Zag scan pattern | |
| 148 | 0, 1, 8, 16, 9, 2, 3, 10, | |
| 149 | 17, 24, 32, 25, 18, 11, 4, 5, | |
| 150 | 12, 19, 26, 33, 40, 48, 41, 34, | |
| 151 | 27, 20, 13, 6, 7, 14, 21, 28, | |
| 152 | 35, 42, 49, 56, 57, 50, 43, 36, | |
| 153 | 29, 22, 15, 23, 30, 37, 44, 51, | |
| 154 | 58, 59, 52, 45, 38, 31, 39, 46, | |
| 155 | 53, 60, 61, 54, 47, 55, 62, 63 | |
| 156 | }; | |
| 157 | ||
| 158 | #endif // __CODEC_DEF_ENCODE_JPEG_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_encode_mpeg2.h | |
| 23 | //! \brief Defines encode MPEG2 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to MPEG2 encode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | ||
| 27 | #ifndef __CODEC_DEF_ENCODE_MPEG2_H__ | |
| 28 | #define __CODEC_DEF_ENCODE_MPEG2_H__ | |
| 29 | ||
| 30 | #include "codec_def_common_encode.h" | |
| 31 | #include "codec_def_common_mpeg2.h" | |
| 32 | ||
| 33 | #define CODEC_ENCODE_MPEG2_BRC_PIC_HEADER_SURFACE_SIZE 1024 | |
| 34 | #define CODEC_ENCODE_MPEG2_VBV_BUFFER_SIZE_UNITS (16 * 1024) //!< 16 K bits | |
| 35 | #define CODEC_ENCODE_MPEG2_MAX_NAL_TYPE 0x1f | |
| 36 | ||
| 37 | //! | |
| 38 | //! \enum CodecEncodeMpeg2ExtensionStartCode | |
| 39 | //! \brief Codec encode MPEG2 extension start code | |
| 40 | //! | |
| 41 | enum CodecEncodeMpeg2ExtensionStartCode | |
| 42 | { | |
| 43 | // 0x00 - Reserved | |
| 44 | Mpeg2sequenceExtension = 0x01, | |
| 45 | Mpeg2sequenceDisplayExtension = 0x02, | |
| 46 | Mpeg2quantMatrixExtension = 0x03, | |
| 47 | Mpeg2copyrightExtension = 0x04, | |
| 48 | Mpeg2sequnceScalableExtension = 0x05, | |
| 49 | // 0x06 - Reserved | |
| 50 | Mpeg2pictureDisplayExtension = 0x07, | |
| 51 | Mpeg2pictureCodingExtension = 0x08, | |
| 52 | Mpeg2pictureSpatialScalableExtension = 0x09, | |
| 53 | Mpeg2pictureTemporalScalableExtension = 0x0A | |
| 54 | // 0x0B .. 0x0F - Reserved | |
| 55 | } ; | |
| 56 | ||
| 57 | //! | |
| 58 | //! \struct CodecEncodeMpeg2SequenceParams | |
| 59 | //! \brief MPEG2 Sequence Parameter Set | |
| 60 | //! | |
| 61 | struct CodecEncodeMpeg2SequenceParams | |
| 62 | { | |
| 63 | uint16_t m_frameWidth; //!< Width of picture in unit of pixels | |
| 64 | uint16_t m_frameHeight; //!< Height of picture in unit pixels | |
| 65 | uint8_t m_profile; //!< Profile | |
| 66 | uint8_t m_level; //!< Level | |
| 67 | uint8_t m_chromaFormat; //!< Color sampling formats | |
| 68 | uint8_t m_targetUsage; //!< Target usage number, indicates trade-offs between quality and speed | |
| 69 | ||
| 70 | // ENC + PAK related parameters | |
| 71 | union | |
| 72 | { | |
| 73 | uint16_t m_aratioFrate; //!< Aspect ratio and frame rate | |
| 74 | struct | |
| 75 | { | |
| 76 | uint16_t m_aspectRatio : 4; //!< Aspect ratio | |
| 77 | uint16_t m_frameRateCode : 4; //!< Frame rate Code | |
| 78 | uint16_t m_frameRateExtN : 3; //!< Frame rate extend numerator | |
| 79 | uint16_t m_frameRateExtD : 5; //!< Frame rate extend denominator | |
| 80 | }; | |
| 81 | }; | |
| 82 | ||
| 83 | uint32_t m_bitrate; //!< Bit rate bits per second | |
| 84 | uint32_t m_vbvBufferSize; //!< VBV buffer size in bits | |
| 85 | ||
| 86 | uint8_t m_progressiveSequence : 1; //!< Indicate progressive sequence | |
| 87 | uint8_t m_lowDelay : 1; //!< Indicate low delay | |
| 88 | uint8_t m_resetBRC : 1; //!< Indicate if a BRC reset is desired to set a new bit rate or frame rate | |
| 89 | uint8_t m_noAcceleratorSPSInsertion : 1; //!< Indicates if current SPS is just a BRC parameter update, not a SPS change to be inserted into the bitstream. | |
| 90 | uint8_t m_forcePanicModeControl : 1; // Force to control the panic mode through DDI. | |
| 91 | uint8_t m_panicModeDisable : 1; // Disable the panic mode | |
| 92 | uint8_t m_reserved0 : 2; //!< Reserved | |
| 93 | uint8_t m_rateControlMethod; //!< rate control method, CBR = 1, VBR = 2, AVBR = 4, CQP = 3 | |
| 94 | uint16_t m_reserved1; //!< Reserved | |
| 95 | uint32_t m_maxBitRate; //!< Maximum bit rate, bits/sec | |
| 96 | uint32_t m_minBitRate; //!< Minimum bit rate, bits/sec | |
| 97 | uint32_t m_userMaxFrameSize; //!< Maximum frame size by user | |
| 98 | uint32_t m_initVBVBufferFullnessInBit; //!< Initial VBV buffer fullness size in bits | |
| 99 | uint16_t m_reserved2; //!< Reserved | |
| 100 | uint16_t m_reserved3; //!< Reserved | |
| 101 | } ; | |
| 102 | ||
| 103 | //! | |
| 104 | //! \struct CodecEncodeMpeg2PictureParams | |
| 105 | //! \brief MPEG2 Picture Parameter Set | |
| 106 | //! | |
| 107 | struct CodecEncodeMpeg2PictureParams | |
| 108 | { | |
| 109 | CODEC_PICTURE m_currOriginalPic; //!< The current uncompressed original frame surface for encoding | |
| 110 | CODEC_PICTURE m_currReconstructedPic; //!< The uncompressed frame surface for the current reconstructed picture. | |
| 111 | uint8_t m_pictureCodingType; //!< Coding Type | |
| 112 | uint8_t m_fieldCodingFlag : 1; //!< Indication of field mode coding when set to 1. | |
| 113 | uint8_t m_fieldFrameCodingFlag : 1; //!< Indication interlaced frame coding | |
| 114 | uint8_t m_reserved0 : 2; //!< Reserved | |
| 115 | uint8_t m_interleavedFieldBFF : 1; //!< Indication of input picture layout has top field and bottom field interleaved together | |
| 116 | //!< with bottom field first when set to 1; otherwise (when set to 0) it is | |
| 117 | //!< interleaved with top field first. | |
| 118 | uint8_t m_progressiveField : 1; //!< Indication of input picture layout has only one field picture (half of a frame) stored progressively | |
| 119 | uint8_t m_reserved1 : 2; //!< Reserved | |
| 120 | ||
| 121 | uint8_t m_numSlice; //!< Number of slices per frame; number of slices per field in field coding | |
| 122 | uint8_t m_picBackwardPrediction; //!< Indicates whether any macroblocks of the current picture might include backward prediction | |
| 123 | uint8_t m_bidirectionalAveragingMode; //!< Indicates the rounding method for combining prediction planes in bidirectional motion compensation | |
| 124 | uint8_t m_pic4MVallowed; //!< Picture 4 MV allowed | |
| 125 | CODEC_PICTURE m_refFrameList[2]; //!< List of reference frame buffers | |
| 126 | bool m_useRawPicForRef; //!< Setting to 1 may improve performance at the cost of image quality | |
| 127 | uint32_t m_statusReportFeedbackNumber; //!< The status report feedback data | |
| 128 | ||
| 129 | uint32_t m_alternateScan : 1; //!< Indicate the Inverse Scan method | |
| 130 | uint32_t m_intraVlcFormat : 1; //!< Intra VLC format | |
| 131 | uint32_t m_qscaleType : 1; //!< Quantizer Scale Type | |
| 132 | uint32_t m_concealmentMotionVectors : 1; //!< Indicates if the concealment motion vectors are coded in intra macroblocks | |
| 133 | uint32_t m_framePredFrameDCT : 1; //!< Frame Prediction Frame DCT | |
| 134 | uint32_t m_disableMismatchControl : 1; //!< Disable mismatch control | |
| 135 | uint32_t m_intraDCprecision : 2; //!< Intra DC Precision | |
| 136 | uint32_t m_fcode00 : 4; //!< Used for forward horizontal motion vector prediction | |
| 137 | uint32_t m_fcode01 : 4; //!< Used for forward vertical motion vector prediction | |
| 138 | uint32_t m_fcode10 : 4; //!< Used for backward horizontal motion vector prediction | |
| 139 | uint32_t m_fcode11 : 4; //!< Used for backward vertical motion vector prediction | |
| 140 | uint32_t m_reserved2 : 8; //!< Reserved | |
| 141 | ||
| 142 | // ENC + PAK related parameters | |
| 143 | bool m_lastPicInStream; //!< Indicate the last picture of the stream | |
| 144 | bool m_newGop; //!< Indicates that a new GOP will start with this picture | |
| 145 | ||
| 146 | uint16_t m_gopPicSize; //!< Number of pictures within the current GOP | |
| 147 | uint8_t m_gopRefDist; //!< Distance between I- or P (or GPB) - key frames | |
| 148 | uint8_t m_gopOptFlag : 2; //!< Indicate the additional flags for the GOP specification | |
| 149 | uint8_t m_reserved3 : 6; //!< Reserved | |
| 150 | ||
| 151 | uint32_t m_timeCode : 25;//!< Time code | |
| 152 | uint32_t m_reserved4 : 7; //!< Reserved | |
| 153 | ||
| 154 | uint16_t m_temporalReference : 10;//!< Temporal reference | |
| 155 | uint16_t m_reserved5 : 6; //!< Reserved | |
| 156 | ||
| 157 | uint16_t m_vbvDelay; | |
| 158 | ||
| 159 | uint32_t m_repeatFirstField : 1; //!< Repeat first field | |
| 160 | uint32_t m_compositeDisplayFlag : 1; //!< Composite display flag | |
| 161 | uint32_t m_vaxis : 1; //!< Vaxis | |
| 162 | uint32_t m_fieldSequence : 3; //!< Field sequence | |
| 163 | uint32_t m_subCarrier : 1; //!< Sub carrier | |
| 164 | uint32_t m_burstAmplitude : 7; //!< Burst Amplitude | |
| 165 | uint32_t m_subCarrierPhase : 8; //!< Sub carrier phase | |
| 166 | uint32_t m_reserved6 : 10;//!< Reserved | |
| 167 | ||
| 168 | // Parameters for Skip Frames | |
| 169 | uint8_t m_skipFrameFlag; //!< Skip frame flag | |
| 170 | uint8_t m_numSkipFrames; //!< only reserved for BRC case | |
| 171 | uint32_t m_sizeSkipFrames; //!< only reserved for BRC case | |
| 172 | }; | |
| 173 | ||
| 174 | //! | |
| 175 | //! \struct CodecEncodeMpeg2SliceParmas | |
| 176 | //! \brief MPEG2 Slice Parameters | |
| 177 | //! | |
| 178 | struct CodecEncodeMpeg2SliceParmas | |
| 179 | { | |
| 180 | uint16_t m_numMbsForSlice; //!< Number of macroblocks per slice | |
| 181 | uint16_t m_firstMbX; //!< Specifies the horizontal position of the first macroblock of the slice expressed in units of macroblocks | |
| 182 | uint16_t m_firstMbY; //!< Specifies the vertical position of the first macroblock of the slice expressed in units of macroblocks | |
| 183 | uint16_t m_intraSlice; //!< Indicates slices coded as Intra Slice | |
| 184 | uint8_t m_quantiserScaleCode; //!< Quantier scale code | |
| 185 | }; | |
| 186 | ||
| 187 | //! | |
| 188 | //! \struct CodecEncodeMpeg2VuiParams | |
| 189 | //! \brief MPEG2 VUI Parameters | |
| 190 | //! | |
| 191 | struct CodecEncodeMpeg2VuiParams | |
| 192 | { | |
| 193 | uint32_t m_videoFormat : 3; //!< Indicate the representation of the pictures | |
| 194 | uint32_t m_reserved0 : 4; //!< Reserved | |
| 195 | uint32_t m_colourDescription : 1; //!< Indicate the colour description is presented | |
| 196 | uint32_t m_colourPrimaries : 8; //!< The chromaticity coordinates of the source primaries | |
| 197 | uint32_t m_transferCharacteristics : 8; //!< The opto-electronic transfer characteristic of the source picture | |
| 198 | uint32_t m_matrixCoefficients : 8; //!< The matrix coefficients used in deriving luminance and chrominance signals | |
| 199 | ||
| 200 | uint32_t m_displayHorizontalSize : 14;//!< The horizontal size of the display active region | |
| 201 | uint32_t m_reserved1 : 2; //!< Reserved | |
| 202 | uint32_t m_displayVerticalSize : 14;//!< The vertical size of the display active region | |
| 203 | uint32_t m_reserved2 : 2; //!< Reserved | |
| 204 | }; | |
| 205 | ||
| 206 | //! | |
| 207 | //! \struct CodecEncodeMpeg2QmatixParams | |
| 208 | //! \brief MPEG2 QMATRIX Parameters | |
| 209 | //! | |
| 210 | struct CodecEncodeMpeg2QmatixParams | |
| 211 | { | |
| 212 | uint8_t m_newQmatrix[4]; //!< 0 - intra Y, 1 - inter Y, 2 - intra chroma, 3 - inter chroma | |
| 213 | uint16_t m_qmatrix[4][64]; //!< Quantiser matrix | |
| 214 | }; | |
| 215 | ||
| 216 | //! | |
| 217 | //! \struct CodecEncodeMpeg2UserDataList | |
| 218 | //! \brief Linked List for MPEG-2 User Data | |
| 219 | //! User data may be provided in several pieces. | |
| 220 | //! So a linked list is implemented to keep track of them. | |
| 221 | //! | |
| 222 | struct CodecEncodeMpeg2UserDataList | |
| 223 | { | |
| 224 | void *m_userData; | |
| 225 | uint32_t m_userDataSize; | |
| 226 | CodecEncodeMpeg2UserDataList *m_nextItem; | |
| 227 | }; | |
| 228 | ||
| 229 | #endif // __CODEC_DEF_ENCODE_MPEG2_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017-2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_encode_vp9.h | |
| 23 | //! \brief Defines encode VP9 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to VP9 encode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_ENCODE_VP9_H__ | |
| 27 | #define __CODEC_DEF_ENCODE_VP9_H__ | |
| 28 | ||
| 29 | #include "codec_def_common_encode.h" | |
| 30 | ||
| 31 | #define CODECHAL_ENCODE_VP9_MAX_NUM_TEMPORAL_LAYERS 8 | |
| 32 | #define ENCODE_VP9_NUM_MAX_L0_REF 3 | |
| 33 | ||
| 34 | typedef enum | |
| 35 | { | |
| 36 | VP9_ENCODED_CHROMA_FORMAT_YUV420 = 0, | |
| 37 | VP9_ENCODED_CHROMA_FORMAT_YUV422 = 1, | |
| 38 | VP9_ENCODED_CHROMA_FORMAT_YUV444 = 2 | |
| 39 | } VP9_ENCODED_CHROMA_FORMAT; | |
| 40 | ||
| 41 | typedef enum | |
| 42 | { | |
| 43 | VP9_ENCODED_BIT_DEPTH_8 = 0, | |
| 44 | VP9_ENCODED_BIT_DEPTH_10 = 1, | |
| 45 | VP9_ENCODED_BIT_DEPTH_12 = 2 | |
| 46 | } VP9_ENCODED_BIT_DEPTH; | |
| 47 | ||
| 48 | typedef struct _CODEC_VP9_ENCODE_SEG_PARAMS | |
| 49 | { | |
| 50 | union | |
| 51 | { | |
| 52 | struct | |
| 53 | { | |
| 54 | uint8_t SegmentReferenceEnabled : 1; | |
| 55 | uint8_t SegmentReference : 2; | |
| 56 | uint8_t SegmentSkipped : 1; | |
| 57 | uint8_t ReservedField3 : 4; | |
| 58 | } fields; | |
| 59 | uint8_t value; | |
| 60 | ||
| 61 | } SegmentFlags; | |
| 62 | ||
| 63 | char SegmentLFLevelDelta; | |
| 64 | int16_t SegmentQIndexDelta; | |
| 65 | ||
| 66 | } CODEC_VP9_ENCODE_SEG_PARAMS, *PCODEC_VP9_ENCODE_SEG_PARAMS; | |
| 67 | ||
| 68 | typedef struct _CODEC_VP9_ENCODE_SEGMENT_PARAMS | |
| 69 | { | |
| 70 | CODEC_VP9_ENCODE_SEG_PARAMS SegData[8]; | |
| 71 | ||
| 72 | } CODEC_VP9_ENCODE_SEGMENT_PARAMS, *PCODEC_VP9_ENCODE_SEGMENT_PARAMS; | |
| 73 | ||
| 74 | typedef struct _CODEC_VP9_ENCODE_SEQUENCE_PARAMS | |
| 75 | { | |
| 76 | uint16_t wMaxFrameWidth; | |
| 77 | uint16_t wMaxFrameHeight; | |
| 78 | uint16_t GopPicSize; | |
| 79 | uint8_t TargetUsage; | |
| 80 | uint8_t RateControlMethod; | |
| 81 | uint32_t TargetBitRate[CODECHAL_ENCODE_VP9_MAX_NUM_TEMPORAL_LAYERS]; | |
| 82 | uint32_t MaxBitRate; | |
| 83 | uint32_t MinBitRate; | |
| 84 | uint32_t InitVBVBufferFullnessInBit; | |
| 85 | uint32_t VBVBufferSizeInBit; | |
| 86 | uint32_t OptimalVBVBufferLevelInBit; | |
| 87 | uint32_t UpperVBVBufferLevelThresholdInBit; | |
| 88 | uint32_t LowerVBVBufferLevelThresholdInBit; | |
| 89 | ||
| 90 | union | |
| 91 | { | |
| 92 | struct | |
| 93 | { | |
| 94 | uint32_t bResetBRC : 1; | |
| 95 | uint32_t bNoFrameHeaderInsertion : 1; | |
| 96 | uint32_t bUseRawReconRef : 1; | |
| 97 | uint32_t MBBRC : 4; // This is not to be set for VP9 VDEnc (G10+), this is removed from DDI, only here to support legacy KBL DP | |
| 98 | uint32_t EnableDynamicScaling : 1; | |
| 99 | uint32_t SourceFormat : 2; | |
| 100 | uint32_t SourceBitDepth : 2; | |
| 101 | uint32_t EncodedFormat : 2; | |
| 102 | uint32_t EncodedBitDepth : 2; | |
| 103 | uint32_t DisplayFormatSwizzle : 1; | |
| 104 | uint32_t bReserved : 15; | |
| 105 | } fields; | |
| 106 | ||
| 107 | uint32_t value; | |
| 108 | } SeqFlags; | |
| 109 | ||
| 110 | uint32_t UserMaxFrameSize; | |
| 111 | uint16_t reserved2; | |
| 112 | uint16_t reserved3; | |
| 113 | FRAME_RATE FrameRate[CODECHAL_ENCODE_VP9_MAX_NUM_TEMPORAL_LAYERS]; | |
| 114 | uint8_t NumTemporalLayersMinus1; | |
| 115 | uint8_t ICQQualityFactor; | |
| 116 | ||
| 117 | ENCODE_INPUT_COLORSPACE InputColorSpace; | |
| 118 | ENCODE_SCENARIO ScenarioInfo; | |
| 119 | ENCODE_CONTENT ContentInfo; | |
| 120 | ENCODE_FRAMESIZE_TOLERANCE FrameSizeTolerance; | |
| 121 | ||
| 122 | } CODEC_VP9_ENCODE_SEQUENCE_PARAMS, *PCODEC_VP9_ENCODE_SEQUENCE_PARAMS; | |
| 123 | ||
| 124 | typedef struct _CODEC_VP9_ENCODE_PIC_PARAMS | |
| 125 | { | |
| 126 | uint16_t SrcFrameHeightMinus1; | |
| 127 | uint16_t SrcFrameWidthMinus1; | |
| 128 | uint16_t DstFrameHeightMinus1; | |
| 129 | uint16_t DstFrameWidthMinus1; | |
| 130 | ||
| 131 | CODEC_PICTURE CurrOriginalPic; | |
| 132 | CODEC_PICTURE CurrReconstructedPic; | |
| 133 | CODEC_PICTURE RefFrameList[8]; | |
| 134 | ||
| 135 | union | |
| 136 | { | |
| 137 | struct | |
| 138 | { | |
| 139 | uint32_t frame_type : 1; | |
| 140 | uint32_t show_frame : 1; | |
| 141 | uint32_t error_resilient_mode : 1; | |
| 142 | uint32_t intra_only : 1; | |
| 143 | uint32_t allow_high_precision_mv : 1; | |
| 144 | uint32_t mcomp_filter_type : 3; | |
| 145 | uint32_t frame_parallel_decoding_mode : 1; | |
| 146 | uint32_t segmentation_enabled : 1; | |
| 147 | uint32_t segmentation_temporal_update : 1; | |
| 148 | uint32_t segmentation_update_map : 1; | |
| 149 | uint32_t reset_frame_context : 2; | |
| 150 | uint32_t refresh_frame_context : 1; | |
| 151 | uint32_t frame_context_idx : 2; | |
| 152 | uint32_t LosslessFlag : 1; | |
| 153 | uint32_t comp_prediction_mode : 2; | |
| 154 | uint32_t super_frame : 1; | |
| 155 | uint32_t seg_id_block_size : 2; | |
| 156 | uint32_t seg_update_data : 1; | |
| 157 | uint32_t reserved : 8; | |
| 158 | } fields; | |
| 159 | ||
| 160 | uint32_t value; | |
| 161 | } PicFlags; | |
| 162 | ||
| 163 | union | |
| 164 | { | |
| 165 | struct | |
| 166 | { | |
| 167 | uint32_t LastRefIdx : 3; | |
| 168 | uint32_t LastRefSignBias : 1; | |
| 169 | uint32_t GoldenRefIdx : 3; | |
| 170 | uint32_t GoldenRefSignBias : 1; | |
| 171 | uint32_t AltRefIdx : 3; | |
| 172 | uint32_t AltRefSignBias : 1; | |
| 173 | ||
| 174 | uint32_t ref_frame_ctrl_l0 : 3; | |
| 175 | uint32_t ref_frame_ctrl_l1 : 3; | |
| 176 | ||
| 177 | uint32_t refresh_frame_flags : 8; | |
| 178 | uint32_t reserved2 : 6; | |
| 179 | } fields; | |
| 180 | ||
| 181 | uint32_t value; | |
| 182 | } RefFlags; | |
| 183 | ||
| 184 | uint8_t LumaACQIndex; | |
| 185 | char LumaDCQIndexDelta; | |
| 186 | char ChromaACQIndexDelta; | |
| 187 | char ChromaDCQIndexDelta; | |
| 188 | ||
| 189 | uint8_t filter_level; // This is not to be set for VP9 VDEnc (G10+), this is removed from DDI, only here to support legacy KBL DP | |
| 190 | uint8_t sharpness_level; // This is not to be set for VP9 VDEnc (G10+), this is removed from DDI, only here to support legacy KBL DP | |
| 191 | ||
| 192 | char LFRefDelta[4]; // This is not to be set for VP9 VDEnc (G10+), this is removed from DDI, only here to support legacy KBL DP | |
| 193 | char LFModeDelta[2]; // This is not to be set for VP9 VDEnc (G10+), this is removed from DDI, only here to support legacy KBL DP | |
| 194 | ||
| 195 | uint16_t BitOffsetForLFRefDelta; | |
| 196 | uint16_t BitOffsetForLFModeDelta; | |
| 197 | uint16_t BitOffsetForLFLevel; | |
| 198 | uint16_t BitOffsetForQIndex; | |
| 199 | uint16_t BitOffsetForFirstPartitionSize; | |
| 200 | uint16_t BitOffsetForSegmentation; | |
| 201 | uint16_t BitSizeForSegmentation; | |
| 202 | ||
| 203 | uint8_t log2_tile_rows; | |
| 204 | uint8_t log2_tile_columns; | |
| 205 | ||
| 206 | uint8_t temporal_id; | |
| 207 | ||
| 208 | uint32_t StatusReportFeedbackNumber; | |
| 209 | ||
| 210 | // Skip Frames | |
| 211 | uint8_t SkipFrameFlag; // [0..2] | |
| 212 | uint8_t NumSkipFrames; | |
| 213 | uint32_t SizeSkipFrames; | |
| 214 | } CODEC_VP9_ENCODE_PIC_PARAMS, *PCODEC_VP9_ENCODE_PIC_PARAMS; | |
| 215 | #endif |
| 18 | 18 | # OTHER DEALINGS IN THE SOFTWARE. |
| 19 | 19 | |
| 20 | 20 | set(TMP_HEADERS_ |
| 21 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_encode.h | |
| 21 | 22 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_av1.h |
| 23 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_av1.h | |
| 22 | 24 | ) |
| 23 | 25 | |
| 24 | 26 | set(TMP_2_HEADERS_ |
| 25 | 27 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common.h |
| 28 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_avc.h | |
| 29 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_hevc.h | |
| 30 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_jpeg.h | |
| 31 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_mpeg2.h | |
| 32 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_vp9.h | |
| 33 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_avc.h | |
| 34 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_hevc.h | |
| 35 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_vc1.h | |
| 36 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_vp9.h | |
| 37 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode.h | |
| 38 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode_avc.h | |
| 39 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode_jpeg.h | |
| 40 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode_mpeg2.h | |
| 41 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode_vp9.h | |
| 26 | 42 | ) |
| 27 | 43 | |
| 28 | 44 | set(HEADERS_ |
| 29 | 45 | ${HEADERS_} |
| 46 | ${TMP_HEADERS_} | |
| 47 | ${TMP_2_HEADERS_} | |
| 48 | ) | |
| 49 | ||
| 50 | set(COMMON_HEADERS_ | |
| 51 | ${COMMON_HEADERS_} | |
| 30 | 52 | ${TMP_HEADERS_} |
| 31 | 53 | ${TMP_2_HEADERS_} |
| 32 | 54 | ) |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | media_include_subdirectory(vdbox) |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | set(TMP_HEADERS_ | |
| 21 | ${CMAKE_CURRENT_LIST_DIR}/mhw_vdbox.h | |
| 22 | ) | |
| 23 | ||
| 24 | set(HEADERS_ | |
| 25 | ${HEADERS_} | |
| 26 | ${TMP_HEADERS_} | |
| 27 | ) | |
| 28 | ||
| 29 | set(COMMON_HEADERS_ | |
| 30 | ${COMMON_HEADERS_} | |
| 31 | ${TMP_HEADERS_} | |
| 32 | ) | |
| 33 | ||
| 34 | source_group( "MHW\\Vdbox" FILES ${TMP_HEADERS_} ) | |
| 35 | ||
| 36 | media_add_curr_to_include_path()⏎ |
| 0 | /* | |
| 1 | * Copyright (c) 2014-2020, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file mhw_vdbox.h | |
| 23 | //! \brief This modules implements HW interface layer to be used on all platforms on all operating systems/DDIs, across MHW components. | |
| 24 | //! | |
| 25 | #ifndef _MHW_VDBOX_H_ | |
| 26 | #define _MHW_VDBOX_H_ | |
| 27 | ||
| 28 | #include "codec_def_encode_avc.h" | |
| 29 | #include "codec_def_encode_jpeg.h" | |
| 30 | #include "codec_def_encode_mpeg2.h" | |
| 31 | #include "codec_def_encode_vp9.h" | |
| 32 | #include "codec_def_decode_vp9.h" | |
| 33 | #include "codec_def_decode_vc1.h" | |
| 34 | #include "codec_def_decode_avc.h" | |
| 35 | #include "codec_def_decode_hevc.h" | |
| 36 | #include "mos_os.h" | |
| 37 | #include "mhw_utilities.h" | |
| 38 | ||
| 39 | #define MHW_VDBOX_VC1_BITPLANE_BUFFER_PITCH_SMALL 64 | |
| 40 | #define MHW_VDBOX_VC1_BITPLANE_BUFFER_PITCH_LARGE 128 | |
| 41 | ||
| 42 | #define MHW_VDBOX_MFX_RAW_UV_PLANE_ALIGNMENT_GEN9 4 // starting Gen9 the alignment is relaxed to 4x instead of 16x | |
| 43 | #define MHW_VDBOX_MFX_UV_PLANE_ALIGNMENT_LEGACY 16 | |
| 44 | #define MHW_VDBOX_MFX_RECON_UV_PLANE_ALIGNMENT 16 | |
| 45 | #define MHW_VDBOX_HCP_RAW_UV_PLANE_ALIGNMENT 4 // starting Gen9 the alignment is relaxed to 4x instead of 16x | |
| 46 | #define MHW_VDBOX_HCP_RECON_UV_PLANE_ALIGNMENT 8 | |
| 47 | ||
| 48 | #define MHW_VDBOX_PAK_BITSTREAM_OVERFLOW_SIZE 400 | |
| 49 | #define MHW_VDBOX_PAK_SLICE_HEADER_OVERFLOW_SIZE 50 | |
| 50 | #define MHW_VDBOX_VDENC_DYNAMIC_SLICE_WA_COUNT 1500 | |
| 51 | ||
| 52 | // Rowstore Cache values | |
| 53 | #define MHW_VDBOX_PICWIDTH_1K 1024 | |
| 54 | #define MHW_VDBOX_PICWIDTH_2K 2048 | |
| 55 | #define MHW_VDBOX_PICWIDTH_3K 3072 | |
| 56 | #define MHW_VDBOX_PICWIDTH_4K 4096 | |
| 57 | #define MHW_VDBOX_PICWIDTH_8K 8192 | |
| 58 | #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 256 | |
| 59 | #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 384 | |
| 60 | #define INTRAROWSTORE_MBAFF_BASEADDRESS_PICWIDTH_LESS_THAN_2K 512 | |
| 61 | #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_3K_AND_4K 384 | |
| 62 | #define DEBLOCKINGROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 384 | |
| 63 | #define BSDMPCROWSTORE_BASEADDRESS 0 | |
| 64 | #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 128 | |
| 65 | #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 192 | |
| 66 | #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_GREATER_THAN_3K 256 | |
| 67 | #define MPRROWSTORE_MBAFF_BASEADDRESS_PICWIDTH_LESS_THAN_2K 256 | |
| 68 | #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_LESS_THAN_2K 128 | |
| 69 | #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 192 | |
| 70 | #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_BETWEEN_3K_AND_4K 256 | |
| 71 | #define HEVCDATROWSTORE_BASEADDRESS 0 | |
| 72 | #define HEVCDFROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 64 | |
| 73 | #define HEVCDFROWSTORE_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_4K 128 | |
| 74 | #define HEVCSAOROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 320 | |
| 75 | #define VP9HVDROWSTORE_BASEADDRESS 0 | |
| 76 | #define VP9DFROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 32 | |
| 77 | #define MHW_CACHELINE_SIZE 64 | |
| 78 | #define BYTES_PER_DWORD 4 | |
| 79 | #define NUM_PAK_DWS_PER_LCU 5 | |
| 80 | #define NUM_DWS_PER_CU 8 | |
| 81 | ||
| 82 | #define VP9DFROWSTORE_BASEADDRESS_8BIT_PICWIDTH_LESS_THAN_OR_EQU_TO_4K 384 | |
| 83 | #define VP9DATROWSTORE_BASEADDRESS_8BIT_PICWIDTH_LESS_THAN_OR_EQU_TO_4K 64 | |
| 84 | ||
| 85 | typedef enum _MHW_VDBOX_ADDRESS_SHIFT | |
| 86 | { | |
| 87 | MHW_VDBOX_SURFACE_STATE_SHIFT = 0, | |
| 88 | MHW_VDBOX_MFX_GENERAL_STATE_SHIFT = 6, | |
| 89 | MHW_VDBOX_HCP_GENERAL_STATE_SHIFT = 6, | |
| 90 | MHW_VDBOX_HUC_GENERAL_STATE_SHIFT = 6, | |
| 91 | MHW_VDBOX_MFX_UPPER_BOUND_STATE_SHIFT = 12, | |
| 92 | MHW_VDBOX_STATE_BASE_ADDRESS_SHIFT = 12, | |
| 93 | MHW_VDBOX_HCP_UPPER_BOUND_STATE_SHIFT = 12, | |
| 94 | MHW_VDBOX_HUC_UPPER_BOUND_STATE_SHIFT = 12, | |
| 95 | MHW_VDBOX_HUC_IMEM_STATE_SHIFT = 15, | |
| 96 | MHW_VDBOX_HCP_DECODED_BUFFER_SHIFT = 12 | |
| 97 | } MHW_VDBOX_ADDRESS_SHIFT; | |
| 98 | ||
| 99 | typedef enum _MHW_VDBOX_NODE_IND | |
| 100 | { | |
| 101 | MHW_VDBOX_NODE_1 = 0x0, | |
| 102 | MHW_VDBOX_NODE_2 = 0x1, | |
| 103 | MHW_VDBOX_NODE_MAX | |
| 104 | } MHW_VDBOX_NODE_IND; | |
| 105 | ||
| 106 | typedef struct _MHW_VDBOX_AVC_QM_PARAMS | |
| 107 | { | |
| 108 | uint8_t List4x4[6][16]; | |
| 109 | uint8_t List8x8[2][64]; | |
| 110 | } MHW_VDBOX_AVC_QM_PARAMS, *PMHW_VDBOX_AVC_QM_PARAMS; | |
| 111 | ||
| 112 | typedef struct _MHW_VDBOX_HEVC_QM_PARAMS | |
| 113 | { | |
| 114 | uint8_t List4x4[6][16]; | |
| 115 | uint8_t List8x8[6][64]; | |
| 116 | uint8_t List16x16[6][64]; | |
| 117 | uint8_t List32x32[2][64]; | |
| 118 | uint8_t ListDC16x16[6]; | |
| 119 | uint8_t ListDC32x32[2]; | |
| 120 | } MHW_VDBOX_HEVC_QM_PARAMS, *PMHW_VDBOX_HEVC_QM_PARAMS; | |
| 121 | ||
| 122 | typedef enum _HCP_SURFACE_FORMAT | |
| 123 | { | |
| 124 | HCP_SURFACE_FORMAT_YUY2 = 0x0, | |
| 125 | HCP_SURFACE_FORMAT_RGBX8888 = 0x1, | |
| 126 | HCP_SURFACE_FORMAT_AYUV4444 = 0x2, | |
| 127 | HCP_SURFACE_FORMAT_P010_VARIANT = 0x3, | |
| 128 | HCP_SURFACE_FORMAT_PLANAR_420_8 = 0x4, | |
| 129 | HCP_SURFACE_FORMAT_UYVY = 0x5, | |
| 130 | HCP_SURFACE_FORMAT_YVYU = 0x6, | |
| 131 | HCP_SURFACE_FORMAT_VYUY = 0x7, | |
| 132 | HCP_SURFACE_FORMAT_Y210 = 0x8, | |
| 133 | HCP_SURFACE_FORMAT_Y216 = 0x8, | |
| 134 | HCP_SURFACE_FORMAT_RGBA1010102 = 0x9, | |
| 135 | HCP_SURFACE_FORMAT_Y410 = 0xA, | |
| 136 | HCP_SURFACE_FORMAT_NV21 = 0xB, | |
| 137 | HCP_SURFACE_FORMAT_Y416 = 0xC, | |
| 138 | HCP_SURFACE_FORMAT_P010 = 0xD, | |
| 139 | HCP_SURFACE_FORMAT_P016 = 0xE, | |
| 140 | HCP_SURFACE_FORMAT_Y8 = 0xF, | |
| 141 | HCP_SURFACE_FORMAT_Y16 = 0x10, | |
| 142 | HCP_SURFACE_FORMAT_Y216_VARIANT = 0x11, | |
| 143 | HCP_SURFACE_FORMAT_Y416_VARIANT = 0x12, | |
| 144 | HCP_SURFACE_FORMAT_YUYV_VARIANT = 0x13, | |
| 145 | HCP_SURFACE_FORMAT_AYUV4444_VARIANT = 0x14, | |
| 146 | HCP_SURFACE_FORMAT_RESERVED = 0x15, | |
| 147 | } HCP_SURFACE_FORMAT; | |
| 148 | ||
| 149 | typedef enum _PIPE_WORK_MODE | |
| 150 | { | |
| 151 | MHW_VDBOX_HCP_PIPE_WORK_MODE_LEGACY = 0, | |
| 152 | MHW_VDBOX_HCP_PIPE_WORK_MODE_CABAC_FE = 1, | |
| 153 | MHW_VDBOX_HCP_PIPE_WORK_MODE_CODEC_BE = 2, | |
| 154 | MHW_VDBOX_HCP_PIPE_WORK_MODE_CABAC_REAL_TILE = 3, | |
| 155 | }MHW_VDBOX_HCP_PIPE_WORK_MODE; | |
| 156 | ||
| 157 | typedef enum _MULTI_ENGINE_MODE | |
| 158 | { | |
| 159 | MHW_VDBOX_HCP_MULTI_ENGINE_MODE_FE_LEGACY = 0, | |
| 160 | MHW_VDBOX_HCP_MULTI_ENGINE_MODE_LEFT = 1, | |
| 161 | MHW_VDBOX_HCP_MULTI_ENGINE_MODE_RIGHT = 2, | |
| 162 | MHW_VDBOX_HCP_MULTI_ENGINE_MODE_MIDDLE = 3, | |
| 163 | }MHW_VDBOX_HCP_MULTI_ENGINE_MODE; | |
| 164 | ||
| 165 | typedef enum | |
| 166 | { | |
| 167 | MHW_VDBOX_HCP_RT_FIRST_PHASE = 0, //!< First phase | |
| 168 | MHW_VDBOX_HCP_RT_MIDDLE_PHASE = 1, //!< Middle phase | |
| 169 | MHW_VDBOX_HCP_RT_LAST_PHASE = 2 //!< Last phase | |
| 170 | } MHW_HCP_RT_PHASE_INDICATOR; | |
| 171 | ||
| 172 | typedef enum _VDENC_PIPE_NUM_OF_PIPE | |
| 173 | { | |
| 174 | VDENC_PIPE_SINGLE_PIPE = 0, | |
| 175 | VDENC_PIPE_TWO_PIPE = 1, | |
| 176 | VDENC_PIPE_INVALID = 2, | |
| 177 | VDENC_PIPE_FOUR_PIPE = 3, | |
| 178 | }VDENC_PIPE_NUM_OF_PIPE; | |
| 179 | ||
| 180 | typedef enum | |
| 181 | { | |
| 182 | HCP_CHROMA_FORMAT_MONOCHROME = 0, | |
| 183 | HCP_CHROMA_FORMAT_YUV420 = 1, | |
| 184 | HCP_CHROMA_FORMAT_YUV422 = 2, | |
| 185 | HCP_CHROMA_FORMAT_YUV444 = 3 | |
| 186 | } HCP_CHROMA_FORMAT_IDC; | |
| 187 | ||
| 188 | // Media memory compression trigger | |
| 189 | typedef enum _MHW_MEDIA_MEMORY_COMPRESSION_EN | |
| 190 | { | |
| 191 | MHW_MEDIA_MEMCOMP_DISABLED = 0x0, | |
| 192 | MHW_MEDIA_MEMCOMP_ENABLED = 0x1 | |
| 193 | } MHW_MEDIA_MEMORY_COMPRESSION_EN; | |
| 194 | ||
| 195 | // Media memory compression mode | |
| 196 | typedef enum _MHW_MEDIA_MEMORY_COMPRESSION_MODE | |
| 197 | { | |
| 198 | MHW_MEDIA_MEMCOMP_MODE_HORIZONTAL = 0x0, | |
| 199 | MHW_MEDIA_MEMCOMP_MODE_VERTICAL = 0x1, | |
| 200 | } MHW_MEDIA_MEMORY_COMPRESSION_MODE; | |
| 201 | ||
| 202 | //! | |
| 203 | //! \enum ROWSTORE_SCRATCH_BUFFER_CACHE | |
| 204 | //! \brief Rowstore scratch buffer cache select | |
| 205 | //! | |
| 206 | enum ROWSTORE_SCRATCH_BUFFER_CACHE | |
| 207 | { | |
| 208 | BUFFER_TO_LLC = 0x0, | |
| 209 | BUFFER_TO_INTERNALMEDIASTORAGE = 0x1 | |
| 210 | }; | |
| 211 | ||
| 212 | struct MHW_VDBOX_PIPE_MODE_SELECT_PARAMS | |
| 213 | { | |
| 214 | uint32_t Mode = 0; | |
| 215 | bool bStreamOutEnabled = false; | |
| 216 | bool bStreamOutEnabledExtEnabled = false; | |
| 217 | bool bShortFormatInUse = false; | |
| 218 | bool bVC1OddFrameHeight = false; | |
| 219 | bool pakFrmLvlStrmoutEnable = false; | |
| 220 | bool pakPiplnStrmoutEnabled = false; | |
| 221 | ||
| 222 | bool bDeblockerStreamOutEnable = false; | |
| 223 | bool bPostDeblockOutEnable = false; | |
| 224 | bool bPreDeblockOutEnable = false; | |
| 225 | bool bDynamicSliceEnable = false; | |
| 226 | bool bSaoFirstPass = false; | |
| 227 | bool bRdoqEnable = false; | |
| 228 | bool bDynamicScalingEnabled = false; | |
| 229 | ||
| 230 | // VDEnc specific | |
| 231 | bool bVdencEnabled = false; | |
| 232 | bool bVdencStreamInEnable = false; | |
| 233 | uint8_t ucVdencBitDepthMinus8 = 0; | |
| 234 | bool bPakThresholdCheckEnable = false; | |
| 235 | bool bVdencPakObjCmdStreamOutEnable = false; | |
| 236 | bool bBatchBufferInUse = false; | |
| 237 | bool bTlbPrefetchEnable = 0; | |
| 238 | PMHW_BATCH_BUFFER pBatchBuffer = nullptr; | |
| 239 | uint32_t ChromaType = 0; | |
| 240 | MOS_FORMAT Format = {}; | |
| 241 | bool isIFrame = false; | |
| 242 | bool bIBCEnabled = false; | |
| 243 | ||
| 244 | // HuC specific | |
| 245 | uint32_t dwMediaSoftResetCounterValue = 0; | |
| 246 | bool bAdvancedRateControlEnable = false; | |
| 247 | bool bStreamObjectUsed = false; | |
| 248 | // No need to set protection settings | |
| 249 | bool disableProtectionSetting = false; | |
| 250 | virtual ~MHW_VDBOX_PIPE_MODE_SELECT_PARAMS() {} | |
| 251 | }; | |
| 252 | using PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS = MHW_VDBOX_PIPE_MODE_SELECT_PARAMS * ; | |
| 253 | ||
| 254 | typedef struct _MHW_VDBOX_SURFACE_PARAMS | |
| 255 | { | |
| 256 | uint32_t Mode; | |
| 257 | PMOS_SURFACE psSurface; // 2D surface parameters | |
| 258 | uint8_t ucVDirection; | |
| 259 | uint8_t ChromaType; | |
| 260 | uint8_t ucSurfaceStateId; | |
| 261 | uint8_t ucBitDepthLumaMinus8; | |
| 262 | uint8_t ucBitDepthChromaMinus8; | |
| 263 | uint32_t dwUVPlaneAlignment; | |
| 264 | bool bDisplayFormatSwizzle; | |
| 265 | bool bSrc8Pak10Mode; | |
| 266 | bool bColorSpaceSelection; | |
| 267 | bool bVdencDynamicScaling; | |
| 268 | uint32_t dwActualWidth; | |
| 269 | uint32_t dwActualHeight; | |
| 270 | uint32_t dwReconSurfHeight; | |
| 271 | MOS_MEMCOMP_STATE mmcState; | |
| 272 | uint8_t mmcSkipMask; | |
| 273 | uint32_t dwCompressionFormat; | |
| 274 | } MHW_VDBOX_SURFACE_PARAMS, *PMHW_VDBOX_SURFACE_PARAMS; | |
| 275 | ||
| 276 | struct MHW_VDBOX_PIPE_BUF_ADDR_PARAMS | |
| 277 | { | |
| 278 | uint32_t Mode = 0; | |
| 279 | PMOS_SURFACE psPreDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface | |
| 280 | MOS_MEMCOMP_STATE PreDeblockSurfMmcState = MOS_MEMCOMP_DISABLED; | |
| 281 | PMOS_SURFACE psPostDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface | |
| 282 | MOS_MEMCOMP_STATE PostDeblockSurfMmcState = MOS_MEMCOMP_DISABLED; | |
| 283 | PMOS_SURFACE psRawSurface = nullptr; // Pointer to MOS_SURFACE of raw surface | |
| 284 | MOS_MEMCOMP_STATE RawSurfMmcState = MOS_MEMCOMP_DISABLED; | |
| 285 | PMOS_SURFACE ps4xDsSurface = nullptr; | |
| 286 | MOS_MEMCOMP_STATE Ps4xDsSurfMmcState = MOS_MEMCOMP_DISABLED; | |
| 287 | PMOS_SURFACE ps8xDsSurface = nullptr; | |
| 288 | MOS_MEMCOMP_STATE Ps8xDsSurfMmcState = MOS_MEMCOMP_DISABLED; | |
| 289 | PMOS_RESOURCE presDataBuffer = nullptr; // Handle of residual difference surface | |
| 290 | PMOS_RESOURCE presReferences[CODEC_MAX_NUM_REF_FRAME] = {}; | |
| 291 | PMOS_RESOURCE presMfdIntraRowStoreScratchBuffer = nullptr; // Handle of MFD Intra Row Store Scratch data surface | |
| 292 | PMOS_RESOURCE presMfdDeblockingFilterRowStoreScratchBuffer = nullptr; // Handle of MFD Deblocking Filter Row Store Scratch data surface | |
| 293 | PMOS_RESOURCE presStreamOutBuffer = nullptr; | |
| 294 | MOS_MEMCOMP_STATE StreamOutBufMmcState = MOS_MEMCOMP_DISABLED; | |
| 295 | PMOS_RESOURCE presMacroblockIldbStreamOutBuffer1 = nullptr; | |
| 296 | PMOS_RESOURCE presMacroblockIldbStreamOutBuffer2 = nullptr; | |
| 297 | PMOS_RESOURCE presSliceSizeStreamOutBuffer = nullptr; | |
| 298 | PMOS_SURFACE psFwdRefSurface0 = nullptr; | |
| 299 | PMOS_SURFACE psFwdRefSurface1 = nullptr; | |
| 300 | PMOS_SURFACE psFwdRefSurface2 = nullptr; | |
| 301 | bool bDynamicScalingEnable = false; | |
| 302 | ||
| 303 | PMOS_RESOURCE presVdencIntraRowStoreScratchBuffer = nullptr; // For VDEnc, Handle of VDEnc Intra Row Store Scratch data surface | |
| 304 | PMOS_RESOURCE presVdencTileRowStoreBuffer = nullptr; | |
| 305 | PMOS_RESOURCE presVdencStreamOutBuffer = nullptr; | |
| 306 | PMOS_RESOURCE presVdencCuObjStreamOutBuffer = nullptr; | |
| 307 | PMOS_RESOURCE presVdencPakObjCmdStreamOutBuffer = nullptr; | |
| 308 | PMOS_RESOURCE presVdencStreamInBuffer = nullptr; | |
| 309 | PMOS_RESOURCE presVdencReferences[CODEC_MAX_NUM_REF_FRAME] = {}; | |
| 310 | PMOS_RESOURCE presVdenc4xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {}; | |
| 311 | PMOS_RESOURCE presVdenc8xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {}; | |
| 312 | ||
| 313 | PMOS_RESOURCE presVdencColocatedMVWriteBuffer = nullptr; // For AVC only | |
| 314 | PMOS_RESOURCE presVdencColocatedMVReadBuffer = nullptr; // For AVC only | |
| 315 | PMOS_RESOURCE presDeblockingFilterTileRowStoreScratchBuffer = nullptr; // For HEVC, VP9 | |
| 316 | PMOS_RESOURCE presDeblockingFilterColumnRowStoreScratchBuffer = nullptr; // For HEVC, VP9 | |
| 317 | PMOS_RESOURCE presMetadataLineBuffer = nullptr; // For HEVC, VP9 | |
| 318 | PMOS_RESOURCE presMetadataTileLineBuffer = nullptr; // For HEVC, VP9 | |
| 319 | PMOS_RESOURCE presMetadataTileColumnBuffer = nullptr; // For HEVC, VP9 | |
| 320 | PMOS_RESOURCE presSaoLineBuffer = nullptr; // For HEVC only | |
| 321 | PMOS_RESOURCE presSaoTileLineBuffer = nullptr; // For HEVC only | |
| 322 | PMOS_RESOURCE presSaoTileColumnBuffer = nullptr; // For HEVC only | |
| 323 | PMOS_RESOURCE presCurMvTempBuffer = nullptr; // For HEVC, VP9 | |
| 324 | PMOS_RESOURCE presColMvTempBuffer[CODEC_MAX_NUM_REF_FRAME] = {}; // For HEVC, VP9 | |
| 325 | PMOS_RESOURCE presLcuBaseAddressBuffer = nullptr; // For HEVC only | |
| 326 | PMOS_RESOURCE presLcuILDBStreamOutBuffer = nullptr; // For HEVC only | |
| 327 | PMOS_RESOURCE presVp9ProbBuffer = nullptr; // For VP9 only | |
| 328 | PMOS_RESOURCE presVp9SegmentIdBuffer = nullptr; // For VP9 only | |
| 329 | PMOS_RESOURCE presHvdLineRowStoreBuffer = nullptr; // For VP9 only | |
| 330 | PMOS_RESOURCE presHvdTileRowStoreBuffer = nullptr; // For VP9 only | |
| 331 | PMOS_RESOURCE presSaoStreamOutBuffer = nullptr; // For HEVC only | |
| 332 | PMOS_RESOURCE presSaoRowStoreBuffer = nullptr; // For HEVC only | |
| 333 | PMOS_SURFACE presP010RTSurface = nullptr; // For HEVC only | |
| 334 | PMOS_RESOURCE presFrameStatStreamOutBuffer = nullptr; | |
| 335 | PMOS_RESOURCE presSseSrcPixelRowStoreBuffer = nullptr; | |
| 336 | PMOS_RESOURCE presSegmentMapStreamIn = nullptr; | |
| 337 | PMOS_RESOURCE presSegmentMapStreamOut = nullptr; | |
| 338 | PMOS_RESOURCE presPakCuLevelStreamoutBuffer = nullptr; | |
| 339 | PMHW_VDBOX_SURFACE_PARAMS pRawSurfParam = nullptr; | |
| 340 | PMHW_VDBOX_SURFACE_PARAMS pDecodedReconParam = nullptr; | |
| 341 | bool bVdencEnabled = false; | |
| 342 | bool bRawIs10Bit = false; | |
| 343 | bool bDecodecReconIs10Bit = false; | |
| 344 | uint32_t dwNumRefIdxL0ActiveMinus1 = 0; | |
| 345 | uint32_t dwNumRefIdxL1ActiveMinus1 = 0; | |
| 346 | uint32_t dwLcuStreamOutOffset = 0; | |
| 347 | uint32_t dwFrameStatStreamOutOffset = 0; | |
| 348 | uint32_t dwVdencStatsStreamOutOffset = 0; | |
| 349 | bool oneOnOneMapping = false; // Flag for indicating using 1:1 ref index mapping for vdenc | |
| 350 | bool isLowDelayB = true; // Flag to indicate if it is LDB | |
| 351 | bool isIFrame = false; // Flag to indicate if it is I frame | |
| 352 | bool isPFrame = false; // Flag to indicate if it is P frame | |
| 353 | bool bIBCEnabled = false; | |
| 354 | uint8_t IBCRefIdxMask = 0; | |
| 355 | PMOS_RESOURCE presVdencCumulativeCuCountStreamoutSurface = nullptr; | |
| 356 | virtual ~MHW_VDBOX_PIPE_BUF_ADDR_PARAMS() {} | |
| 357 | }; | |
| 358 | using PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS = MHW_VDBOX_PIPE_BUF_ADDR_PARAMS * ; | |
| 359 | ||
| 360 | typedef struct _MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS | |
| 361 | { | |
| 362 | uint32_t Mode; | |
| 363 | PMOS_RESOURCE presDataBuffer; | |
| 364 | uint32_t dwDataSize; | |
| 365 | uint32_t dwDataOffset; | |
| 366 | PMOS_RESOURCE presMvObjectBuffer; | |
| 367 | uint32_t dwMvObjectSize; | |
| 368 | uint32_t dwMvObjectOffset; | |
| 369 | PMOS_RESOURCE presPakBaseObjectBuffer; | |
| 370 | uint32_t dwPakBaseObjectSize; | |
| 371 | uint32_t dwPakBaseObjectOffset; | |
| 372 | PMOS_RESOURCE presPakTileSizeStasBuffer; | |
| 373 | uint32_t dwPakTileSizeStasBufferSize; | |
| 374 | uint32_t dwPakTileSizeRecordOffset; | |
| 375 | // used by VP9 | |
| 376 | PMOS_RESOURCE presCompressedHeaderBuffer; | |
| 377 | uint32_t dwCompressedHeaderSize; | |
| 378 | PMOS_RESOURCE presProbabilityDeltaBuffer; | |
| 379 | uint32_t dwProbabilityDeltaSize; | |
| 380 | PMOS_RESOURCE presProbabilityCounterBuffer; | |
| 381 | uint32_t dwProbabilityCounterOffset; | |
| 382 | uint32_t dwProbabilityCounterSize; | |
| 383 | PMOS_RESOURCE presTileRecordBuffer; | |
| 384 | uint32_t dwTileRecordSize; | |
| 385 | PMOS_RESOURCE presCuStatsBuffer; | |
| 386 | uint32_t dwCuStatsSize; | |
| 387 | ||
| 388 | PMOS_RESOURCE presStreamOutObjectBuffer; | |
| 389 | uint32_t dwStreamOutObjectSize; | |
| 390 | uint32_t dwStreamOutObjectOffset; | |
| 391 | } MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS, *PMHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS; | |
| 392 | ||
| 393 | struct MHW_VDBOX_AVC_IMG_PARAMS | |
| 394 | { | |
| 395 | // Decoding Params | |
| 396 | PCODEC_AVC_PIC_PARAMS pAvcPicParams = nullptr; | |
| 397 | PCODEC_MVC_EXT_PIC_PARAMS pMvcExtPicParams = nullptr; | |
| 398 | uint8_t ucActiveFrameCnt = 0; | |
| 399 | // Encoding Params | |
| 400 | PCODEC_AVC_ENCODE_SEQUENCE_PARAMS pEncodeAvcSeqParams = nullptr; | |
| 401 | PCODEC_AVC_ENCODE_PIC_PARAMS pEncodeAvcPicParams = nullptr; | |
| 402 | PCODEC_AVC_ENCODE_SLICE_PARAMS pEncodeAvcSliceParams = nullptr; | |
| 403 | PCODEC_REF_LIST *ppRefList = nullptr; | |
| 404 | CODEC_PIC_ID *pPicIdx = nullptr; | |
| 405 | uint32_t dwTqEnabled = 0; | |
| 406 | uint32_t dwTqRounding = 0; | |
| 407 | uint32_t dwMaxVmvR = 0; | |
| 408 | uint16_t wPicWidthInMb = 0; | |
| 409 | uint16_t wPicHeightInMb = 0; | |
| 410 | uint16_t wSlcHeightInMb = 0; | |
| 411 | uint8_t ucKernelMode = 0; // normal, performance, quality. | |
| 412 | ||
| 413 | //FEI multiple passes PAK ---max frame size | |
| 414 | uint16_t currPass = 0; | |
| 415 | uint8_t *pDeltaQp = nullptr; | |
| 416 | uint32_t dwMaxFrameSize = 0; | |
| 417 | ||
| 418 | bool bIPCMPass = false; | |
| 419 | // VDEnc specific | |
| 420 | bool bVdencEnabled = false; | |
| 421 | bool bVDEncPerfModeEnabled = false; | |
| 422 | bool bVdencStreamInEnabled = false; | |
| 423 | bool bVdencBRCEnabled = false; | |
| 424 | bool bSliceSizeStreamOutEnabled = false; | |
| 425 | bool bCrePrefetchEnable = false; | |
| 426 | bool bPerMBStreamOut = false; | |
| 427 | bool bRollingIRestrictFracCand = false; | |
| 428 | ||
| 429 | uint32_t dwMbSlcThresholdValue = 0; // For VDENC dynamic slice size control | |
| 430 | uint32_t dwVdencSliceMinusBytes = 0; | |
| 431 | uint8_t *pVDEncModeCost = nullptr; | |
| 432 | uint8_t *pVDEncMvCost = nullptr; | |
| 433 | uint8_t *pVDEncHmeMvCost = nullptr; | |
| 434 | uint32_t biWeight = 0; | |
| 435 | virtual ~MHW_VDBOX_AVC_IMG_PARAMS(){} | |
| 436 | }; | |
| 437 | using PMHW_VDBOX_AVC_IMG_PARAMS = MHW_VDBOX_AVC_IMG_PARAMS * ; | |
| 438 | ||
| 439 | typedef struct _MHW_VDBOX_QM_PARAMS | |
| 440 | { | |
| 441 | uint32_t Standard; | |
| 442 | uint32_t Mode; | |
| 443 | PMHW_VDBOX_AVC_QM_PARAMS pAvcIqMatrix; | |
| 444 | CodecMpeg2IqMatrix *pMpeg2IqMatrix; | |
| 445 | CodecJpegQuantMatrix *pJpegQuantMatrix; | |
| 446 | uint32_t JpegQMTableSelector; | |
| 447 | bool bJpegQMRotation; | |
| 448 | PMHW_VDBOX_HEVC_QM_PARAMS pHevcIqMatrix; | |
| 449 | } MHW_VDBOX_QM_PARAMS, *PMHW_VDBOX_QM_PARAMS; | |
| 450 | ||
| 451 | typedef struct _MHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS | |
| 452 | { | |
| 453 | uint32_t uiList; | |
| 454 | uint32_t uiLumaLogWeightDenom; | |
| 455 | uint32_t uiChromaLogWeightDenom; | |
| 456 | uint32_t uiLumaWeightFlag; | |
| 457 | uint32_t uiChromaWeightFlag; | |
| 458 | uint32_t uiNumRefForList; | |
| 459 | int16_t Weights[2][32][3][2]; | |
| 460 | PCODEC_AVC_ENCODE_PIC_PARAMS pAvcPicParams; | |
| 461 | } MHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS, *PMHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS; | |
| 462 | ||
| 463 | typedef struct _MHW_VDBOX_PAK_INSERT_PARAMS | |
| 464 | { | |
| 465 | PBSBuffer pBsBuffer; | |
| 466 | // also reuse dwBitSize for passing SrcDataEndingBitInclusion when (pEncoder->bLastPicInStream || pEncoder->bLastPicInSeq) | |
| 467 | uint32_t dwBitSize; | |
| 468 | uint32_t dwOffset; | |
| 469 | uint32_t uiSkipEmulationCheckCount; | |
| 470 | bool bLastPicInSeq; | |
| 471 | bool bLastPicInStream; | |
| 472 | bool bLastHeader; | |
| 473 | bool bEmulationByteBitsInsert; | |
| 474 | bool bSetLastPicInStreamData; | |
| 475 | bool bSliceHeaderIndicator; | |
| 476 | bool bHeaderLengthExcludeFrmSize; | |
| 477 | uint32_t *pdwMpeg2PicHeaderTotalBufferSize; | |
| 478 | uint32_t *pdwMpeg2PicHeaderDataStartOffset; | |
| 479 | bool bResetBitstreamStartingPos; | |
| 480 | bool bEndOfSlice; | |
| 481 | uint32_t dwLastPicInSeqData; | |
| 482 | uint32_t dwLastPicInStreamData; | |
| 483 | PMHW_BATCH_BUFFER pBatchBufferForPakSlices; | |
| 484 | bool bVdencInUse; | |
| 485 | } MHW_VDBOX_PAK_INSERT_PARAMS, *PMHW_VDBOX_PAK_INSERT_PARAMS; | |
| 486 | ||
| 487 | typedef struct _MHW_VDBOX_VP9_SEGMENT_STATE | |
| 488 | { | |
| 489 | uint32_t Mode; | |
| 490 | PCODEC_VP9_SEGMENT_PARAMS pVp9SegmentParams; | |
| 491 | PCODEC_VP9_ENCODE_SEGMENT_PARAMS pVp9EncodeSegmentParams; | |
| 492 | uint8_t ucCurrentSegmentId; | |
| 493 | uint8_t ucQPIndexLumaAC; | |
| 494 | const uint8_t *pcucLfQpLookup; | |
| 495 | uint8_t *pbSegStateBufferPtr; | |
| 496 | } MHW_VDBOX_VP9_SEGMENT_STATE, *PMHW_VDBOX_VP9_SEGMENT_STATE; | |
| 497 | ||
| 498 | typedef struct _MHW_VDBOX_HCP_BSD_PARAMS | |
| 499 | { | |
| 500 | uint32_t dwBsdDataLength; | |
| 501 | uint32_t dwBsdDataStartOffset; | |
| 502 | } MHW_VDBOX_HCP_BSD_PARAMS, *PMHW_VDBOX_HCP_BSD_PARAMS; | |
| 503 | ||
| 504 | typedef struct _MHW_VDBOX_ROWSTORE_PARAMS | |
| 505 | { | |
| 506 | uint32_t Mode = 0; | |
| 507 | uint32_t dwPicWidth = 0; | |
| 508 | uint32_t bMbaff = 0; | |
| 509 | bool bIsFrame = false; | |
| 510 | uint8_t ucBitDepthMinus8 = 0; | |
| 511 | uint8_t ucChromaFormat = 0; | |
| 512 | uint8_t ucLCUSize = 0; | |
| 513 | } MHW_VDBOX_ROWSTORE_PARAMS, *PMHW_VDBOX_ROWSTORE_PARAMS; | |
| 514 | ||
| 515 | typedef struct _MHW_VDBOX_ROWSTORE_CACHE | |
| 516 | { | |
| 517 | bool bSupported; | |
| 518 | bool bEnabled; | |
| 519 | uint32_t dwAddress; | |
| 520 | } MHW_VDBOX_ROWSTORE_CACHE, *PMHW_VDBOX_ROWSTORE_CACHE; | |
| 521 | ||
| 522 | struct MHW_VDBOX_STATE_CMDSIZE_PARAMS | |
| 523 | { | |
| 524 | bool bShortFormat = false; | |
| 525 | bool bHucDummyStream = false; | |
| 526 | bool bSfcInUse = false; | |
| 527 | uint32_t uNumStoreDataImm = 0; | |
| 528 | uint32_t uNumStoreReg = 0; | |
| 529 | uint32_t uNumMfxWait = 0; | |
| 530 | uint32_t uNumAddConBBEnd = 0; | |
| 531 | uint32_t uNumMiCopy = 0; | |
| 532 | uint32_t uNumMiFlush = 0; | |
| 533 | uint32_t bPerformHucStreamOut = false; | |
| 534 | uint32_t uNumVdPipelineFlush = 0; | |
| 535 | virtual ~MHW_VDBOX_STATE_CMDSIZE_PARAMS() {} | |
| 536 | }; | |
| 537 | using PMHW_VDBOX_STATE_CMDSIZE_PARAMS = MHW_VDBOX_STATE_CMDSIZE_PARAMS * ; | |
| 538 | ||
| 539 | typedef struct _MHW_VDBOX_AVC_SLICE_STATE | |
| 540 | { | |
| 541 | PCODEC_PIC_ID pAvcPicIdx; | |
| 542 | PMOS_RESOURCE presDataBuffer; | |
| 543 | uint32_t dwDataBufferOffset; | |
| 544 | uint32_t dwOffset; | |
| 545 | uint32_t dwLength; | |
| 546 | uint32_t dwSliceIndex; | |
| 547 | bool bLastSlice; | |
| 548 | uint32_t dwTotalBytesConsumed; | |
| 549 | ||
| 550 | // Decoding Only | |
| 551 | PCODEC_AVC_PIC_PARAMS pAvcPicParams; | |
| 552 | PCODEC_MVC_EXT_PIC_PARAMS pMvcExtPicParams; | |
| 553 | PCODEC_AVC_SLICE_PARAMS pAvcSliceParams; | |
| 554 | uint32_t dwNextOffset; | |
| 555 | uint32_t dwNextLength; | |
| 556 | bool bIntelEntrypointInUse; | |
| 557 | bool bPicIdRemappingInUse; | |
| 558 | bool bShortFormatInUse; | |
| 559 | bool bPhantomSlice; | |
| 560 | uint8_t ucDisableDeblockingFilterIdc; | |
| 561 | uint8_t ucSliceBetaOffsetDiv2; | |
| 562 | uint8_t ucSliceAlphaC0OffsetDiv2; | |
| 563 | ||
| 564 | // Encoding Only | |
| 565 | PCODEC_AVC_ENCODE_SEQUENCE_PARAMS pEncodeAvcSeqParams; | |
| 566 | PCODEC_AVC_ENCODE_PIC_PARAMS pEncodeAvcPicParams; | |
| 567 | PCODEC_AVC_ENCODE_SLICE_PARAMS pEncodeAvcSliceParams; | |
| 568 | PBSBuffer pBsBuffer; | |
| 569 | PCODECHAL_NAL_UNIT_PARAMS *ppNalUnitParams; | |
| 570 | PMHW_BATCH_BUFFER pBatchBufferForPakSlices; | |
| 571 | bool bSingleTaskPhaseSupported; | |
| 572 | bool bFirstPass; | |
| 573 | bool bLastPass; | |
| 574 | bool bBrcEnabled; | |
| 575 | bool bRCPanicEnable; | |
| 576 | bool bInsertBeforeSliceHeaders; | |
| 577 | bool bAcceleratorHeaderPackingCaps; | |
| 578 | uint32_t dwBatchBufferForPakSlicesStartOffset; | |
| 579 | uint32_t uiSkipEmulationCheckCount; | |
| 580 | uint32_t dwRoundingValue; | |
| 581 | uint32_t dwRoundingIntraValue; | |
| 582 | bool bRoundingInterEnable; | |
| 583 | uint16_t wFrameFieldHeightInMB; // Frame/field Height in MB | |
| 584 | bool bVdencInUse; | |
| 585 | bool bVdencNoTailInsertion; | |
| 586 | bool oneOnOneMapping = false; | |
| 587 | bool bFullFrameData; | |
| 588 | } MHW_VDBOX_AVC_SLICE_STATE, *PMHW_VDBOX_AVC_SLICE_STATE; | |
| 589 | ||
| 590 | #endif |
| 18 | 18 | # OTHER DEALINGS IN THE SOFTWARE. |
| 19 | 19 | |
| 20 | 20 | media_include_subdirectory(os) |
| 21 | media_include_subdirectory(codec)⏎ | |
| 21 | media_include_subdirectory(codec) | |
| 22 | media_include_subdirectory(hw)⏎ |
| 352 | 352 | __MEDIA_USER_FEATURE_VALUE_FORCE_AV1_TILE_BASED_DECODE_ID, |
| 353 | 353 | __MEDIA_USER_FEATURE_VALUE_AV1_ERROR_STATUS_ADDR_VALUE_ID, |
| 354 | 354 | __MEDIA_USER_FEATURE_VALUE_DECODE_HISTOGRAM_DEBUG_ID, |
| 355 | __MEDIA_USER_FEATURE_VALUE_DECODE_SFC_RGBFORMAT_OUTPUT_DEBUG_ID, | |
| 356 | __MEDIA_USER_FEATURE_VALUE_DECODE_SFC_LINEAR_OUTPUT_DEBUG_ID, | |
| 357 | __MEDIA_USER_FEATURE_VALUE_HEVC_VDENC_TCBRC_ARB_DISABLE_ID, | |
| 355 | 358 | #endif // (_DEBUG || _RELEASE_INTERNAL) |
| 356 | 359 | __MEDIA_USER_FEATURE_VALUE_STATUS_REPORTING_ENABLE_ID, |
| 357 | 360 | __MEDIA_USER_FEATURE_VALUE_SPLIT_SCREEN_DEMO_POSITION_ID, |
| 432 | 435 | __MEDIA_USER_FEATURE_MCPY_MODE_ID, |
| 433 | 436 | __MEDIA_USER_FEATURE_ENABLE_HW_DEBUG_HOOKS_ID, |
| 434 | 437 | __MEDIA_USER_FEATURE_VALUE_CODECHAL_FRAME_NUMBER_TO_STOP_ID, |
| 438 | __MEDIA_USER_FEATURE_VALUE_CODECHAL_ENABLE_SW_CRC_ID, | |
| 435 | 439 | __VPHAL_VEBOX_OUTPUTPIPE_MODE_ID, |
| 436 | 440 | __VPHAL_VEBOX_FEATURE_INUSE_ID, |
| 437 | 441 | __VPHAL_RNDR_SSD_CONTROL_ID, |
| 584 | 588 | __MEDIA_USER_FEATURE_VALUE_SFC_LINEAR_OUTPUT_USED_ID, |
| 585 | 589 | #endif |
| 586 | 590 | __MEDIA_USER_FEATURE_VALUE_PROTECT_MODE_ENABLE_ID, |
| 591 | __MEDIA_USER_FEATURE_VALUE_OLP_IN_USE_ID, | |
| 592 | __MEDIA_USER_FEATURE_VALUE_SKIP_FRAME_IN_USE_ID, | |
| 587 | 593 | __MOS_USER_FEATURE_KEY_MAX_ID, |
| 588 | 594 | } MOS_USER_FEATURE_VALUE_ID; |
| 589 | 595 | |
| 0 | /* | |
| 1 | * Copyright (c) 2011-2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codechal.cpp | |
| 23 | //! \brief Impelements the public interface for CodecHal. | |
| 24 | //! \details | |
| 25 | //! | |
| 26 | ||
| 27 | #include "codechal.h" | |
| 28 | #include "codechal_hw.h" | |
| 29 | #include "codechal_debug.h" | |
| 30 | #include "mos_solo_generic.h" | |
| 31 | #include "codechal_setting.h" | |
| 32 | ||
| 33 | Codechal::Codechal( | |
| 34 | CodechalHwInterface* hwInterface, | |
| 35 | CodechalDebugInterface* debugInterface) | |
| 36 | { | |
| 37 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 38 | ||
| 39 | CODECHAL_PUBLIC_CHK_NULL_NO_STATUS_RETURN(hwInterface); | |
| 40 | CODECHAL_PUBLIC_CHK_NULL_NO_STATUS_RETURN(hwInterface->GetOsInterface()); | |
| 41 | MOS_UNUSED(debugInterface); | |
| 42 | ||
| 43 | m_hwInterface = hwInterface; | |
| 44 | m_osInterface = hwInterface->GetOsInterface(); | |
| 45 | ||
| 46 | if (m_hwInterface->bEnableVdboxBalancingbyUMD && m_osInterface->bEnableVdboxBalancing) | |
| 47 | { | |
| 48 | m_hwInterface->m_getVdboxNodeByUMD = true; | |
| 49 | } | |
| 50 | ||
| 51 | #if USE_CODECHAL_DEBUG_TOOL | |
| 52 | CODECHAL_PUBLIC_CHK_NULL_NO_STATUS_RETURN(debugInterface); | |
| 53 | m_debugInterface = debugInterface; | |
| 54 | #endif // USE_CODECHAL_DEBUG_TOOL | |
| 55 | } | |
| 56 | ||
| 57 | Codechal::~Codechal() | |
| 58 | { | |
| 59 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 60 | ||
| 61 | MOS_TraceEvent(EVENT_CODECHAL_DESTROY, EVENT_TYPE_START, nullptr, 0, nullptr, 0); | |
| 62 | ||
| 63 | #if USE_CODECHAL_DEBUG_TOOL | |
| 64 | if (m_debugInterface != nullptr) | |
| 65 | { | |
| 66 | MOS_Delete(m_debugInterface); | |
| 67 | m_debugInterface = nullptr; | |
| 68 | } | |
| 69 | ||
| 70 | if (m_statusReportDebugInterface != nullptr) | |
| 71 | { | |
| 72 | MOS_Delete(m_statusReportDebugInterface); | |
| 73 | m_statusReportDebugInterface = nullptr; | |
| 74 | } | |
| 75 | #endif // USE_CODECHAL_DEBUG_TOOL | |
| 76 | ||
| 77 | // Destroy HW interface objects (GSH, SSH, etc) | |
| 78 | if (m_hwInterface != nullptr) | |
| 79 | { | |
| 80 | MOS_Delete(m_hwInterface); | |
| 81 | m_hwInterface = nullptr; | |
| 82 | } | |
| 83 | ||
| 84 | // Destroy OS interface objects (CBs, etc) | |
| 85 | if (m_osInterface != nullptr) | |
| 86 | { | |
| 87 | m_osInterface->pfnDestroy(m_osInterface, false); | |
| 88 | ||
| 89 | // Deallocate OS interface structure (except if externally provided) | |
| 90 | if (m_osInterface->bDeallocateOnExit) | |
| 91 | { | |
| 92 | MOS_FreeMemory(m_osInterface); | |
| 93 | } | |
| 94 | } | |
| 95 | ||
| 96 | MOS_TraceEvent(EVENT_CODECHAL_DESTROY, EVENT_TYPE_END, nullptr, 0, nullptr, 0); | |
| 97 | } | |
| 98 | ||
| 99 | MOS_STATUS Codechal::Allocate(CodechalSetting * codecHalSettings) | |
| 100 | { | |
| 101 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 102 | ||
| 103 | CODECHAL_PUBLIC_CHK_NULL_RETURN(codecHalSettings); | |
| 104 | CODECHAL_PUBLIC_CHK_NULL_RETURN(m_hwInterface); | |
| 105 | CODECHAL_PUBLIC_CHK_NULL_RETURN(m_osInterface); | |
| 106 | ||
| 107 | MOS_TraceEvent(EVENT_CODECHAL_CREATE, | |
| 108 | EVENT_TYPE_INFO, | |
| 109 | &codecHalSettings->codecFunction, | |
| 110 | sizeof(uint32_t), | |
| 111 | nullptr, | |
| 112 | 0); | |
| 113 | ||
| 114 | CODECHAL_PUBLIC_CHK_STATUS_RETURN(m_hwInterface->Initialize(codecHalSettings)); | |
| 115 | ||
| 116 | MOS_NULL_RENDERING_FLAGS nullHWAccelerationEnable; | |
| 117 | nullHWAccelerationEnable.Value = 0; | |
| 118 | ||
| 119 | #if (_DEBUG || _RELEASE_INTERNAL) | |
| 120 | if (!m_statusReportDebugInterface) | |
| 121 | { | |
| 122 | m_statusReportDebugInterface = MOS_New(CodechalDebugInterface); | |
| 123 | CODECHAL_PUBLIC_CHK_NULL_RETURN(m_statusReportDebugInterface); | |
| 124 | CODECHAL_PUBLIC_CHK_STATUS_RETURN( | |
| 125 | m_statusReportDebugInterface->Initialize(m_hwInterface, codecHalSettings->codecFunction)); | |
| 126 | } | |
| 127 | ||
| 128 | MOS_USER_FEATURE_VALUE_DATA userFeatureData; | |
| 129 | MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData)); | |
| 130 | MOS_UserFeature_ReadValue_ID( | |
| 131 | nullptr, | |
| 132 | __MEDIA_USER_FEATURE_VALUE_NULL_HW_ACCELERATION_ENABLE_ID, | |
| 133 | &userFeatureData, | |
| 134 | m_osInterface->pOsContext); | |
| 135 | nullHWAccelerationEnable.Value = userFeatureData.u32Data; | |
| 136 | ||
| 137 | m_useNullHw[MOS_GPU_CONTEXT_VIDEO] = | |
| 138 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVideo); | |
| 139 | m_useNullHw[MOS_GPU_CONTEXT_VIDEO2] = | |
| 140 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVideo2); | |
| 141 | m_useNullHw[MOS_GPU_CONTEXT_VIDEO3] = | |
| 142 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVideo3); | |
| 143 | m_useNullHw[MOS_GPU_CONTEXT_VDBOX2_VIDEO] = | |
| 144 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVDBox2Video); | |
| 145 | m_useNullHw[MOS_GPU_CONTEXT_VDBOX2_VIDEO2] = | |
| 146 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVDBox2Video2); | |
| 147 | m_useNullHw[MOS_GPU_CONTEXT_VDBOX2_VIDEO3] = | |
| 148 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVDBox2Video3); | |
| 149 | m_useNullHw[MOS_GPU_CONTEXT_RENDER] = | |
| 150 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxRender); | |
| 151 | m_useNullHw[MOS_GPU_CONTEXT_RENDER2] = | |
| 152 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxRender2); | |
| 153 | #endif // _DEBUG || _RELEASE_INTERNAL | |
| 154 | ||
| 155 | return MOS_STATUS_SUCCESS; | |
| 156 | } | |
| 157 | ||
| 158 | MOS_STATUS Codechal::BeginFrame() | |
| 159 | { | |
| 160 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 161 | return MOS_STATUS_SUCCESS; | |
| 162 | } | |
| 163 | ||
| 164 | MOS_STATUS Codechal::EndFrame() | |
| 165 | { | |
| 166 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 167 | return MOS_STATUS_SUCCESS; | |
| 168 | } | |
| 169 | ||
| 170 | MOS_STATUS Codechal::Execute(void *params) | |
| 171 | { | |
| 172 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 173 | ||
| 174 | CODECHAL_PUBLIC_CHK_NULL_RETURN(params); | |
| 175 | ||
| 176 | CODECHAL_DEBUG_TOOL( | |
| 177 | CODECHAL_PUBLIC_CHK_NULL_RETURN(m_osInterface); | |
| 178 | CODECHAL_PUBLIC_CHK_NULL_RETURN(m_debugInterface); | |
| 179 | ||
| 180 | CODECHAL_PUBLIC_CHK_STATUS_RETURN(Mos_Solo_ForceDumps( | |
| 181 | m_debugInterface->m_bufferDumpFrameNum, | |
| 182 | m_osInterface));) | |
| 183 | ||
| 184 | return MOS_STATUS_SUCCESS; | |
| 185 | } | |
| 186 | ||
| 187 | MOS_STATUS Codechal::GetStatusReport( | |
| 188 | void *status, | |
| 189 | uint16_t numStatus) | |
| 190 | { | |
| 191 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 192 | MOS_UNUSED(status); | |
| 193 | MOS_UNUSED(numStatus); | |
| 194 | CODECHAL_PUBLIC_ASSERTMESSAGE("Unsupported codec function requested."); | |
| 195 | return MOS_STATUS_UNKNOWN; | |
| 196 | } | |
| 197 | ||
| 198 | void Codechal::Destroy() | |
| 199 | { | |
| 200 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 201 | } | |
| 202 | ||
| 203 | MOS_STATUS Codechal::ResolveMetaData(PMOS_RESOURCE pInput, PMOS_RESOURCE pOutput) | |
| 204 | { | |
| 205 | return MOS_STATUS_SUCCESS; | |
| 206 | }⏎ |
| 25 | 25 | #ifndef __CODECHAL_H__ |
| 26 | 26 | #define __CODECHAL_H__ |
| 27 | 27 | |
| 28 | #include "mos_os.h" | |
| 29 | #include "mos_util_debug.h" | |
| 28 | #include "codechal_common.h" | |
| 29 | #include "mhw_cp_interface.h" | |
| 30 | 30 | #include "codec_def_common.h" |
| 31 | #include "mhw_cp_interface.h" | |
| 32 | 31 | |
| 33 | 32 | #ifdef __cplusplus |
| 34 | 33 | extern "C" { |
| 35 | 34 | #endif // __cplusplus |
| 35 | ||
| 36 | #define CODECHAL_PUBLIC_CHK_NULL(_ptr) \ | |
| 37 | MOS_CHK_NULL(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _ptr) | |
| 38 | ||
| 39 | #define CODECHAL_PUBLIC_CHK_STATUS(_stmt) \ | |
| 40 | MOS_CHK_STATUS(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _stmt) | |
| 41 | ||
| 42 | #define CODECHAL_PUBLIC_CHK_NULL_NO_STATUS(_ptr) \ | |
| 43 | MOS_CHK_NULL_NO_STATUS(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _ptr) | |
| 36 | 44 | |
| 37 | 45 | //----------------------------------------------------------------------------- |
| 38 | 46 | // Forward declaration - |
| 39 | 47 | // IMPORTANT - DDI interfaces are NOT to access internal CODECHAL states |
| 40 | 48 | //----------------------------------------------------------------------------- |
| 41 | class CodechalDebugInterface; | |
| 42 | 49 | class CodechalDecode; |
| 43 | 50 | class CodechalEncoderState; |
| 44 | class CodechalHwInterface; | |
| 45 | class CodechalSetting; | |
| 46 | 51 | |
| 47 | 52 | // Forward Declarations |
| 48 | 53 | class USERMODE_DEVICE_CONTEXT; |
| 147 | 152 | uint8_t RefQpIndex[3]; |
| 148 | 153 | }CODECHAL_VP8_HYBRIDPAK_FRAMEUPDATE, *PCODECHAL_VP8_HYBRIDPAK_FRAMEUPDATE; |
| 149 | 154 | |
| 150 | //------------------------------------------------------------------------------ | |
| 151 | // Simplified macros for debug message, Assert, Null check and MOS eStatus check | |
| 152 | // within Codechal without the need to explicitly pass comp and sub-comp name | |
| 153 | //------------------------------------------------------------------------------ | |
| 154 | //------------------------------------------------------------------------------ | |
| 155 | // Macros specific to MOS_CODEC_SUBCOMP_PUBLIC sub-comp | |
| 156 | //------------------------------------------------------------------------------ | |
| 157 | #define CODECHAL_PUBLIC_ASSERT(_expr) \ | |
| 158 | MOS_ASSERT(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _expr) | |
| 159 | ||
| 160 | #define CODECHAL_PUBLIC_ASSERTMESSAGE(_message, ...) \ | |
| 161 | MOS_ASSERTMESSAGE(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _message, ##__VA_ARGS__) | |
| 162 | ||
| 163 | #define CODECHAL_PUBLIC_NORMALMESSAGE(_message, ...) \ | |
| 164 | MOS_NORMALMESSAGE(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _message, ##__VA_ARGS__) | |
| 165 | ||
| 166 | #define CODECHAL_PUBLIC_VERBOSEMESSAGE(_message, ...) \ | |
| 167 | MOS_VERBOSEMESSAGE(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _message, ##__VA_ARGS__) | |
| 168 | ||
| 169 | #define CODECHAL_PUBLIC_FUNCTION_ENTER \ | |
| 170 | MOS_FUNCTION_ENTER(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC) | |
| 171 | ||
| 172 | #define CODECHAL_PUBLIC_CHK_STATUS(_stmt) \ | |
| 173 | MOS_CHK_STATUS(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _stmt) | |
| 174 | ||
| 175 | #define CODECHAL_PUBLIC_CHK_STATUS_RETURN(_stmt) \ | |
| 176 | MOS_CHK_STATUS_RETURN(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _stmt) | |
| 177 | ||
| 178 | #define CODECHAL_PUBLIC_CHK_STATUS_MESSAGE(_stmt, _message, ...) \ | |
| 179 | MOS_CHK_STATUS_MESSAGE(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _stmt, _message, ##__VA_ARGS__) | |
| 180 | ||
| 181 | #define CODECHAL_PUBLIC_CHK_NULL(_ptr) \ | |
| 182 | MOS_CHK_NULL(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _ptr) | |
| 183 | ||
| 184 | #define CODECHAL_PUBLIC_CHK_NULL_RETURN(_ptr) \ | |
| 185 | MOS_CHK_NULL_RETURN(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _ptr) | |
| 186 | ||
| 187 | #define CODECHAL_PUBLIC_CHK_NULL_NO_STATUS(_ptr) \ | |
| 188 | MOS_CHK_NULL_NO_STATUS(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _ptr) | |
| 189 | ||
| 190 | #define CODECHAL_PUBLIC_CHK_NULL_NO_STATUS_RETURN(_ptr) \ | |
| 191 | MOS_CHK_NULL_NO_STATUS_RETURN(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _ptr) | |
| 192 | ||
| 193 | 155 | /*! \brief Information pertaining to the PAK object and MV data. |
| 194 | 156 | */ |
| 195 | 157 | typedef struct _CODEC_ENCODE_MBDATA_LAYOUT |
| 213 | 175 | }CODECHAL_STANDARD_INFO, *PCODECHAL_STANDARD_INFO; |
| 214 | 176 | |
| 215 | 177 | //! |
| 216 | //! \class Codechal | |
| 217 | //! \brief This class defines the common member fields, functions etc as Codechal base class. | |
| 218 | //! | |
| 219 | class Codechal | |
| 220 | { | |
| 221 | public: | |
| 222 | //! | |
| 223 | //! \brief Constructor | |
| 224 | //! \param [in] hwInterface | |
| 225 | //! Hardware interface | |
| 226 | //! \param [in] debugInterface | |
| 227 | //! Debug interface | |
| 228 | //! | |
| 229 | Codechal( | |
| 230 | CodechalHwInterface* hwInterface, | |
| 231 | CodechalDebugInterface* debugInterface); | |
| 232 | ||
| 233 | //! | |
| 234 | //! \brief Copy constructor | |
| 235 | //! | |
| 236 | Codechal(const Codechal&) = delete; | |
| 237 | ||
| 238 | //! | |
| 239 | //! \brief Copy assignment operator | |
| 240 | //! | |
| 241 | Codechal& operator=(const Codechal&) = delete; | |
| 242 | ||
| 243 | //! | |
| 244 | //! \brief Destructor | |
| 245 | //! | |
| 246 | virtual ~Codechal(); | |
| 247 | ||
| 248 | //! | |
| 249 | //! \brief Allocate and intialize the Codechal. | |
| 250 | //! \param [in] codecHalSettings | |
| 251 | //! Settings used to finalize the creation of the CodecHal device | |
| 252 | //! \return MOS_STATUS | |
| 253 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 254 | //! | |
| 255 | virtual MOS_STATUS Allocate(CodechalSetting *codecHalSettings); | |
| 256 | ||
| 257 | //! | |
| 258 | //! \brief Signals the beginning of a picture. | |
| 259 | //! \details Initializes necessary parameters to perform the requested operation. | |
| 260 | //! \return MOS_STATUS | |
| 261 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 262 | //! | |
| 263 | virtual MOS_STATUS BeginFrame(); | |
| 264 | ||
| 265 | //! | |
| 266 | //! \brief Signals the end of a picture. | |
| 267 | //! \details This function closes out the picture which was started by BeginFrame(). | |
| 268 | //! All Execute() calls for a particular picture must be complete before | |
| 269 | //! EndFrame() is called. Resets all current picture parameters in | |
| 270 | //! preparation for the next BeginFrame(). For decode, in the case | |
| 271 | //! of incomplete frames, if the picture is still incomplete at EndFrame(), | |
| 272 | //! CodecHal conceals the error internally and submits the codec workload. | |
| 273 | //! \return MOS_STATUS | |
| 274 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 275 | //! | |
| 276 | virtual MOS_STATUS EndFrame(); | |
| 277 | ||
| 278 | //! | |
| 279 | //! \brief Performs the operation requested by the codec function. | |
| 280 | //! \param [in] params | |
| 281 | //! Parameters need to perform the requested function. The parameter structure | |
| 282 | //! changes based on codec function. | |
| 283 | //! \return MOS_STATUS | |
| 284 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 285 | //! | |
| 286 | virtual MOS_STATUS Execute(void *params); | |
| 287 | ||
| 288 | //! | |
| 289 | //! \brief Gets available statuses for executed pictures. | |
| 290 | //! \details All pictures for which EndFrame() has been called are eligable | |
| 291 | //! for status reporting. Once a successful or error status is reported out by | |
| 292 | //! CodecHal, it is discarded. | |
| 293 | //! \param [out] status | |
| 294 | //! Array to store statuses up to a maximum of wNumStatus, valid pointer | |
| 295 | //! must be passed in to GetStatusReport() | |
| 296 | //! \param [in] numStatus | |
| 297 | //! The size of the pCodecStatus array | |
| 298 | //! \return MOS_STATUS | |
| 299 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 300 | //! | |
| 301 | virtual MOS_STATUS GetStatusReport( | |
| 302 | void *status, | |
| 303 | uint16_t numStatus); | |
| 304 | ||
| 305 | //! | |
| 306 | //! \brief Destroy codechl state | |
| 307 | //! | |
| 308 | //! \return void | |
| 309 | //! | |
| 310 | virtual void Destroy(); | |
| 311 | ||
| 312 | //! | |
| 313 | //! \brief Resolve MetaData. | |
| 314 | //! \details Resolve MetaData from Input to Output. | |
| 315 | //! \param [out] pOutput | |
| 316 | //! Resolved Metadata resource. | |
| 317 | //! \param [in] pInput | |
| 318 | //! Metadata resource to be resolve. | |
| 319 | //! \return MOS_STATUS | |
| 320 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 321 | //! | |
| 322 | virtual MOS_STATUS ResolveMetaData(PMOS_RESOURCE pInput, PMOS_RESOURCE pOutput); | |
| 323 | ||
| 324 | //! | |
| 325 | //! \brief Gets hardware interface. | |
| 326 | //! \return CodechalHwInterface | |
| 327 | //! return hardware interface | |
| 328 | //! | |
| 329 | CodechalHwInterface * GetHwInterface() { return m_hwInterface; } | |
| 330 | ||
| 331 | //! | |
| 332 | //! \brief Gets OS interface. | |
| 333 | //! \return PMOS_INTERFACE | |
| 334 | //! return OS interface | |
| 335 | //! | |
| 336 | PMOS_INTERFACE GetOsInterface() { return m_osInterface; } | |
| 337 | ||
| 338 | //! | |
| 339 | //! \brief Gets debug interface. | |
| 340 | //! \return CodechalDebugInterface | |
| 341 | //! return debug interface | |
| 342 | //! | |
| 343 | CodechalDebugInterface * GetDebugInterface() { return m_debugInterface; } | |
| 344 | ||
| 345 | //! | |
| 346 | //! \brief Check if Apogeios enabled. | |
| 347 | //! \return bool | |
| 348 | //! return m_apogeiosEnable | |
| 349 | //! | |
| 350 | bool IsApogeiosEnabled() { return m_apogeiosEnable; } | |
| 351 | protected: | |
| 352 | //! \brief HW Inteface | |
| 353 | //! \details Responsible for constructing all defined states and commands. | |
| 354 | //! Each HAL has a separate OS interface. | |
| 355 | CodechalHwInterface *m_hwInterface = nullptr; | |
| 356 | ||
| 357 | //! \brief Os Inteface | |
| 358 | //! \details Used to abstract all OS and KMD interactions such that CodecHal may be | |
| 359 | //! OS agnostic. Each HAL has a separate OS interface. | |
| 360 | PMOS_INTERFACE m_osInterface = nullptr; | |
| 361 | ||
| 362 | //! \brief Interface used for debug dumps. | |
| 363 | //! \details This interface is only valid for release internal and debug builds. | |
| 364 | CodechalDebugInterface *m_debugInterface = nullptr; | |
| 365 | ||
| 366 | //! \brief Interface used for debug dumps in GetStatusReport. | |
| 367 | //! \details This interface is only valid for release internal and debug builds. | |
| 368 | CodechalDebugInterface *m_statusReportDebugInterface = nullptr; | |
| 369 | ||
| 370 | //! \brief Indicates whether or not using null hardware | |
| 371 | bool m_useNullHw[MOS_GPU_CONTEXT_MAX] = { false }; | |
| 372 | ||
| 373 | //! \brief Apogeios Enable Flag | |
| 374 | bool m_apogeiosEnable = false; | |
| 375 | }; | |
| 376 | ||
| 377 | //! | |
| 378 | 178 | //! \class CodechalResLock |
| 379 | 179 | //! \brief Help function to lock the resource, the resource will be unlock automatically when this class destroy. |
| 380 | 180 | //! |
| 89 | 89 | LoadGoldenReference(); |
| 90 | 90 | } |
| 91 | 91 | |
| 92 | MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData)); | |
| 92 | 93 | userFeatureData.i32Data = -1; |
| 93 | 94 | userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE; |
| 94 | 95 | MOS_UserFeature_ReadValue_ID( |
| 97 | 98 | &userFeatureData, |
| 98 | 99 | m_osInterface->pOsContext); |
| 99 | 100 | m_stopFrameNumber = userFeatureData.i32Data; |
| 101 | ||
| 102 | MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData)); | |
| 103 | userFeatureData.i32Data = 0; | |
| 104 | userFeatureData.i32DataFlag = MOS_USER_FEATURE_VALUE_DATA_FLAG_CUSTOM_DEFAULT_VALUE_TYPE; | |
| 105 | MOS_UserFeature_ReadValue_ID( | |
| 106 | nullptr, | |
| 107 | __MEDIA_USER_FEATURE_VALUE_CODECHAL_ENABLE_SW_CRC_ID, | |
| 108 | &userFeatureData, | |
| 109 | m_osInterface->pOsContext); | |
| 110 | m_swCRC = userFeatureData.i32Data == 0 ? false : true; | |
| 100 | 111 | #endif |
| 101 | 112 | |
| 102 | 113 | return MOS_STATUS_SUCCESS; |
| 1434 | 1434 | uint32_t yuvSize = 0; |
| 1435 | 1435 | |
| 1436 | 1436 | CheckDecodeOutputBufSize(*decodeParams->m_destSurface); |
| 1437 | ||
| 1438 | m_debugInterface->DumpYUVSurfaceToBuffer(decodeParams->m_destSurface, | |
| 1439 | m_decodeOutputBuf, | |
| 1440 | yuvSize); | |
| 1441 | uint32_t curIdx = (m_decodeStatusBuf.m_currIndex + CODECHAL_DECODE_STATUS_NUM - 1) % CODECHAL_DECODE_STATUS_NUM; | |
| 1442 | m_debugInterface->CaptureGoldenReference(m_decodeOutputBuf, yuvSize, m_decodeStatusBuf.m_decodeStatus[curIdx].m_mmioFrameCrcReg); | |
| 1443 | if (m_debugInterface->m_swCRC) | |
| 1444 | { | |
| 1437 | if (!m_debugInterface->m_swCRC) //HW CRC | |
| 1438 | { | |
| 1439 | uint32_t curIdx = (m_decodeStatusBuf.m_currIndex + CODECHAL_DECODE_STATUS_NUM - 1) % CODECHAL_DECODE_STATUS_NUM; | |
| 1440 | while (true) | |
| 1441 | { | |
| 1442 | uint32_t globalHWStoredData = *(m_decodeStatusBuf.m_data); | |
| 1443 | uint32_t globalCount = m_decodeStatusBuf.m_swStoreData - globalHWStoredData; | |
| 1444 | uint32_t localCount = m_decodeStatusBuf.m_decodeStatus[curIdx].m_swStoredData - globalHWStoredData; | |
| 1445 | if (localCount == 0 || localCount > globalCount) //Decode OK | |
| 1446 | { | |
| 1447 | m_debugInterface->CaptureGoldenReference(m_decodeOutputBuf, yuvSize, m_decodeStatusBuf.m_decodeStatus[curIdx].m_mmioFrameCrcReg); | |
| 1448 | break; | |
| 1449 | } | |
| 1450 | MOS_Sleep(1); | |
| 1451 | } | |
| 1452 | } | |
| 1453 | else //sw crc | |
| 1454 | { | |
| 1455 | m_debugInterface->DumpYUVSurfaceToBuffer(decodeParams->m_destSurface, | |
| 1456 | m_decodeOutputBuf, | |
| 1457 | yuvSize); | |
| 1458 | m_debugInterface->CaptureGoldenReference(m_decodeOutputBuf, yuvSize, 0); | |
| 1445 | 1459 | std::vector<MOS_RESOURCE> vRes = {m_crcBuf}; |
| 1446 | 1460 | m_debugInterface->DetectCorruptionSw(this, vRes, &m_frameCountTypeBuf, m_decodeOutputBuf, yuvSize, m_frameNum); |
| 1447 | 1461 | } |
| 597 | 597 | MHW_VDBOX_PIPE_BUF_ADDR_PARAMS pipeBufAddrParams; |
| 598 | 598 | pipeBufAddrParams.Mode = m_mode; |
| 599 | 599 | pipeBufAddrParams.psRawSurface = &m_rawSurface; // original picture to be encoded |
| 600 | pipeBufAddrParams.pRawSurfParam = &surfaceParams; | |
| 600 | 601 | |
| 601 | 602 | CODECHAL_ENCODE_CHK_NULL_RETURN(m_mmcState); |
| 602 | 603 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_mmcState->SetPipeBufAddr(&pipeBufAddrParams, &cmdBuffer)); |
| 1132 | 1132 | CODECHAL_ENCODE_PERFTAG_CALL_SCOREBOARD, |
| 1133 | 1133 | CODECHAL_ENCODE_PERFTAG_CALL_SFD_KERNEL, |
| 1134 | 1134 | CODECHAL_ENCODE_PERFTAG_CALL_PAK_ENGINE_SECOND_PASS, |
| 1135 | CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE_SECOND_PASS | |
| 1135 | CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE_SECOND_PASS, | |
| 1136 | CODECHAL_ENCODE_PERFTAG_CALL_HEVC_LA_UPDATE | |
| 1136 | 1137 | }; |
| 1137 | 1138 | |
| 1138 | 1139 | class CodechalEncodeWP; |
| 0 | /* | |
| 1 | * Copyright (c) 2011-2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codechal_setting.cpp | |
| 23 | //! \brief Implements class CodechalSetting | |
| 24 | //! | |
| 25 | ||
| 26 | #include "codechal_setting.h" | |
| 27 | ||
| 28 | ||
| 29 | CodechalSetting *CodechalSetting::CreateCodechalSetting() | |
| 30 | { | |
| 31 | return MOS_New(CodechalSetting); | |
| 32 | } | |
| 33 |
| 0 | /* | |
| 1 | * Copyright (c) 2011-2020, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codechal_setting.h | |
| 23 | //! \brief Defines class CodechalSetting | |
| 24 | //! | |
| 25 | #ifndef __CODECHAL_SETTING_H__ | |
| 26 | #define __CODECHAL_SETTING_H__ | |
| 27 | ||
| 28 | #include "codec_def_common.h" | |
| 29 | //! | |
| 30 | //! \class CodechalSetting | |
| 31 | //! \brief Settings used to finalize the creation of the CodecHal device | |
| 32 | //! | |
| 33 | class CodechalSetting | |
| 34 | { | |
| 35 | public: | |
| 36 | CODECHAL_FUNCTION codecFunction = CODECHAL_FUNCTION_INVALID; //!< High level codec functionality requested. | |
| 37 | /*! \brief Width requested. | |
| 38 | * | |
| 39 | * For encode this width must be the maximum width for the entire stream to be encoded, for decode dynamic allocation is supported and this width is the largest width recieved. | |
| 40 | */ | |
| 41 | uint32_t width = 0; | |
| 42 | /*! \brief Height requested. | |
| 43 | * | |
| 44 | * For encode this height must be the maximum height for the entire stream to be encoded, for decode dynamic allocation is supported and this height is the largest height recieved. | |
| 45 | */ | |
| 46 | uint32_t height = 0; | |
| 47 | uint32_t mode = 0; //!< Mode requested (high level combination between Standard and CodecFunction). | |
| 48 | uint32_t standard = 0; //!< Codec standard requested. | |
| 49 | uint8_t lumaChromaDepth = 0; //!< Applies currently to HEVC only, specifies bit depth as either 8 or 10 bits. | |
| 50 | uint8_t chromaFormat = 0; //!< Applies currently to HEVC/VP9 only, specifies chromaformat as 420/422/444. | |
| 51 | bool intelEntrypointInUse = false; //!< Applies to decode only, application is using a Intel-specific entrypoint. | |
| 52 | bool shortFormatInUse = false; //!< Applies to decode only, application is passing short format slice data. | |
| 53 | ||
| 54 | bool disableDecodeSyncLock = false; //!< Flag to indicate if Decode O/P can be locked for sync. | |
| 55 | ||
| 56 | // Decode Downsampling | |
| 57 | bool downsamplingHinted = false; //!< Applies to decode only, application may request field scaling. | |
| 58 | ||
| 59 | bool disableUltraHME = false; //!< Applies currently to HEVC VDEnc only to disable UHME | |
| 60 | bool disableSuperHME = false; //!< Applies currently to HEVC VDEnc only to disable SHME | |
| 61 | void *cpParams = nullptr; //!< CP params | |
| 62 | bool isMfeEnabled = false; //!< Flag to indicate if Mfe is enabled. | |
| 63 | ||
| 64 | // Decode SFC enabling | |
| 65 | bool sfcEnablingHinted = false; //!< Applies to decode only, application may request field sfc. | |
| 66 | bool sfcInUseHinted = false; //!< Applies to decode only, application may request sfc engine. | |
| 67 | bool enableCodecMmc = true; //!< Applies to both of decode and encode, to indicate if codec MMC could be enabled by default | |
| 68 | bool secureMode = false; //!< secure decoder is required if enabled | |
| 69 | ||
| 70 | // HEVC Encode only | |
| 71 | bool isSCCEnabled = false; //!< Flag to indicate if HEVC SCC is enabled. | |
| 72 | ||
| 73 | //! | |
| 74 | //! \brief Destructor | |
| 75 | //! | |
| 76 | virtual ~CodechalSetting(){}; | |
| 77 | ||
| 78 | //! | |
| 79 | //! \brief Return the pointer to CP parameters | |
| 80 | //! | |
| 81 | void *GetCpParams() { return cpParams; }; | |
| 82 | ||
| 83 | //! | |
| 84 | //! \brief Return the indicate if cenc advance is used or not | |
| 85 | //! | |
| 86 | virtual bool CheckCencAdvance() {return false; }; | |
| 87 | ||
| 88 | //! | |
| 89 | //! \brief Create CodechalSetting instance | |
| 90 | //! | |
| 91 | static CodechalSetting *CreateCodechalSetting(); | |
| 92 | }; | |
| 93 | ||
| 94 | #endif |
| 3656 | 3656 | return eStatus; |
| 3657 | 3657 | } |
| 3658 | 3658 | |
| 3659 | MOS_STATUS CodechalVdencAvcState::GetInterRounding(PMHW_VDBOX_AVC_SLICE_STATE sliceState) | |
| 3659 | MOS_STATUS CodechalVdencAvcState::SetRounding(PCODECHAL_ENCODE_AVC_ROUNDING_PARAMS param, PMHW_VDBOX_AVC_SLICE_STATE sliceState) | |
| 3660 | 3660 | { |
| 3661 | 3661 | MOS_STATUS eStatus = MOS_STATUS_SUCCESS; |
| 3662 | 3662 | |
| 3663 | 3663 | CODECHAL_ENCODE_FUNCTION_ENTER; |
| 3664 | 3664 | |
| 3665 | CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState); | |
| 3666 | CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState->pEncodeAvcSeqParams); | |
| 3667 | CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState->pEncodeAvcPicParams); | |
| 3668 | CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState->pEncodeAvcSliceParams); | |
| 3669 | ||
| 3670 | auto avcSeqParams = sliceState->pEncodeAvcSeqParams; | |
| 3671 | auto avcPicParams = sliceState->pEncodeAvcPicParams; | |
| 3672 | auto avcSliceParams = sliceState->pEncodeAvcSliceParams; | |
| 3673 | uint8_t sliceQP = avcPicParams->pic_init_qp_minus26 + 26 + avcSliceParams->slice_qp_delta; | |
| 3674 | ||
| 3675 | switch (Slice_Type[avcSliceParams->slice_type]) | |
| 3676 | { | |
| 3677 | case SLICE_P: | |
| 3678 | if (m_roundingInterP == CODECHAL_ENCODE_AVC_INVALID_ROUNDING) | |
| 3679 | { | |
| 3680 | // Adaptive Rounding is only used in CQP case | |
| 3681 | if (m_adaptiveRoundingInterEnable && !m_vdencBrcEnabled) | |
| 3665 | if (param != nullptr && param->bEnableCustomRoudingIntra) | |
| 3666 | { | |
| 3667 | sliceState->dwRoundingIntraValue = param->dwRoundingIntra; | |
| 3668 | } | |
| 3669 | else | |
| 3670 | { | |
| 3671 | sliceState->dwRoundingIntraValue = 5; | |
| 3672 | } | |
| 3673 | ||
| 3674 | if (param != nullptr && param->bEnableCustomRoudingInter) | |
| 3675 | { | |
| 3676 | sliceState->bRoundingInterEnable = true; | |
| 3677 | sliceState->dwRoundingValue = param->dwRoundingInter; | |
| 3678 | } | |
| 3679 | else | |
| 3680 | { | |
| 3681 | sliceState->bRoundingInterEnable = m_roundingInterEnable; | |
| 3682 | ||
| 3683 | CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState); | |
| 3684 | CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState->pEncodeAvcSeqParams); | |
| 3685 | CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState->pEncodeAvcPicParams); | |
| 3686 | CODECHAL_ENCODE_CHK_NULL_RETURN(sliceState->pEncodeAvcSliceParams); | |
| 3687 | ||
| 3688 | auto avcSeqParams = sliceState->pEncodeAvcSeqParams; | |
| 3689 | auto avcPicParams = sliceState->pEncodeAvcPicParams; | |
| 3690 | auto avcSliceParams = sliceState->pEncodeAvcSliceParams; | |
| 3691 | uint8_t sliceQP = avcPicParams->pic_init_qp_minus26 + 26 + avcSliceParams->slice_qp_delta; | |
| 3692 | ||
| 3693 | switch (Slice_Type[avcSliceParams->slice_type]) | |
| 3694 | { | |
| 3695 | case SLICE_P: | |
| 3696 | if (m_roundingInterP == CODECHAL_ENCODE_AVC_INVALID_ROUNDING) | |
| 3682 | 3697 | { |
| 3683 | // If IPPP scenario | |
| 3684 | if (avcSeqParams->GopRefDist == 1) | |
| 3698 | // Adaptive Rounding is only used in CQP case | |
| 3699 | if (m_adaptiveRoundingInterEnable && !m_vdencBrcEnabled) | |
| 3685 | 3700 | { |
| 3686 | sliceState->dwRoundingValue = CodechalVdencAvcState::AdaptiveInterRoundingPWithoutB[sliceQP]; | |
| 3701 | // If IPPP scenario | |
| 3702 | if (avcSeqParams->GopRefDist == 1) | |
| 3703 | { | |
| 3704 | sliceState->dwRoundingValue = CodechalVdencAvcState::AdaptiveInterRoundingPWithoutB[sliceQP]; | |
| 3705 | } | |
| 3706 | else | |
| 3707 | { | |
| 3708 | sliceState->dwRoundingValue = CodechalVdencAvcState::AdaptiveInterRoundingP[sliceQP]; | |
| 3709 | } | |
| 3687 | 3710 | } |
| 3688 | 3711 | else |
| 3689 | 3712 | { |
| 3690 | sliceState->dwRoundingValue = CodechalVdencAvcState::AdaptiveInterRoundingP[sliceQP]; | |
| 3713 | sliceState->dwRoundingValue = CodechalVdencAvcState::InterRoundingP[avcSeqParams->TargetUsage]; | |
| 3691 | 3714 | } |
| 3692 | 3715 | } |
| 3693 | 3716 | else |
| 3694 | 3717 | { |
| 3695 | sliceState->dwRoundingValue = CodechalVdencAvcState::InterRoundingP[avcSeqParams->TargetUsage]; | |
| 3718 | sliceState->dwRoundingValue = m_roundingInterP; | |
| 3696 | 3719 | } |
| 3697 | } | |
| 3698 | else | |
| 3699 | { | |
| 3700 | sliceState->dwRoundingValue = m_roundingInterP; | |
| 3701 | } | |
| 3702 | break; | |
| 3703 | case SLICE_B: | |
| 3704 | if (m_refList[m_currReconstructedPic.FrameIdx]->bUsedAsRef) | |
| 3705 | { | |
| 3706 | sliceState->dwRoundingValue = InterRoundingBRef[avcSeqParams->TargetUsage]; | |
| 3707 | } | |
| 3708 | else | |
| 3709 | { | |
| 3710 | if (m_adaptiveRoundingInterEnable && !m_vdencBrcEnabled) | |
| 3720 | break; | |
| 3721 | case SLICE_B: | |
| 3722 | if (m_refList[m_currReconstructedPic.FrameIdx]->bUsedAsRef) | |
| 3711 | 3723 | { |
| 3712 | sliceState->dwRoundingValue = AdaptiveInterRoundingB[sliceQP]; | |
| 3724 | sliceState->dwRoundingValue = InterRoundingBRef[avcSeqParams->TargetUsage]; | |
| 3713 | 3725 | } |
| 3714 | 3726 | else |
| 3715 | 3727 | { |
| 3716 | sliceState->dwRoundingValue = InterRoundingB[avcSeqParams->TargetUsage]; | |
| 3728 | if (m_adaptiveRoundingInterEnable && !m_vdencBrcEnabled) | |
| 3729 | { | |
| 3730 | sliceState->dwRoundingValue = AdaptiveInterRoundingB[sliceQP]; | |
| 3731 | } | |
| 3732 | else | |
| 3733 | { | |
| 3734 | sliceState->dwRoundingValue = InterRoundingB[avcSeqParams->TargetUsage]; | |
| 3735 | } | |
| 3717 | 3736 | } |
| 3718 | } | |
| 3719 | break; | |
| 3720 | default: | |
| 3721 | // do nothing | |
| 3722 | break; | |
| 3737 | break; | |
| 3738 | default: | |
| 3739 | // do nothing | |
| 3740 | break; | |
| 3741 | } | |
| 3723 | 3742 | } |
| 3724 | 3743 | |
| 3725 | 3744 | return eStatus; |
| 4968 | 4987 | CODECHAL_ENCODE_CHK_STATUS_RETURN(SendPrologWithFrameTracking( |
| 4969 | 4988 | &cmdBuffer, bRequestFrameTracking, validMmio ? &mmioRegister: nullptr)); |
| 4970 | 4989 | } |
| 4990 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_perfProfiler->AddPerfCollectStartCmd((void*)this, m_osInterface, m_miInterface, &cmdBuffer)); | |
| 4971 | 4991 | |
| 4972 | 4992 | // load kernel from WOPCM into L2 storage RAM |
| 4973 | 4993 | MHW_VDBOX_HUC_IMEM_STATE_PARAMS imemParams; |
| 5022 | 5042 | flushDwParams.bVideoPipelineCacheInvalidate = true; |
| 5023 | 5043 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd(&cmdBuffer, &flushDwParams)); |
| 5024 | 5044 | |
| 5045 | // Collect HuC Init/Reset kernel performance data | |
| 5046 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_perfProfiler->AddPerfCollectEndCmd((void*)this, m_osInterface, m_miInterface, &cmdBuffer)); | |
| 5047 | ||
| 5025 | 5048 | // Handle HUC_STATUS error codes |
| 5026 | 5049 | CODECHAL_ENCODE_CHK_STATUS_RETURN(AddHucOutputRegistersHandling(mmioRegisters, &cmdBuffer, true)); |
| 5027 | 5050 | |
| 5078 | 5101 | CODECHAL_ENCODE_CHK_STATUS_RETURN( |
| 5079 | 5102 | SendPrologWithFrameTracking(&cmdBuffer, bRequestFrameTracking, validMmio ? &mmioRegister : nullptr)); |
| 5080 | 5103 | } |
| 5104 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_perfProfiler->AddPerfCollectStartCmd((void*)this, m_osInterface, m_miInterface, &cmdBuffer)); | |
| 5081 | 5105 | |
| 5082 | 5106 | if (m_brcInit || m_brcReset) |
| 5083 | 5107 | { |
| 5254 | 5278 | storeRegParams.dwOffset = 0; |
| 5255 | 5279 | storeRegParams.dwRegister = mmioRegisters->hucStatusRegOffset; |
| 5256 | 5280 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(&cmdBuffer, &storeRegParams)); |
| 5281 | ||
| 5282 | // Collect HuC Update kernel performance data | |
| 5283 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_perfProfiler->AddPerfCollectEndCmd((void*)this, m_osInterface, m_miInterface, &cmdBuffer)); | |
| 5257 | 5284 | |
| 5258 | 5285 | // Handle HUC_STATUS error codes |
| 5259 | 5286 | CODECHAL_ENCODE_CHK_STATUS_RETURN(AddHucOutputRegistersHandling(mmioRegisters, &cmdBuffer, true)); |
| 5858 | 5885 | if (m_vdencBrcEnabled) |
| 5859 | 5886 | { |
| 5860 | 5887 | PerfTagSetting perfTag; |
| 5861 | perfTag.Value = 0; | |
| 5862 | perfTag.Mode = (uint16_t)m_mode & CODECHAL_ENCODE_MODE_BIT_MASK; | |
| 5863 | // STF: HuC+VDEnc+PAK single BB, non-STF: HuC Init/HuC Update/(VDEnc+PAK) in separate BBs | |
| 5864 | perfTag.CallType = m_singleTaskPhaseSupported ? CODECHAL_ENCODE_PERFTAG_CALL_PAK_ENGINE : CODECHAL_ENCODE_PERFTAG_CALL_BRC_INIT_RESET; | |
| 5888 | perfTag.Value = 0; | |
| 5889 | perfTag.Mode = (uint16_t)m_mode & CODECHAL_ENCODE_MODE_BIT_MASK; | |
| 5890 | perfTag.CallType = CODECHAL_ENCODE_PERFTAG_CALL_BRC_INIT_RESET; | |
| 5865 | 5891 | perfTag.PictureCodingType = m_pictureCodingType; |
| 5866 | 5892 | m_osInterface->pfnSetPerfTag(m_osInterface, perfTag.Value); |
| 5867 | 5893 | |
| 5887 | 5913 | CODECHAL_ENCODE_CHK_STATUS_RETURN(HuCBrcInitReset()); |
| 5888 | 5914 | } |
| 5889 | 5915 | |
| 5890 | if (!m_singleTaskPhaseSupported) | |
| 5891 | { | |
| 5892 | perfTag.CallType = CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE; | |
| 5893 | m_osInterface->pfnSetPerfTag(m_osInterface, perfTag.Value); | |
| 5894 | } | |
| 5916 | perfTag.CallType = m_currPass == 0 ? CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE : CODECHAL_ENCODE_PERFTAG_CALL_BRC_UPDATE_SECOND_PASS; | |
| 5917 | m_osInterface->pfnSetPerfTag(m_osInterface, perfTag.Value); | |
| 5895 | 5918 | |
| 5896 | 5919 | // Invoke BRC update FW |
| 5897 | 5920 | CODECHAL_ENCODE_CHK_STATUS_RETURN(HuCBrcUpdate()); |
| 5901 | 5924 | PerfTagSetting perfTag; |
| 5902 | 5925 | perfTag.Value = 0; |
| 5903 | 5926 | perfTag.Mode = (uint16_t)m_mode & CODECHAL_ENCODE_MODE_BIT_MASK; |
| 5904 | perfTag.CallType = CODECHAL_ENCODE_PERFTAG_CALL_PAK_ENGINE; | |
| 5927 | perfTag.CallType = m_currPass == 0 ? CODECHAL_ENCODE_PERFTAG_CALL_PAK_ENGINE : CODECHAL_ENCODE_PERFTAG_CALL_PAK_ENGINE_SECOND_PASS; | |
| 5905 | 5928 | perfTag.PictureCodingType = m_pictureCodingType; |
| 5906 | 5929 | m_osInterface->pfnSetPerfTag(m_osInterface, perfTag.Value); |
| 5907 | 5930 | |
| 6021 | 6044 | surfaceParams.Mode = m_mode; |
| 6022 | 6045 | surfaceParams.ucSurfaceStateId = CODECHAL_MFX_SRC_SURFACE_ID; |
| 6023 | 6046 | surfaceParams.psSurface = m_rawSurfaceToPak; |
| 6024 | surfaceParams.dwActualHeight = surfaceParams.psSurface->dwHeight; | |
| 6025 | surfaceParams.dwActualWidth = surfaceParams.psSurface->dwWidth; | |
| 6047 | surfaceParams.dwActualHeight = m_avcSeqParam->FrameHeight; | |
| 6048 | surfaceParams.dwActualWidth = m_avcSeqParam->FrameWidth; | |
| 6026 | 6049 | surfaceParams.bDisplayFormatSwizzle = m_avcPicParam->bDisplayFormatSwizzle; |
| 6027 | 6050 | surfaceParams.bColorSpaceSelection = (m_avcSeqParam->InputColorSpace == ECOLORSPACE_P709) ? 1 : 0; |
| 6028 | 6051 | CODECHAL_DEBUG_TOOL(m_debugInterface->DumpSurfaceInfo(m_rawSurfaceToPak, "RawSurfaceToPak")); |
| 6341 | 6364 | sliceState.dwBatchBufferForPakSlicesStartOffset = batchBufferForPakSlicesStartOffset; |
| 6342 | 6365 | } |
| 6343 | 6366 | |
| 6344 | if (m_avcRoundingParams != nullptr && m_avcRoundingParams->bEnableCustomRoudingIntra) | |
| 6345 | { | |
| 6346 | sliceState.dwRoundingIntraValue = m_avcRoundingParams->dwRoundingIntra; | |
| 6347 | } | |
| 6348 | else | |
| 6349 | { | |
| 6350 | sliceState.dwRoundingIntraValue = 5; | |
| 6351 | } | |
| 6352 | if (m_avcRoundingParams != nullptr && m_avcRoundingParams->bEnableCustomRoudingInter) | |
| 6353 | { | |
| 6354 | sliceState.bRoundingInterEnable = true; | |
| 6355 | sliceState.dwRoundingValue = m_avcRoundingParams->dwRoundingInter; | |
| 6356 | } | |
| 6357 | else | |
| 6358 | { | |
| 6359 | sliceState.bRoundingInterEnable = m_roundingInterEnable; | |
| 6360 | CODECHAL_ENCODE_CHK_STATUS_RETURN(GetInterRounding(&sliceState)); | |
| 6361 | } | |
| 6367 | CODECHAL_ENCODE_CHK_STATUS_RETURN(SetRounding(m_avcRoundingParams, &sliceState)); | |
| 6362 | 6368 | |
| 6363 | 6369 | sliceState.oneOnOneMapping = m_oneOnOneMapping; |
| 6364 | 6370 | CODECHAL_ENCODE_CHK_STATUS_RETURN(SendSlice(&cmdBuffer, &sliceState)); |
| 6968 | 6974 | if (m_nonNativeBrcRoiSupported) |
| 6969 | 6975 | { |
| 6970 | 6976 | // BRC ROI Buffer |
| 6971 | allocParamsForBufferLinear.dwBytes = m_picWidthInMb * m_picHeightInMb; | |
| 6977 | allocParamsForBufferLinear.dwBytes = MOS_ALIGN_CEIL(m_picWidthInMb * m_picHeightInMb, MHW_CACHELINE_SIZE); | |
| 6972 | 6978 | allocParamsForBufferLinear.pBufName = "VDENC BRC ROI Buffer"; |
| 6973 | 6979 | |
| 6974 | 6980 | for (uint32_t i = 0; i < CODECHAL_ENCODE_RECYCLED_BUFFER_NUM; i++) |
| 7915 | 7921 | CODECHAL_ENCODE_CHK_COND_RETURN((m_vdboxIndex > m_hwInterface->GetMfxInterface()->GetMaxVdboxIndex()), "ERROR - vdbox index exceed the maximum"); |
| 7916 | 7922 | MmioRegistersMfx *mmioRegisters = m_hwInterface->SelectVdboxAndGetMmioRegister(m_vdboxIndex, cmdBuffer); |
| 7917 | 7923 | |
| 7918 | // Special processing for one slice case (to avoid limitations for multi-slice configuration) | |
| 7919 | if (m_numSlices == 1) | |
| 7920 | { | |
| 7921 | MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParamsAVC; | |
| 7922 | MOS_ZeroMemory(&miStoreRegMemParamsAVC, sizeof(miStoreRegMemParamsAVC)); | |
| 7923 | miStoreRegMemParamsAVC.presStoreBuffer = presSliceSizeStreamoutBuffer; | |
| 7924 | miStoreRegMemParamsAVC.dwOffset = 0; | |
| 7925 | ||
| 7926 | miStoreRegMemParamsAVC.dwRegister = mmioRegisters->mfcBitstreamBytecountFrameRegOffset; | |
| 7927 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParamsAVC)); | |
| 7928 | } | |
| 7929 | ||
| 7930 | 7924 | MHW_MI_STORE_DATA_PARAMS storeDataParams; |
| 7931 | 7925 | MOS_ZeroMemory(&storeDataParams, sizeof(storeDataParams)); |
| 7932 | 7926 | storeDataParams.pOsResource = presMetadataBuffer; |
| 7938 | 7932 | storeDataParams.dwValue = m_numSlices; |
| 7939 | 7933 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams)); |
| 7940 | 7934 | |
| 7941 | MHW_MI_COPY_MEM_MEM_PARAMS miCpyMemMemParams; | |
| 7942 | MOS_ZeroMemory(&miCpyMemMemParams, sizeof(miCpyMemMemParams)); | |
| 7943 | for (uint16_t slcCount = 0; slcCount < m_numSlices; slcCount++) | |
| 7944 | { | |
| 7945 | uint32_t subRegionSartOffset = m_metaDataOffset.dwMetaDataSize + slcCount * m_metaDataOffset.dwMetaDataSubRegionSize; | |
| 7946 | ||
| 7947 | storeDataParams.dwResourceOffset = subRegionSartOffset + m_metaDataOffset.dwbStartOffset; | |
| 7948 | storeDataParams.dwValue = m_slcData[slcCount].SliceOffset; | |
| 7935 | MHW_MI_LOAD_REGISTER_MEM_PARAMS miLoadRegMemParams; | |
| 7936 | MHW_MI_LOAD_REGISTER_IMM_PARAMS miLoadRegImmParams; | |
| 7937 | MHW_MI_MATH_PARAMS miMathParams; | |
| 7938 | MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams; | |
| 7939 | for (uint16_t slcCount = 0; slcCount < m_numSlices; ++slcCount) | |
| 7940 | { | |
| 7941 | uint32_t subRegionStartOffset = m_metaDataOffset.dwMetaDataSize + slcCount * m_metaDataOffset.dwMetaDataSubRegionSize; | |
| 7942 | ||
| 7943 | storeDataParams.dwResourceOffset = subRegionStartOffset + m_metaDataOffset.dwbStartOffset; | |
| 7944 | storeDataParams.dwValue = 0; //m_slcData[slcCount].SliceOffset; | |
| 7949 | 7945 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams)); |
| 7950 | 7946 | |
| 7951 | storeDataParams.dwResourceOffset = subRegionSartOffset + m_metaDataOffset.dwbHeaderSize; | |
| 7947 | storeDataParams.dwResourceOffset = subRegionStartOffset + m_metaDataOffset.dwbHeaderSize; | |
| 7952 | 7948 | storeDataParams.dwValue = m_slcData[slcCount].BitSize; |
| 7953 | 7949 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreDataImmCmd(cmdBuffer, &storeDataParams)); |
| 7954 | 7950 | |
| 7955 | miCpyMemMemParams.presSrc = presSliceSizeStreamoutBuffer; | |
| 7956 | miCpyMemMemParams.presDst = presMetadataBuffer; | |
| 7957 | miCpyMemMemParams.dwSrcOffset = slcCount * 2; | |
| 7958 | miCpyMemMemParams.dwDstOffset = subRegionSartOffset + m_metaDataOffset.dwbSize; | |
| 7959 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiCopyMemMemCmd(cmdBuffer, &miCpyMemMemParams)); | |
| 7960 | } | |
| 7961 | ||
| 7962 | MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParams; | |
| 7951 | // reg0Lo = (SlcCount)thSliceSize con (slcCount-1)thSliceSize | |
| 7952 | miLoadRegMemParams.presStoreBuffer = presSliceSizeStreamoutBuffer; | |
| 7953 | miLoadRegMemParams.dwOffset = (slcCount / 2) * 4; | |
| 7954 | miLoadRegMemParams.dwRegister = mmioRegisters->generalPurposeRegister0LoOffset; | |
| 7955 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterMemCmd(cmdBuffer, &miLoadRegMemParams)); | |
| 7956 | miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister0HiOffset; | |
| 7957 | miLoadRegImmParams.dwData = 0; | |
| 7958 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams)); | |
| 7959 | ||
| 7960 | // reg4Lo = mask | |
| 7961 | miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4LoOffset; | |
| 7962 | miLoadRegImmParams.dwData = (slcCount & 1) ? 0xFFFF0000 : 0x0000FFFF; | |
| 7963 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams)); | |
| 7964 | miLoadRegImmParams.dwData = 0; | |
| 7965 | miLoadRegImmParams.dwRegister = mmioRegisters->generalPurposeRegister4HiOffset; | |
| 7966 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams)); | |
| 7967 | ||
| 7968 | MHW_MI_ALU_PARAMS aluParams[4 + 16 * 4]; | |
| 7969 | int aluCount = 0; | |
| 7970 | ||
| 7971 | // load SrcA, reg0 | |
| 7972 | aluParams[aluCount].AluOpcode = MHW_MI_ALU_LOAD; | |
| 7973 | aluParams[aluCount].Operand1 = MHW_MI_ALU_SRCA; | |
| 7974 | aluParams[aluCount].Operand2 = MHW_MI_ALU_GPREG0; | |
| 7975 | ++aluCount; | |
| 7976 | // load SrcB, reg4 | |
| 7977 | aluParams[aluCount].AluOpcode = MHW_MI_ALU_LOAD; | |
| 7978 | aluParams[aluCount].Operand1 = MHW_MI_ALU_SRCB; | |
| 7979 | aluParams[aluCount].Operand2 = MHW_MI_ALU_GPREG4; | |
| 7980 | ++aluCount; | |
| 7981 | // and SrcA, SrcB | |
| 7982 | aluParams[aluCount].AluOpcode = MHW_MI_ALU_AND; | |
| 7983 | ++aluCount; | |
| 7984 | // >> 16 | |
| 7985 | if (slcCount & 1) | |
| 7986 | { | |
| 7987 | for (int i = 0; i < 16; ++i) | |
| 7988 | { | |
| 7989 | // store reg0, accu | |
| 7990 | aluParams[aluCount].AluOpcode = MHW_MI_ALU_STORE; | |
| 7991 | aluParams[aluCount].Operand1 = MHW_MI_ALU_GPREG0; | |
| 7992 | aluParams[aluCount].Operand2 = MHW_MI_ALU_ACCU; | |
| 7993 | ++aluCount; | |
| 7994 | // load SrcA, accu | |
| 7995 | aluParams[aluCount].AluOpcode = MHW_MI_ALU_LOAD; | |
| 7996 | aluParams[aluCount].Operand1 = MHW_MI_ALU_SRCA; | |
| 7997 | aluParams[aluCount].Operand2 = MHW_MI_ALU_GPREG0; | |
| 7998 | ++aluCount; | |
| 7999 | // load SrcB, accu | |
| 8000 | aluParams[aluCount].AluOpcode = MHW_MI_ALU_LOAD; | |
| 8001 | aluParams[aluCount].Operand1 = MHW_MI_ALU_SRCB; | |
| 8002 | aluParams[aluCount].Operand2 = MHW_MI_ALU_GPREG0; | |
| 8003 | ++aluCount; | |
| 8004 | // add SrcA, SrcB | |
| 8005 | aluParams[aluCount].AluOpcode = MHW_MI_ALU_ADD; | |
| 8006 | ++aluCount; | |
| 8007 | } | |
| 8008 | } | |
| 8009 | // store reg0, accu | |
| 8010 | aluParams[aluCount].AluOpcode = MHW_MI_ALU_STORE; | |
| 8011 | aluParams[aluCount].Operand1 = MHW_MI_ALU_GPREG0; | |
| 8012 | aluParams[aluCount].Operand2 = MHW_MI_ALU_ACCU; | |
| 8013 | ++aluCount; | |
| 8014 | ||
| 8015 | miMathParams.dwNumAluParams = aluCount; | |
| 8016 | miMathParams.pAluPayload = aluParams; | |
| 8017 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiMathCmd(cmdBuffer, &miMathParams)); | |
| 8018 | ||
| 8019 | // Store from reg0Lo/Hi to presMetadataBuffer | |
| 8020 | MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams)); | |
| 8021 | miStoreRegMemParams.presStoreBuffer = presMetadataBuffer; | |
| 8022 | miStoreRegMemParams.dwOffset = subRegionStartOffset + m_metaDataOffset.dwbSize; | |
| 8023 | miStoreRegMemParams.dwRegister = (slcCount & 1) ? mmioRegisters->generalPurposeRegister0HiOffset : mmioRegisters->generalPurposeRegister0LoOffset; | |
| 8024 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams)); | |
| 8025 | ||
| 8026 | MHW_MI_FLUSH_DW_PARAMS flushDwParams; | |
| 8027 | MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams)); | |
| 8028 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiFlushDwCmd( | |
| 8029 | cmdBuffer, | |
| 8030 | &flushDwParams)); | |
| 8031 | } | |
| 8032 | ||
| 8033 | // Special processing for one slice case (to avoid limitations for multi-slice configuration) | |
| 8034 | // It is a temporary solution. Need to implement programming via mfcBitstreamBytecountSliceRegOffset register | |
| 8035 | // But it is possible to use this programming for slice conformance feature in the future | |
| 8036 | if (m_numSlices == 1) | |
| 8037 | { | |
| 8038 | MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParamsAVC; | |
| 8039 | MOS_ZeroMemory(&miStoreRegMemParamsAVC, sizeof(miStoreRegMemParamsAVC)); | |
| 8040 | miStoreRegMemParamsAVC.presStoreBuffer = presMetadataBuffer; | |
| 8041 | miStoreRegMemParamsAVC.dwOffset = m_metaDataOffset.dwMetaDataSize + m_metaDataOffset.dwbSize; // overwrite | |
| 8042 | ||
| 8043 | miStoreRegMemParamsAVC.dwRegister = mmioRegisters->mfcBitstreamBytecountFrameRegOffset; | |
| 8044 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParamsAVC)); | |
| 8045 | } | |
| 8046 | ||
| 7963 | 8047 | MOS_ZeroMemory(&miStoreRegMemParams, sizeof(miStoreRegMemParams)); |
| 7964 | 8048 | miStoreRegMemParams.presStoreBuffer = presMetadataBuffer; |
| 7965 | 8049 | miStoreRegMemParams.dwOffset = m_metaDataOffset.dwEncodedBitstreamWrittenBytesCount; |
| 7966 | miStoreRegMemParams.dwRegister = mmioRegisters->mfcBitstreamBytecountFrameRegOffset; | |
| 8050 | miStoreRegMemParams.dwRegister = mmioRegisters->mfcBitstreamBytecountFrameRegOffset; | |
| 7967 | 8051 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParams)); |
| 7968 | 8052 | |
| 7969 | 8053 | // Statistics |
| 7980 | 8064 | } |
| 7981 | 8065 | |
| 7982 | 8066 | MOS_RESOURCE *pPakFrameStat = (m_perMBStreamOutEnable) ? &m_pakStatsBufferFull : &m_pakStatsBuffer; //& m_resFrameStatStreamOutBuffer; or m_pakStatsBuffer |
| 7983 | MHW_MI_LOAD_REGISTER_IMM_PARAMS miLoadRegImmParams; | |
| 7984 | MHW_MI_LOAD_REGISTER_MEM_PARAMS miLoadRegMemParams; | |
| 7985 | 8067 | MHW_MI_LOAD_REGISTER_REG_PARAMS miLoadRegRegParams; |
| 7986 | 8068 | MHW_MI_FLUSH_DW_PARAMS flushDwParams; |
| 7987 | 8069 | |
| 7988 | 8070 | MOS_ZeroMemory(&flushDwParams, sizeof(flushDwParams)); |
| 8071 | MOS_ZeroMemory(&miLoadRegMemParams, sizeof(miLoadRegMemParams)); | |
| 8072 | MOS_ZeroMemory(&miLoadRegImmParams, sizeof(miLoadRegImmParams)); | |
| 7989 | 8073 | |
| 7990 | 8074 | /*** Intra/Inter/Skip statistics counted by number of MBs (not sub-blocks) ***/ |
| 7991 | 8075 | |
| 8009 | 8093 | miLoadRegImmParams.dwData = 0; |
| 8010 | 8094 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiLoadRegisterImmCmd(cmdBuffer, &miLoadRegImmParams)); |
| 8011 | 8095 | |
| 8012 | MHW_MI_MATH_PARAMS miMathParams; | |
| 8096 | MOS_ZeroMemory(&miMathParams, sizeof(miMathParams)); | |
| 8097 | ||
| 8013 | 8098 | MHW_MI_ALU_PARAMS aluParams[4 + 16 * 4]; |
| 8014 | 8099 | int aluCount; |
| 8015 | 8100 | |
| 376 | 376 | virtual MOS_STATUS ValidateNumReferences( PCODECHAL_ENCODE_AVC_VALIDATE_NUM_REFS_PARAMS params); |
| 377 | 377 | |
| 378 | 378 | //! |
| 379 | //! \brief Get inter rounding value. | |
| 380 | //! | |
| 381 | //! \param [in] sliceState | |
| 379 | //! \brief Set intra/inter rounding value. | |
| 380 | //! | |
| 381 | //! \param [in] rounding | |
| 382 | //! Pointer to CODECHAL_ENCODE_AVC_ROUNDING_PARAMS | |
| 383 | //! | |
| 384 | //! \param [out] sliceState | |
| 382 | 385 | //! Pointer to MHW_VDBOX_AVC_SLICE_STATE |
| 383 | 386 | //! |
| 384 | 387 | //! \return MOS_STATUS |
| 385 | 388 | //! MOS_STATUS_SUCCESS if success, else fail reason |
| 386 | 389 | //! |
| 387 | virtual MOS_STATUS GetInterRounding( PMHW_VDBOX_AVC_SLICE_STATE sliceState); | |
| 390 | virtual MOS_STATUS SetRounding(PCODECHAL_ENCODE_AVC_ROUNDING_PARAMS param, PMHW_VDBOX_AVC_SLICE_STATE sliceState); | |
| 388 | 391 | |
| 389 | 392 | //! |
| 390 | 393 | //! \brief Get Skip Bias Adjustment. |
| 19 | 19 | |
| 20 | 20 | # common |
| 21 | 21 | set(TMP_1_SOURCES_ |
| 22 | ${CMAKE_CURRENT_LIST_DIR}/codechal.cpp | |
| 23 | 22 | ${CMAKE_CURRENT_LIST_DIR}/codechal_hw.cpp |
| 24 | 23 | ${CMAKE_CURRENT_LIST_DIR}/codechal_utilities.cpp |
| 25 | 24 | ${CMAKE_CURRENT_LIST_DIR}/codechal_mmc.cpp |
| 50 | 49 | ) |
| 51 | 50 | endif() |
| 52 | 51 | |
| 53 | if(NOT "${Media_Reserved}" STREQUAL "yes") | |
| 54 | set(TMP_1_SOURCES_ | |
| 55 | ${TMP_1_SOURCES_} | |
| 56 | ${CMAKE_CURRENT_LIST_DIR}/codechal_setting.cpp | |
| 57 | ) | |
| 58 | endif() | |
| 59 | 52 | set(TMP_1_HEADERS_ |
| 60 | 53 | ${TMP_1_HEADERS_} |
| 61 | ${CMAKE_CURRENT_LIST_DIR}/codechal_setting.h | |
| 62 | 54 | ) |
| 63 | 55 | |
| 64 | 56 | #decode |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_avc.h | |
| 23 | //! \brief Defines basic AVC types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details This is the base header for all codec_def AVC files. All codec_def AVC files should include this file which should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_AVC_H__ | |
| 27 | #define __CODEC_DEF_COMMON_AVC_H__ | |
| 28 | ||
| 29 | #include "codec_def_common.h" | |
| 30 | ||
| 31 | #define CODEC_AVC_MAX_NUM_REF_FRAME 16 | |
| 32 | #define CODEC_AVC_NUM_REF_LISTS 2 | |
| 33 | #define CODEC_AVC_NUM_REF_DMV_BUFFERS (CODEC_AVC_MAX_NUM_REF_FRAME + 1) // Max 16 references + 1 for the current frame | |
| 34 | #define CODEC_AVC_NUM_DMV_BUFFERS (CODEC_AVC_NUM_REF_DMV_BUFFERS + 1) // 1 for non-reference | |
| 35 | #define CODEC_AVC_NUM_INIT_DMV_BUFFERS 4 | |
| 36 | ||
| 37 | #define CODEC_MAX_NUM_REF_FIELD (CODEC_MAX_NUM_REF_FRAME * CODEC_NUM_FIELDS_PER_FRAME) | |
| 38 | #define CODEC_AVC_MAX_SPS_NUM 32 | |
| 39 | #define CODEC_AVC_MAX_PPS_NUM 255 | |
| 40 | ||
| 41 | #define CODEC_AVC_NUM_UNCOMPRESSED_SURFACE 128 // 7 bits | |
| 42 | ||
| 43 | //! | |
| 44 | //! \enum CODEC_AVC_WEIGHT_SCALE_SIZE | |
| 45 | //! \brief Codec AVC weight scale size | |
| 46 | //! | |
| 47 | enum CODEC_AVC_WEIGHT_SCALE_SIZE | |
| 48 | { | |
| 49 | CODEC_AVC_WEIGHT_SCALE_4x4 = 24, | |
| 50 | CODEC_AVC_WEIGHT_SCALE_8x8 = 32, | |
| 51 | CODEC_AVC_WEIGHT_SCALE = 56 | |
| 52 | }; | |
| 53 | ||
| 54 | typedef enum | |
| 55 | { | |
| 56 | CODEC_AVC_BASE_PROFILE = 66, | |
| 57 | CODEC_AVC_MAIN_PROFILE = 77, | |
| 58 | CODEC_AVC_EXTENDED_PROFILE = 88, | |
| 59 | CODEC_AVC_HIGH_PROFILE = 100, | |
| 60 | CODEC_AVC_HIGH10_PROFILE = 110, | |
| 61 | CODEC_AVC_HIGH422_PROFILE = 122, | |
| 62 | CODEC_AVC_HIGH444_PROFILE = 244, | |
| 63 | CODEC_AVC_CAVLC444_INTRA_PROFILE = 44, | |
| 64 | CODEC_AVC_SCALABLE_BASE_PROFILE = 83, | |
| 65 | CODEC_AVC_SCALABLE_HIGH_PROFILE = 86 | |
| 66 | } CODEC_AVC_PROFILE_IDC; | |
| 67 | ||
| 68 | typedef enum | |
| 69 | { | |
| 70 | CODEC_AVC_LEVEL_1 = 10, | |
| 71 | CODEC_AVC_LEVEL_1b = 9, | |
| 72 | CODEC_AVC_LEVEL_11 = 11, | |
| 73 | CODEC_AVC_LEVEL_12 = 12, | |
| 74 | CODEC_AVC_LEVEL_13 = 13, | |
| 75 | CODEC_AVC_LEVEL_2 = 20, | |
| 76 | CODEC_AVC_LEVEL_21 = 21, | |
| 77 | CODEC_AVC_LEVEL_22 = 22, | |
| 78 | CODEC_AVC_LEVEL_3 = 30, | |
| 79 | CODEC_AVC_LEVEL_31 = 31, | |
| 80 | CODEC_AVC_LEVEL_32 = 32, | |
| 81 | CODEC_AVC_LEVEL_4 = 40, | |
| 82 | CODEC_AVC_LEVEL_41 = 41, | |
| 83 | CODEC_AVC_LEVEL_42 = 42, | |
| 84 | CODEC_AVC_LEVEL_5 = 50, | |
| 85 | CODEC_AVC_LEVEL_51 = 51, | |
| 86 | CODEC_AVC_LEVEL_52 = 52 | |
| 87 | } CODEC_AVC_LEVEL_IDC; | |
| 88 | ||
| 89 | // H.264 Inverse Quantization Matrix Buffer | |
| 90 | typedef struct _CODEC_AVC_IQ_MATRIX_PARAMS | |
| 91 | { | |
| 92 | uint8_t ScalingList4x4[6][16]; | |
| 93 | uint8_t ScalingList8x8[2][64]; | |
| 94 | } CODEC_AVC_IQ_MATRIX_PARAMS, *PCODEC_AVC_IQ_MATRIX_PARAMS; | |
| 95 | ||
| 96 | typedef struct _CODEC_AVC_FRAME_STORE_ID | |
| 97 | { | |
| 98 | bool inUse; | |
| 99 | bool reUse; | |
| 100 | } CODEC_AVC_FRAME_STORE_ID, *PCODEC_AVC_FRAME_STORE_ID; | |
| 101 | ||
| 102 | const uint8_t CODEC_AVC_Qmatrix_scan_4x4[16] = | |
| 103 | { | |
| 104 | 0, 1, 4, 8, 5, 2, 3, 6, 9, 12, 13, 10, 7, 11, 14, 15 | |
| 105 | }; | |
| 106 | ||
| 107 | const uint8_t CODEC_AVC_Qmatrix_scan_8x8[64] = | |
| 108 | { | |
| 109 | 0, 1, 8, 16, 9, 2, 3, 10, 17, 24, 32, 25, 18, 11, 4, 5, | |
| 110 | 12, 19, 26, 33, 40, 48, 41, 34, 27, 20, 13, 6, 7, 14, 21, 28, | |
| 111 | 35, 42, 49, 56, 57, 50, 43, 36, 29, 22, 15, 23, 30, 37, 44, 51, | |
| 112 | 58, 59, 52, 45, 38, 31, 39, 46, 53, 60, 61, 54, 47, 55, 62, 63 | |
| 113 | }; | |
| 114 | ||
| 115 | const uint8_t CODEC_AVC_Default_4x4_Intra[16] = | |
| 116 | { | |
| 117 | 6, 13, 13, 20, 20, 20, 28, 28, 28, 28, 32, 32, 32, 37, 37, 42 | |
| 118 | }; | |
| 119 | ||
| 120 | const uint8_t CODEC_AVC_Default_4x4_Inter[16] = | |
| 121 | { | |
| 122 | 10, 14, 14, 20, 20, 20, 24, 24, 24, 24, 27, 27, 27, 30, 30, 34 | |
| 123 | }; | |
| 124 | ||
| 125 | const uint8_t CODEC_AVC_Default_8x8_Intra[64] = | |
| 126 | { | |
| 127 | 6, 10, 10, 13, 11, 13, 16, 16, 16, 16, 18, 18, 18, 18, 18, 23, | |
| 128 | 23, 23, 23, 23, 23, 25, 25, 25, 25, 25, 25, 25, 27, 27, 27, 27, | |
| 129 | 27, 27, 27, 27, 29, 29, 29, 29, 29, 29, 29, 31, 31, 31, 31, 31, | |
| 130 | 31, 33, 33, 33, 33, 33, 36, 36, 36, 36, 38, 38, 38, 40, 40, 42 | |
| 131 | }; | |
| 132 | ||
| 133 | const uint8_t CODEC_AVC_Default_8x8_Inter[64] = | |
| 134 | { | |
| 135 | 9, 13, 13, 15, 13, 15, 17, 17, 17, 17, 19, 19, 19, 19, 19, 21, | |
| 136 | 21, 21, 21, 21, 21, 22, 22, 22, 22, 22, 22, 22, 24, 24, 24, 24, | |
| 137 | 24, 24, 24, 24, 25, 25, 25, 25, 25, 25, 25, 27, 27, 27, 27, 27, | |
| 138 | 27, 28, 28, 28, 28, 28, 30, 30, 30, 30, 32, 32, 32, 33, 33, 35 | |
| 139 | }; | |
| 140 | #endif // __CODEC_DEF_COMMON_AVC_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017-2019, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_encode.h | |
| 23 | //! \brief Defines common types and macros shared by CodecHal, MHW, and DDI layer for encode. | |
| 24 | //! \details All codec_def_encode may include this file which should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_ENCODE_H__ | |
| 27 | #define __CODEC_DEF_COMMON_ENCODE_H__ | |
| 28 | ||
| 29 | #include "mos_defs.h" | |
| 30 | ||
| 31 | #define CODEC_NUM_REF_BUFFERS (CODEC_MAX_NUM_REF_FRAME + 1) // Max 16 references (for AVC) + 1 for the current frame | |
| 32 | #define CODEC_NUM_NON_REF_BUFFERS 3 | |
| 33 | #define CODEC_NUM_TRACKED_BUFFERS (CODEC_NUM_REF_BUFFERS + CODEC_NUM_NON_REF_BUFFERS) | |
| 34 | #define CODEC_CURR_TRACKED_BUFFER CODEC_NUM_TRACKED_BUFFERS | |
| 35 | ||
| 36 | //BRC | |
| 37 | #define BRC_IMG_STATE_SIZE_PER_PASS 128 | |
| 38 | #define BRC_IMG_STATE_SIZE_PER_PASS_G10 144 | |
| 39 | #define BRC_IMG_STATE_SIZE_PER_PASS_G11 192 | |
| 40 | ||
| 41 | // Quality/Performance differentiators for HSW AVC Encode | |
| 42 | #define NUM_TARGET_USAGE_MODES 8 | |
| 43 | #define NUM_VDENC_TARGET_USAGE_MODES 8 | |
| 44 | ||
| 45 | //weighted prediction | |
| 46 | #define CODEC_NUM_WP_FRAME 8 | |
| 47 | #define CODEC_MAX_FORWARD_WP_FRAME 6 | |
| 48 | #define CODEC_MAX_BACKWARD_WP_FRAME 2 | |
| 49 | #define CODEC_WP_OUTPUT_L0_START 0 | |
| 50 | #define CODEC_WP_OUTPUT_L1_START 6 | |
| 51 | ||
| 52 | #define CODEC_720P_MAX_PIC_WIDTH 1280 | |
| 53 | #define CODEC_720P_MAX_PIC_HEIGHT 1280 | |
| 54 | ||
| 55 | #define CODEC_MAX_PIC_WIDTH 1920 | |
| 56 | #define CODEC_MAX_PIC_HEIGHT 1920 // Tablet usage in portrait mode, image resolution = 1200x1920, so change MAX_HEIGHT to 1920 | |
| 57 | ||
| 58 | #define CODEC_2K_MAX_PIC_WIDTH 2048 | |
| 59 | #define CODEC_2K_MAX_PIC_HEIGHT 2048 | |
| 60 | ||
| 61 | #define CODEC_4K_MAX_PIC_WIDTH 4096 | |
| 62 | #define CODEC_4K_MAX_PIC_HEIGHT 4096 | |
| 63 | ||
| 64 | #define CODEC_8K_MAX_PIC_WIDTH 8192 | |
| 65 | #define CODEC_8K_MAX_PIC_HEIGHT 8192 | |
| 66 | ||
| 67 | #define CODEC_16K_MAX_PIC_WIDTH 16384 | |
| 68 | #define CODEC_12K_MAX_PIC_HEIGHT 12288 | |
| 69 | #define CODEC_16K_MAX_PIC_HEIGHT 16384 | |
| 70 | ||
| 71 | #define CODECHAL_MAD_BUFFER_SIZE 4 // buffer size is 4 bytes | |
| 72 | ||
| 73 | #define CODEC_128_MIN_PIC_WIDTH 128 | |
| 74 | #define CODEC_96_MIN_PIC_HEIGHT 96 | |
| 75 | ||
| 76 | // HME | |
| 77 | #define SCALE_FACTOR_2x 2 | |
| 78 | #define SCALE_FACTOR_4x 4 | |
| 79 | #define SCALE_FACTOR_16x 16 | |
| 80 | #define SCALE_FACTOR_32x 32 | |
| 81 | ||
| 82 | #define CODECHAL_VP9_MB_CODE_SIZE 204 | |
| 83 | ||
| 84 | typedef struct tagENCODE_RECT | |
| 85 | { | |
| 86 | uint16_t Top; // [0..(FrameHeight+ M-1)/M -1] | |
| 87 | uint16_t Bottom; // [0..(FrameHeight+ M-1)/M -1] | |
| 88 | uint16_t Left; // [0..(FrameWidth+15)/16-1] | |
| 89 | uint16_t Right; // [0..(FrameWidth+15)/16-1] | |
| 90 | } ENCODE_RECT; | |
| 91 | ||
| 92 | typedef struct tagMOVE_RECT | |
| 93 | { | |
| 94 | uint32_t SourcePointX; | |
| 95 | uint32_t SourcePointY; | |
| 96 | uint32_t DestRectTop; | |
| 97 | uint32_t DestRectBottom; | |
| 98 | uint32_t DestRectLeft; | |
| 99 | uint32_t DestRectRight; | |
| 100 | } MOVE_RECT; | |
| 101 | ||
| 102 | /*! \brief Defines ROI settings. | |
| 103 | * | |
| 104 | * {Top, Bottom, Left, Right} defines the ROI boundary. The values are in unit of blocks. The block size M should use LCU size (e.g. sif LCU size is 32x32, M is 32). And its range should be within the frame boundary, so that: | |
| 105 | * 0 <= Top <= Bottom <= (FrameHeight+ M-1)/M -1 | |
| 106 | * 0 <= Left <= Right <= (FrameWidth+M-1)/M-1 | |
| 107 | * If input range is out of frame boundary, driver should trim it. | |
| 108 | * ROI alignes with LCU based rectangular blocks and cannot have arbitrary pixel-based location. | |
| 109 | * Region overlapping is allowed. For MBs reside within more than one ROIs, parameters from ROI with smaller index rules. For example, when ROI[0] and ROI[1] overlap on a certain area, the QP value for the overlapped area will be determined by value of ROI[0]. The order of ROI[] reflects objects’ relative relationship of depth. Foreground objects should have ROI index smaller than background objects. | |
| 110 | */ | |
| 111 | typedef struct _CODEC_ROI | |
| 112 | { | |
| 113 | uint16_t Top; //!< [0..(FrameHeight+15)/16-1] | |
| 114 | uint16_t Bottom; //!< [0..(FrameHeight+15)/16-1] | |
| 115 | uint16_t Left; //!< [0..(FrameWidth+15)/16-1] | |
| 116 | uint16_t Right; //!< [0..(FrameWidth+15)/16-1] | |
| 117 | /*! \brief For ROIValueInDeltaQP equals CQP case, this parameter gives explicit delta QP value of ROI regional QP vs. frame QP. | |
| 118 | * | |
| 119 | * Value range [-51..51]. If regional QP PriorityLevelOfDQp + QpY is out of range of [0..51], driver should crop it. It could be applied on both CQP and BRC cases. For ROIValueInDeltaQP equals 0BRC cases, this parameter describes the priority level of the ROI region. Value range [-3..3]. The higher the absolute value, the bigger range of delta QP is allowed. And it is usually applies on BRC case. BRC will decide the actual delta QP value. Positive priority level means negative delta QP should be applied. And negative priority level means positive delta QP which implies the region should be intentionally blurred. In either case, value Priority level 0 means same as non-ROI region. It is suggested that application does not set value 0. But if it happens, driver will treat that ROI as part of non-ROI background. | |
| 120 | */ | |
| 121 | char PriorityLevelOrDQp; | |
| 122 | } CODEC_ROI, *PCODEC_ROI; | |
| 123 | ||
| 124 | /*! \brief Indicates the uncompressed input color space | |
| 125 | * | |
| 126 | * Valid only when input is ARGB format. | |
| 127 | */ | |
| 128 | typedef enum _CODEC_INPUT_COLORSPACE | |
| 129 | { | |
| 130 | ECOLORSPACE_P709 = 0, | |
| 131 | ECOLORSPACE_P601 = 1, | |
| 132 | ECOLORSPACE_P2020 = 2 | |
| 133 | } CODEC_INPUT_COLORSPACE, ENCODE_INPUT_COLORSPACE; | |
| 134 | ||
| 135 | /*! \brief Indicates the tolerance the application has to variations in the frame size. | |
| 136 | * | |
| 137 | * For example, wireless display scenarios may require very steady bitrate to reduce buffering time. It affects the BRC algorithm used, but may or may not have an effect based on the combination of other BRC parameters. Only valid when the driver reports support for FrameSizeToleranceSupport. | |
| 138 | */ | |
| 139 | typedef enum _CODEC_FRAMESIZE_TOLERANCE | |
| 140 | { | |
| 141 | EFRAMESIZETOL_NORMAL = 0, | |
| 142 | EFRAMESIZETOL_LOW = 1, //!< Maps to "sliding window" | |
| 143 | EFRAMESIZETOL_EXTREMELY_LOW = 2 //!< Maps to "low delay" | |
| 144 | } CODEC_FRAMESIZE_TOLERANCE, ENCODE_FRAMESIZE_TOLERANCE; | |
| 145 | ||
| 146 | /*! \brief Provides a hint to encoder about the scenario for the encoding session. | |
| 147 | * | |
| 148 | * BRC algorithm may tune differently based on this info. | |
| 149 | */ | |
| 150 | typedef enum _CODEC_SCENARIO | |
| 151 | { | |
| 152 | ESCENARIO_UNKNOWN = 0, | |
| 153 | ESCENARIO_DISPLAYREMOTING = 1, | |
| 154 | ESCENARIO_VIDEOCONFERENCE = 2, | |
| 155 | ESCENARIO_ARCHIVE = 3, | |
| 156 | ESCENARIO_LIVESTREAMING = 4, | |
| 157 | ESCENARIO_VIDEOCAPTURE = 5, | |
| 158 | ESCENARIO_VIDEOSURVEILLANCE = 6, | |
| 159 | ESCENARIO_GAMESTREAMING = 7, | |
| 160 | ESCENARIO_REMOTEGAMING = 8 | |
| 161 | } CODEC_SCENARIO, ENCODE_SCENARIO; | |
| 162 | ||
| 163 | /*! \brief Provides a hint to encoder about the content for the encoding session. | |
| 164 | */ | |
| 165 | typedef enum _CODEC_CONTENT | |
| 166 | { | |
| 167 | ECONTENT_UNKNOWN = 0, | |
| 168 | ECONTENT_FULLSCREENVIDEO = 1, | |
| 169 | ECONTENT_NONVIDEOSCREEN = 2 | |
| 170 | } CODEC_CONTENT, ENCODE_CONTENT; | |
| 171 | ||
| 172 | typedef enum | |
| 173 | { | |
| 174 | RATECONTROL_CBR = 1, | |
| 175 | RATECONTROL_VBR = 2, | |
| 176 | RATECONTROL_CQP = 3, | |
| 177 | RATECONTROL_AVBR = 4, | |
| 178 | RATECONTROL_RESERVED0 = 8, // This is used by MSDK for Lookahead and hence not used here | |
| 179 | RATECONTROL_ICQ = 9, | |
| 180 | RATECONTROL_VCM = 10, | |
| 181 | RATECONTROL_QVBR = 14, | |
| 182 | RATECONTROL_CQL = 15, | |
| 183 | RATECONTROL_IWD_VBR = 100 | |
| 184 | } RATE_CONTROL_METHOD; | |
| 185 | ||
| 186 | //! | |
| 187 | //! \brief Help function to check if the rate control method is BRC | |
| 188 | //! | |
| 189 | //! \param [in] rc | |
| 190 | //! Rate control method | |
| 191 | //! | |
| 192 | //! \return True if using BRC , else return false | |
| 193 | //! | |
| 194 | inline bool IsRateControlBrc(uint8_t rc) | |
| 195 | { | |
| 196 | return (rc == RATECONTROL_CBR) || | |
| 197 | (rc == RATECONTROL_VBR) || | |
| 198 | (rc == RATECONTROL_AVBR) || | |
| 199 | (rc == RATECONTROL_VCM) || | |
| 200 | (rc == RATECONTROL_ICQ) || | |
| 201 | (rc == RATECONTROL_QVBR); | |
| 202 | } | |
| 203 | ||
| 204 | typedef enum | |
| 205 | { | |
| 206 | DEFAULT_WEIGHTED_INTER_PRED_MODE = 0, | |
| 207 | EXPLICIT_WEIGHTED_INTER_PRED_MODE = 1, | |
| 208 | IMPLICIT_WEIGHTED_INTER_PRED_MODE = 2, | |
| 209 | INVALID_WEIGHTED_INTER_PRED_MODE = -1 | |
| 210 | } WEIGHTED_INTER_PRED_MODE; | |
| 211 | ||
| 212 | // used from MHW & DDI | |
| 213 | typedef enum | |
| 214 | { | |
| 215 | ROLLING_I_DISABLED = 0, | |
| 216 | ROLLING_I_COLUMN = 1, | |
| 217 | ROLLING_I_ROW = 2, | |
| 218 | ROLLING_I_SQUARE = 3 | |
| 219 | } ROLLING_I_SETTING; | |
| 220 | ||
| 221 | typedef enum | |
| 222 | { | |
| 223 | BRC_ROLLING_I_DISABLED = 0, | |
| 224 | BRC_ROLLING_I_COLUMN = 4, | |
| 225 | BRC_ROLLING_I_ROW = 8, | |
| 226 | BRC_ROLLING_I_SQUARE = 12, | |
| 227 | BRC_ROLLING_I_QP = 13 | |
| 228 | }BRC_ROLLING_I_SETTING; | |
| 229 | ||
| 230 | typedef enum _CODECHAL_MFX_SURFACE_ID | |
| 231 | { | |
| 232 | CODECHAL_MFX_REF_SURFACE_ID = 0, | |
| 233 | CODECHAL_MFX_SRC_SURFACE_ID = 4, | |
| 234 | CODECHAL_MFX_DSRECON_SURFACE_ID = 5 | |
| 235 | } CODECHAL_MFX_SURFACE_ID; | |
| 236 | ||
| 237 | typedef enum _CODECHAL_HCP_SURFACE_ID | |
| 238 | { | |
| 239 | CODECHAL_HCP_DECODED_SURFACE_ID = 0, | |
| 240 | CODECHAL_HCP_SRC_SURFACE_ID = 1, // Encode | |
| 241 | CODECHAL_HCP_LAST_SURFACE_ID = 2, // VP9 | |
| 242 | CODECHAL_HCP_GOLDEN_SURFACE_ID = 3, // VP9 | |
| 243 | CODECHAL_HCP_ALTREF_SURFACE_ID = 4, // VP9 | |
| 244 | CODECHAL_HCP_REF_SURFACE_ID = 5 | |
| 245 | } CODECHAL_HCP_SURFACE_ID; | |
| 246 | ||
| 247 | // --------------------------- | |
| 248 | // Structures | |
| 249 | // --------------------------- | |
| 250 | // used from MHW & DDI | |
| 251 | typedef struct _BSBuffer | |
| 252 | { | |
| 253 | uint8_t *pBase; | |
| 254 | uint8_t *pCurrent; | |
| 255 | uint32_t SliceOffset; // Slice offset, always byte aligned | |
| 256 | uint8_t BitOffset; // bit offset for pCurrent. | |
| 257 | uint32_t BitSize; // bit size per slice, first slice may include SPS & PPS | |
| 258 | uint32_t BufferSize; // buffer size | |
| 259 | } BSBuffer, *PBSBuffer; | |
| 260 | ||
| 261 | typedef struct _CODEC_ENCODER_SLCDATA | |
| 262 | { | |
| 263 | uint32_t SliceOffset; | |
| 264 | uint32_t BitSize; | |
| 265 | uint32_t CmdOffset; | |
| 266 | uint32_t SkipEmulationByteCount; | |
| 267 | ||
| 268 | // MPEG2 only | |
| 269 | struct | |
| 270 | { | |
| 271 | uint8_t SliceGroup; | |
| 272 | uint16_t NextSgMbXCnt; | |
| 273 | uint16_t NextSgMbYCnt; | |
| 274 | }; | |
| 275 | } CODEC_ENCODER_SLCDATA, *PCODEC_ENCODER_SLCDATA; | |
| 276 | ||
| 277 | typedef struct _CODECHAL_NAL_UNIT_PARAMS | |
| 278 | { | |
| 279 | uint32_t uiNalUnitType; | |
| 280 | uint32_t uiOffset; | |
| 281 | uint32_t uiSize; | |
| 282 | bool bInsertEmulationBytes; | |
| 283 | uint32_t uiSkipEmulationCheckCount; | |
| 284 | } CODECHAL_NAL_UNIT_PARAMS, *PCODECHAL_NAL_UNIT_PARAMS; | |
| 285 | ||
| 286 | typedef struct tagFRAMERATE | |
| 287 | { | |
| 288 | uint32_t Numerator; | |
| 289 | uint32_t Denominator; | |
| 290 | } FRAMERATE; | |
| 291 | ||
| 292 | /*********************************************************************************\ | |
| 293 | Constants for VDENC costing look-up-tables | |
| 294 | \*********************************************************************************/ | |
| 295 | typedef enum _CODEC_VDENC_LUTMODE | |
| 296 | { | |
| 297 | CODEC_VDENC_LUTMODE_INTRA_SADMPM = 0x00, | |
| 298 | CODEC_VDENC_LUTMODE_INTRA_32x32 = 0x01, | |
| 299 | CODEC_VDENC_LUTMODE_INTRA_16x16 = 0x02, | |
| 300 | CODEC_VDENC_LUTMODE_INTRA_8x8 = 0x03, | |
| 301 | CODEC_VDENC_LUTMODE_INTER_32x16 = 0x04, | |
| 302 | CODEC_VDENC_LUTMODE_INTER_16x32 = 0x04, | |
| 303 | CODEC_VDENC_LUTMODE_INTER_AMP = 0x04, //All asymmetrical shapes | |
| 304 | CODEC_VDENC_LUTMODE_INTER_16x16 = 0x05, | |
| 305 | CODEC_VDENC_LUTMODE_INTER_16x8 = 0x06, | |
| 306 | CODEC_VDENC_LUTMODE_INTER_8x16 = 0x06, | |
| 307 | CODEC_VDENC_LUTMODE_INTER_8x8 = 0x07, | |
| 308 | CODEC_VDENC_LUTMODE_INTER_32x32 = 0x08, | |
| 309 | CODEC_VDENC_LUTMODE_INTER_BIDIR = 0x09, | |
| 310 | CODEC_VDENC_LUTMODE_REF_ID = 0x0A, | |
| 311 | CODEC_VDENC_LUTMODE_INTRA_CHROMA = 0x0B, | |
| 312 | CODEC_VDENC_LUTMODE_INTRA_NxN = 0x0C, | |
| 313 | CODEC_VDENC_LUTMODE_INTRA_RDEMPM = 0x0D, | |
| 314 | CODEC_VDENC_LUTMODE_MERGE_32X32 = 0x0E, | |
| 315 | CODEC_VDENC_LUTMODE_MERGE_16x16 = 0x0F, | |
| 316 | CODEC_VDENC_LUTMODE_MERGE_8x8 = 0x10, | |
| 317 | CODEC_VDENC_LUTMODE_SKIP_32X32 = 0x11, | |
| 318 | CODEC_VDENC_LUTMODE_SKIP_16x16 = 0x12, | |
| 319 | CODEC_VDENC_LUTMODE_SKIP_8x8 = 0x13, | |
| 320 | CODEC_VDENC_LUTMODE_INTRA_DC_32x32_SAD = 0x14, | |
| 321 | CODEC_VDENC_LUTMODE_INTRA_DC_16x16_SAD = 0x15, | |
| 322 | CODEC_VDENC_LUTMODE_INTRA_DC_8x8_SAD = 0x16, | |
| 323 | CODEC_VDENC_LUTMODE_INTRA_DC_4x4_SAD = 0x17, | |
| 324 | CODEC_VDENC_LUTMODE_INTRA_NONDC_32x32_SAD = 0x18, | |
| 325 | CODEC_VDENC_LUTMODE_INTRA_NONDC_16x16_SAD = 0x19, | |
| 326 | CODEC_VDENC_LUTMODE_INTRA_NONDC_8x8_SAD = 0x1A, | |
| 327 | CODEC_VDENC_LUTMODE_INTRA_NONDC_4x4_SAD = 0x1B, | |
| 328 | CODEC_VDENC_LUTMODE_INTRA_DC_32x32_RD = 0x1C, | |
| 329 | CODEC_VDENC_LUTMODE_INTRA_DC_8x8_RD = 0x1D, | |
| 330 | CODEC_VDENC_LUTMODE_INTRA_NONDC_32x32_RD = 0x1E, | |
| 331 | CODEC_VDENC_LUTMODE_INTRA_NONDC_8x8_RD = 0x1F, | |
| 332 | CODEC_VDENC_LUTMODE_INTRA_LEFT_BOUNDARY_SAD = 0x20, | |
| 333 | CODEC_VDENC_LUTMODE_INTRA_TOP_BOUNDARY_SAD = 0x21, | |
| 334 | CODEC_VDENC_LUTMODE_INTRA_TU_SPLIT = 0x22, | |
| 335 | CODEC_VDENC_LUTMODE_INTER_TU_SPLIT = 0x23, | |
| 336 | CODEC_VDENC_LUTMODE_TU_CBF_FLAG = 0x24, | |
| 337 | CODEC_VDENC_LUTMODE_INTRA_TU_32_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 0, | |
| 338 | CODEC_VDENC_LUTMODE_INTRA_TU_16_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 1, | |
| 339 | CODEC_VDENC_LUTMODE_INTRA_TU_8_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 2, | |
| 340 | CODEC_VDENC_LUTMODE_INTRA_TU_4_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 3, | |
| 341 | CODEC_VDENC_LUTMODE_INTER_TU_32_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 4, | |
| 342 | CODEC_VDENC_LUTMODE_INTER_TU_16_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 5, | |
| 343 | CODEC_VDENC_LUTMODE_INTER_TU_8_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 6, | |
| 344 | CODEC_VDENC_LUTMODE_INTER_TU_4_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 7, | |
| 345 | ||
| 346 | CODEC_VDENC_LUTMODE_TU_COEF_EST = 0x2C, | |
| 347 | CODEC_VDENC_LUTMODE_INTRA_TU_32_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 0, | |
| 348 | CODEC_VDENC_LUTMODE_INTRA_TU_16_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 1, | |
| 349 | CODEC_VDENC_LUTMODE_INTRA_TU_8_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 2, | |
| 350 | CODEC_VDENC_LUTMODE_INTRA_TU_4_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 3, | |
| 351 | CODEC_VDENC_LUTMODE_INTER_TU_32_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 4, | |
| 352 | CODEC_VDENC_LUTMODE_INTER_TU_16_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 5, | |
| 353 | CODEC_VDENC_LUTMODE_INTER_TU_8_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 6, | |
| 354 | CODEC_VDENC_LUTMODE_INTER_TU_4_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 7, | |
| 355 | ||
| 356 | CODEC_VDENC_LUTMODE_INTRA_TU_32_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 8, | |
| 357 | CODEC_VDENC_LUTMODE_INTRA_TU_16_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 9, | |
| 358 | CODEC_VDENC_LUTMODE_INTRA_TU_8_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 10, | |
| 359 | CODEC_VDENC_LUTMODE_INTRA_TU_4_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 11, | |
| 360 | CODEC_VDENC_LUTMODE_INTER_TU_32_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 12, | |
| 361 | CODEC_VDENC_LUTMODE_INTER_TU_16_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 13, | |
| 362 | CODEC_VDENC_LUTMODE_INTER_TU_8_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 14, | |
| 363 | CODEC_VDENC_LUTMODE_INTER_TU_4_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 15, | |
| 364 | ||
| 365 | CODEC_VDENC_LUTMODE_INTRA_TU_32_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 16, | |
| 366 | CODEC_VDENC_LUTMODE_INTRA_TU_16_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 17, | |
| 367 | CODEC_VDENC_LUTMODE_INTRA_TU_8_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 18, | |
| 368 | CODEC_VDENC_LUTMODE_INTRA_TU_4_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 19, | |
| 369 | CODEC_VDENC_LUTMODE_INTER_TU_32_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 20, | |
| 370 | CODEC_VDENC_LUTMODE_INTER_TU_16_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 21, | |
| 371 | CODEC_VDENC_LUTMODE_INTER_TU_8_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 22, | |
| 372 | CODEC_VDENC_LUTMODE_INTER_TU_4_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 23, | |
| 373 | ||
| 374 | CODEC_VDENC_LUTMODE_INTRA_TU_32_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 24, | |
| 375 | CODEC_VDENC_LUTMODE_INTRA_TU_16_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 25, | |
| 376 | CODEC_VDENC_LUTMODE_INTRA_TU_8_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 26, | |
| 377 | CODEC_VDENC_LUTMODE_INTRA_TU_4_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 27, | |
| 378 | CODEC_VDENC_LUTMODE_INTER_TU_32_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 28, | |
| 379 | CODEC_VDENC_LUTMODE_INTER_TU_16_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 29, | |
| 380 | CODEC_VDENC_LUTMODE_INTER_TU_8_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 30, | |
| 381 | CODEC_VDENC_LUTMODE_INTER_TU_4_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 31, | |
| 382 | ||
| 383 | // VP9 specific cost | |
| 384 | CODEC_VDENC_LUTMODE_INTRA_32x16 = 0x4C, | |
| 385 | CODEC_VDENC_LUTMODE_INTRA_16x8 = 0x4D, | |
| 386 | CODEC_VDENC_LUTMODE_INTER_NEARESTMV = 0x4E, | |
| 387 | CODEC_VDENC_LUTMODE_INTER_NEARMV = 0x4F, | |
| 388 | CODEC_VDENC_LUTMODE_INTER_ZEROMV = 0x50, | |
| 389 | CODEC_VDENC_LUTMODE_TU_DEPTH0 = 0x51, | |
| 390 | CODEC_VDENC_LUTMODE_TU_DEPTH1 = 0x52, | |
| 391 | CODEC_VDENC_LUTMODE_TU_DEPTH2 = 0x53, | |
| 392 | ||
| 393 | CODEC_VDENC_LUTMODE_INTRA_64X64DC = 0x54, | |
| 394 | CODEC_VDENC_LUTMODE_MERGE_64X64 = 0x55, | |
| 395 | CODEC_VDENC_LUTMODE_SKIP_64X64 = 0x56, | |
| 396 | ||
| 397 | CODEC_VDENC_NUM_MODE_COST = 0x57 | |
| 398 | } CODEC_VDENC_LUTMODE; | |
| 399 | ||
| 400 | // Batch buffer type | |
| 401 | enum | |
| 402 | { | |
| 403 | MB_ENC_Frame_BB = 0, | |
| 404 | MB_ENC_Field_BB, | |
| 405 | //Add new buffer type here | |
| 406 | NUM_ENCODE_BB_TYPE | |
| 407 | }; | |
| 408 | ||
| 409 | typedef enum | |
| 410 | { | |
| 411 | FRAME_NO_SKIP = 0, // encode as normal, no skip frames | |
| 412 | FRAME_SKIP_NORMAL = 1 // one or more frames were skipped prior to curr frame. Encode curr frame as normal, update BRC | |
| 413 | } FRAME_SKIP_FLAG; | |
| 414 | ||
| 415 | typedef enum _CODEC_SLICE_STRUCTS | |
| 416 | { | |
| 417 | CODECHAL_SLICE_STRUCT_ONESLICE = 0, // Once slice for the whole frame | |
| 418 | CODECHAL_SLICE_STRUCT_POW2ROWS = 1, // Slices are power of 2 number of rows, all slices the same | |
| 419 | CODECHAL_SLICE_STRUCT_ROWSLICE = 2, // Slices are any number of rows, all slices the same | |
| 420 | CODECHAL_SLICE_STRUCT_ARBITRARYROWSLICE = 3, // Slices are any number of rows, slices can be different | |
| 421 | CODECHAL_SLICE_STRUCT_ARBITRARYMBSLICE = 4 // Slices are any number of MBs, slices can be different | |
| 422 | // 5 - 7 are Reserved | |
| 423 | } CODEC_SLICE_STRUCTS; | |
| 424 | ||
| 425 | //FEI Encode Macros | |
| 426 | #define CodecHalIsFeiEncode(codecFunction) \ | |
| 427 | ( codecFunction == CODECHAL_FUNCTION_FEI_PRE_ENC || \ | |
| 428 | codecFunction == CODECHAL_FUNCTION_FEI_ENC || \ | |
| 429 | codecFunction == CODECHAL_FUNCTION_FEI_PAK || \ | |
| 430 | codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK) | |
| 431 | ||
| 432 | //Encode Macros | |
| 433 | #define CodecHalIsEncode(codecFunction) \ | |
| 434 | (codecFunction == CODECHAL_FUNCTION_ENC || \ | |
| 435 | codecFunction == CODECHAL_FUNCTION_PAK || \ | |
| 436 | codecFunction == CODECHAL_FUNCTION_ENC_PAK || \ | |
| 437 | codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK ||\ | |
| 438 | codecFunction == CODECHAL_FUNCTION_HYBRIDPAK) || \ | |
| 439 | CodecHalIsFeiEncode(codecFunction) | |
| 440 | ||
| 441 | #define CodecHalUsesVideoEngine(codecFunction) \ | |
| 442 | (codecFunction == CODECHAL_FUNCTION_PAK || \ | |
| 443 | codecFunction == CODECHAL_FUNCTION_ENC_PAK || \ | |
| 444 | codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK || \ | |
| 445 | codecFunction == CODECHAL_FUNCTION_FEI_PAK || \ | |
| 446 | codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK) | |
| 447 | ||
| 448 | #define CodecHalUsesRenderEngine(codecFunction, standard) \ | |
| 449 | (codecFunction == CODECHAL_FUNCTION_ENC || \ | |
| 450 | (codecFunction == CODECHAL_FUNCTION_ENC_PAK) || \ | |
| 451 | codecFunction == CODECHAL_FUNCTION_HYBRIDPAK || \ | |
| 452 | ((codecFunction == CODECHAL_FUNCTION_DECODE) && (standard == CODECHAL_VC1)) || \ | |
| 453 | codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK || \ | |
| 454 | codecFunction == CODECHAL_FUNCTION_FEI_PRE_ENC || \ | |
| 455 | codecFunction == CODECHAL_FUNCTION_FEI_ENC || \ | |
| 456 | codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK) | |
| 457 | ||
| 458 | #define CodecHalUsesOnlyRenderEngine(codecFunction) \ | |
| 459 | (codecFunction == CODECHAL_FUNCTION_ENC || \ | |
| 460 | codecFunction == CODECHAL_FUNCTION_FEI_ENC || \ | |
| 461 | codecFunction == CODECHAL_FUNCTION_HYBRIDPAK) | |
| 462 | ||
| 463 | #define CodecHalUsesVdencEngine(codecFunction) \ | |
| 464 | (codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK) | |
| 465 | ||
| 466 | #define CodecHalUsesPakEngine(codecFunction) \ | |
| 467 | (codecFunction == CODECHAL_FUNCTION_PAK || \ | |
| 468 | codecFunction == CODECHAL_FUNCTION_ENC_PAK) | |
| 469 | ||
| 470 | #define CodecHalIsRateControlBrc(rateControl, standard) (\ | |
| 471 | (rateControl == RATECONTROL_CBR) || \ | |
| 472 | (rateControl == RATECONTROL_VBR) || \ | |
| 473 | (rateControl == RATECONTROL_AVBR) || \ | |
| 474 | (rateControl == RATECONTROL_CQL) || \ | |
| 475 | ((( rateControl == RATECONTROL_VCM) || \ | |
| 476 | ( rateControl == RATECONTROL_ICQ) || \ | |
| 477 | ( rateControl == RATECONTROL_QVBR) || \ | |
| 478 | ( rateControl == RATECONTROL_IWD_VBR)) && \ | |
| 479 | ( standard == CODECHAL_AVC )) ) | |
| 480 | ||
| 481 | // The current definition of the first encode mode CODECHAL_ENCODE_MODE_AVC should be used | |
| 482 | // as a base for subsequent encode modes | |
| 483 | #define CODECHAL_ENCODE_MODE_BIT_OFFSET ((uint32_t)(log((double)CODECHAL_ENCODE_MODE_AVC)/log(2.))) | |
| 484 | #define CODECHAL_ENCODE_MODE_BIT_MASK (( 1L << CODECHAL_ENCODE_MODE_BIT_OFFSET) - 1 ) | |
| 485 | ||
| 486 | #endif // __CODEC_DEF_COMMON_ENCODE_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_hevc.h | |
| 23 | //! \brief Defines basic HEVC types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details This is the base header for all codec_def HEVC files. All codec_def HEVC files should include this file which should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_HEVC_H__ | |
| 27 | #define __CODEC_DEF_COMMON_HEVC_H__ | |
| 28 | ||
| 29 | #include "codec_def_common.h" | |
| 30 | ||
| 31 | #define CODEC_MAX_NUM_REF_FRAME_HEVC 15 | |
| 32 | #define CODECHAL_MAX_CUR_NUM_REF_FRAME_HEVC 8 | |
| 33 | #define CODEC_HEVC_VDENC_LCU_WIDTH 64 | |
| 34 | #define CODEC_HEVC_VDENC_LCU_HEIGHT 64 | |
| 35 | ||
| 36 | /*! \brief Quantization matrix data, which is sent on a per-picture basis. | |
| 37 | * | |
| 38 | * The quantization matrix buffer is sent only when scaling_list_enabled_flag takes value 1. If 0, driver should assume "flat" scaling lists are present and all the entries takes value 16. | |
| 39 | */ | |
| 40 | typedef struct _CODECHAL_HEVC_IQ_MATRIX_PARAMS | |
| 41 | { | |
| 42 | /*! \brief Scaling lists for the 4x4 scaling process. | |
| 43 | * | |
| 44 | * Corresponding to ScalingList[ 0 ][ MatrixID ][ i ] in HEVC specification, where MatrixID is in the range of 0 to 5, inclusive, and i is in the range of 0 to 15, inclusive. | |
| 45 | */ | |
| 46 | uint8_t ucScalingLists0[6][16]; | |
| 47 | ||
| 48 | /*! \brief Scaling lists for the 8x8 scaling process. | |
| 49 | * | |
| 50 | * Corresponding to ScalingList[ 1 ][ MatrixID ][ i ] in the HEVC specification, where MatrixID is in the range of 0 to 5, inclusive, and i is in the range of 0 to 63, inclusive. | |
| 51 | */ | |
| 52 | uint8_t ucScalingLists1[6][64]; | |
| 53 | ||
| 54 | /*! \brief Scaling lists for the 8x8 scaling process. | |
| 55 | * | |
| 56 | * Corresponding to ScalingList[ 2 ][ MatrixID ][ i ] in HEVC specification, where MatrixID is in the range of 0 to 5, inclusive, and i is in the range of 0 to 63, inclusive. | |
| 57 | */ | |
| 58 | uint8_t ucScalingLists2[6][64]; | |
| 59 | ||
| 60 | /*! \brief Scaling lists for the 8x8 scaling process. | |
| 61 | * | |
| 62 | * Corresponding to ScalingList[ 3 ][ MatrixID ][ i ] in HEVC specification, where MatrixID is in the range of 0 to 1, inclusive, and i is in the range of 0 to 63, inclusive. | |
| 63 | */ | |
| 64 | uint8_t ucScalingLists3[2][64]; | |
| 65 | ||
| 66 | /*! \brief DC value of the scaling list for 16x16 size. | |
| 67 | * | |
| 68 | * With sizeID equal to 2 and corresponding to scaling_list_dc_coef_minus8[ sizeID − 2 ][ matrixID ] +8 with sizeID equal to 2 and matrixID in the range of 0 to 5, inclusive, in HEVC specification. | |
| 69 | */ | |
| 70 | uint8_t ucScalingListDCCoefSizeID2[6]; | |
| 71 | ||
| 72 | /*! \brief DC value of the scaling list for 32x32 size. | |
| 73 | * | |
| 74 | * With sizeID equal to 3, and corresponding to scaling_list_dc_coef_minus8[ sizeID − 2 ][ matrixID ] +8 with sizeID equal to 3 and matrixID in the range of 0 to 1, inclusive, in HEVC specification. | |
| 75 | */ | |
| 76 | uint8_t ucScalingListDCCoefSizeID3[2]; | |
| 77 | } CODECHAL_HEVC_IQ_MATRIX_PARAMS, *PCODECHAL_HEVC_IQ_MATRIX_PARAMS; | |
| 78 | ||
| 79 | typedef struct _CODEC_HEVC_SCC_PIC_PARAMS | |
| 80 | { | |
| 81 | union | |
| 82 | { | |
| 83 | struct | |
| 84 | { | |
| 85 | uint32_t pps_curr_pic_ref_enabled_flag : 1; | |
| 86 | uint32_t palette_mode_enabled_flag : 1; | |
| 87 | uint32_t motion_vector_resolution_control_idc : 2; //[0..2] | |
| 88 | uint32_t intra_boundary_filtering_disabled_flag : 1; | |
| 89 | uint32_t residual_adaptive_colour_transform_enabled_flag : 1; | |
| 90 | uint32_t pps_slice_act_qp_offsets_present_flag : 1; | |
| 91 | uint32_t ReservedBits6 : 25; | |
| 92 | } fields; | |
| 93 | uint32_t dwScreenContentCodingPropertyFlags; | |
| 94 | } PicSCCExtensionFlags; | |
| 95 | ||
| 96 | uint8_t palette_max_size; // [0..64] | |
| 97 | uint8_t delta_palette_max_predictor_size; // [0..128] | |
| 98 | uint8_t PredictorPaletteSize; // [0..127] | |
| 99 | uint16_t PredictorPaletteEntries[3][128]; | |
| 100 | char pps_act_y_qp_offset_plus5; // [-7..17] | |
| 101 | char pps_act_cb_qp_offset_plus5; // [-7..17] | |
| 102 | char pps_act_cr_qp_offset_plus3; // [-9..15] | |
| 103 | ||
| 104 | } CODEC_HEVC_SCC_PIC_PARAMS, *PCODEC_HEVC_SCC_PIC_PARAMS; | |
| 105 | ||
| 106 | #endif // __CODEC_DEF_COMMON_HEVC_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_jpeg.h | |
| 23 | //! \brief Defines basic JPEG types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details This is the base header for all codec_def JPEG files. All codec_def JPEG files should include this file which should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_JPEG_H__ | |
| 27 | #define __CODEC_DEF_COMMON_JPEG_H__ | |
| 28 | ||
| 29 | #include "codec_def_common.h" | |
| 30 | ||
| 31 | #define JPEG_MAX_NUM_HUFF_TABLE_INDEX 2 // For baseline only allowed 2, else could have 4. | |
| 32 | #define JPEG_NUM_QUANTMATRIX 64 // Elements of 8x8 matrix in zig-zag scan order. | |
| 33 | #define JPEG_MAX_NUM_OF_QUANTMATRIX 4 // JPEG decoders can store up to 4 different quantization matrix | |
| 34 | ||
| 35 | #define JPEG_NUM_HUFF_TABLE_DC_BITS 12 // Huffman Table DC BITS | |
| 36 | #define JPEG_NUM_HUFF_TABLE_DC_HUFFVAL 12 // Huffman Table DC HUFFVAL | |
| 37 | #define JPEG_NUM_HUFF_TABLE_AC_BITS 16 // Huffman Table AC BITS | |
| 38 | #define JPEG_NUM_HUFF_TABLE_AC_HUFFVAL 162 // Huffman Table AC HUFFVAL | |
| 39 | ||
| 40 | //! | |
| 41 | //! \enum CodecJpegComponents | |
| 42 | //! \brief JPEG Component Types | |
| 43 | //! | |
| 44 | enum CodecJpegComponents | |
| 45 | { | |
| 46 | jpegComponentY = 0, //!< Component Y | |
| 47 | jpegComponentU = 1, //!< Component U | |
| 48 | jpegComponentV = 2, //!< Component V | |
| 49 | jpegNumComponent = 3, //!< Component number | |
| 50 | }; | |
| 51 | ||
| 52 | //! | |
| 53 | //! \struct CodecJpegQuantMatrix | |
| 54 | //! \brief JPEG Quantization Matrix | |
| 55 | //! | |
| 56 | struct CodecJpegQuantMatrix | |
| 57 | { | |
| 58 | uint32_t m_jpegQMTableType[JPEG_MAX_NUM_OF_QUANTMATRIX]; //!< Quant Matrix table type | |
| 59 | uint8_t m_quantMatrix[JPEG_MAX_NUM_OF_QUANTMATRIX][JPEG_NUM_QUANTMATRIX]; //!< Quant Matrix | |
| 60 | }; | |
| 61 | ||
| 62 | #endif // __CODEC_DEF_COMMON_JPEG_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_mpeg2.h | |
| 23 | //! \brief Defines basic MPEG2 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details This is the base header for all codec_def MPEG2 files. All codec_def MPEG2 files should include this file which should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_MPEG2_H__ | |
| 27 | #define __CODEC_DEF_COMMON_MPEG2_H__ | |
| 28 | ||
| 29 | #include "codec_def_common.h" | |
| 30 | ||
| 31 | //! | |
| 32 | //! \struct CodecMpeg2IqMatrix | |
| 33 | //! \brief Inverse Quantization Matrix Buffer | |
| 34 | //! | |
| 35 | struct CodecMpeg2IqMatrix | |
| 36 | { | |
| 37 | int32_t m_loadIntraQuantiserMatrix; //!< Indicate if intra Quantiser Matrix is available | |
| 38 | int32_t m_loadNonIntraQuantiserMatrix; //!< Indicate if non intra Quantiser Matrix is available | |
| 39 | int32_t m_loadChromaIntraQuantiserMatrix; //!< Indicate if chroma intra Quantiser Matrix is available | |
| 40 | int32_t m_loadChromaNonIntraQuantiserMatrix;//!< Indicate if chroma non intra Quantiser Matrix is available | |
| 41 | uint8_t m_intraQuantiserMatrix[64]; //!< Intra Quantiser Matrix | |
| 42 | uint8_t m_nonIntraQuantiserMatrix[64]; //!< Non intra Quantiser Matrix | |
| 43 | uint8_t m_chromaIntraQuantiserMatrix[64]; //!< Chroma intra Quantiser Matrix | |
| 44 | uint8_t m_chromaNonIntraQuantiserMatrix[64];//!< Chroma non intra Quantiser Matrix | |
| 45 | }; | |
| 46 | ||
| 47 | #endif // __CODEC_DEF_COMMON_MPEG2_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017-2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_common_vp9.h | |
| 23 | //! \brief Defines decode VP9 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to VP9 codec only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_COMMON_VP9_H__ | |
| 27 | #define __CODEC_DEF_COMMON_VP9_H__ | |
| 28 | ||
| 29 | #include "mos_os.h" | |
| 30 | ||
| 31 | #define CODEC_VP9_SUPER_BLOCK_WIDTH 64 | |
| 32 | #define CODEC_VP9_SUPER_BLOCK_HEIGHT 64 | |
| 33 | #define CODEC_VP9_MIN_BLOCK_WIDTH 8 | |
| 34 | #define CODEC_VP9_MIN_BLOCK_HEIGHT 8 | |
| 35 | ||
| 36 | #define CODEC_VP9_BLOCK_TYPES 2 //Outside dimension. 0 = Y with DC, 1 = UV | |
| 37 | #define CODEC_VP9_REF_TYPES 2 // intra=0, inter=1 | |
| 38 | #define CODEC_VP9_COEF_BANDS 6 //Middle dimension reflects the coefficient position within the transform. | |
| 39 | #define CODEC_VP9_UNCONSTRAINED_NODES 3 | |
| 40 | /* Inside dimension is measure of nearby complexity, that reflects the energy | |
| 41 | of nearby coefficients are nonzero. For the first coefficient (DC, unless | |
| 42 | block type is 0), we look at the (already encoded) blocks above and to the | |
| 43 | left of the current block. The context index is then the number (0,1,or 2) | |
| 44 | of these blocks having nonzero coefficients. | |
| 45 | After decoding a coefficient, the measure is determined by the size of the | |
| 46 | most recently decoded coefficient. | |
| 47 | Note that the intuitive meaning of this measure changes as coefficients | |
| 48 | are decoded, e.g., prior to the first token, a zero means that my neighbors | |
| 49 | are empty while, after the first token, because of the use of end-of-block, | |
| 50 | a zero means we just decoded a zero and hence guarantees that a non-zero | |
| 51 | coefficient will appear later in this block. However, this shift | |
| 52 | in meaning is perfectly OK because our context depends also on the | |
| 53 | coefficient band (and since zigzag positions 0, 1, and 2 are in | |
| 54 | distinct bands). */ | |
| 55 | #define CODEC_VP9_PREV_COEF_CONTEXTS 6 | |
| 56 | #define CODEC_VP9_MBSKIP_CONTEXTS 3 | |
| 57 | #define CODEC_VP9_INTER_MODE_CONTEXTS 7 | |
| 58 | #define CODEC_VP9_INTER_MODES 4 //NEAREST_MV, NEAR_MV, ZERO_MV, NEW_MV | |
| 59 | #define CODEC_VP9_SWITCHABLE_FILTERS 3 // number of switchable filters | |
| 60 | #define CODEC_VP9_INTRA_INTER_CONTEXTS 4 | |
| 61 | #define CODEC_VP9_COMP_INTER_CONTEXTS 5 | |
| 62 | #define CODEC_VP9_REF_CONTEXTS 5 | |
| 63 | #define CODEC_VP9_BLOCK_SIZE_GROUPS 4 | |
| 64 | #define CODEC_VP9_INTRA_MODES 10 //DC_PRED,V_PRED,H_PRED,D45_PRED,D135_PRED,D117_PRED,D153_PRED,D207_PRED,D63_PRED,TM_PRED | |
| 65 | #define CODEC_VP9_PARTITION_PLOFFSET 4 // number of probability models per block size | |
| 66 | #define CODECHAL_VP9_PARTITION_CONTEXTS (4 * CODEC_VP9_PARTITION_PLOFFSET) | |
| 67 | #define CODEC_VP9_MV_JOINTS 4 | |
| 68 | #define CODEC_VP9_MV_CLASSES 11 | |
| 69 | #define CODEC_VP9_CLASS0_BITS 1 /* bits at integer precision for class 0 */ | |
| 70 | #define CODECHAL_VP9_CLASS0_SIZE (1 << CODEC_VP9_CLASS0_BITS) | |
| 71 | #define CODECHAL_VP9_MV_OFFSET_BITS (CODEC_VP9_MV_CLASSES + CODEC_VP9_CLASS0_BITS - 2) | |
| 72 | #define CODEC_VP9_MV_FP_SIZE 4 | |
| 73 | #define CODEC_VP9_NUM_REF_FRAMES_LOG2 3 | |
| 74 | #define CODEC_VP9_NUM_REF_FRAMES (1 << CODEC_VP9_NUM_REF_FRAMES_LOG2) | |
| 75 | #define CODECHAL_VP9_NUM_DPB_BUFFERS (CODEC_VP9_NUM_REF_FRAMES + 4) | |
| 76 | #define CODEC_VP9_NUM_CONTEXTS 4 | |
| 77 | #define CODEC_VP9_MAX_REF_LF_DELTAS 4 | |
| 78 | #define CODEC_VP9_MAX_MODE_LF_DELTAS 2 | |
| 79 | #define CODECHAL_VP9_SEG_TREE_PROBS (CODEC_VP9_MAX_SEGMENTS - 1) | |
| 80 | #define CODEC_VP9_PREDICTION_PROBS 3 | |
| 81 | #define CODEC_VP9_MAX_LOOP_FILTER 63 | |
| 82 | ||
| 83 | #define CODEC_VP9_MAX_QP 255 | |
| 84 | #define CODEC_VP9_QINDEX_RANGE (CODEC_VP9_MAX_QP + 1) | |
| 85 | #define CODEC_VP9_MAX_REPAK_THRESHOLD 40342 | |
| 86 | ||
| 87 | //VP9 Profile | |
| 88 | typedef enum { | |
| 89 | CODEC_PROFILE_VP9_PROFILE0 = 0, | |
| 90 | CODEC_PROFILE_VP9_PROFILE1 = 1, | |
| 91 | CODEC_PROFILE_VP9_PROFILE2 = 2, | |
| 92 | CODEC_PROFILE_VP9_PROFILE3 = 3 | |
| 93 | }CODEC_VP9_PROFILE_IDC; | |
| 94 | ||
| 95 | typedef enum { | |
| 96 | CODEC_VP9_KEY_FRAME = 0, | |
| 97 | CODEC_VP9_INTER_FRAME = 1, | |
| 98 | CODEC_VP9_FRAME_TYPES, | |
| 99 | } CODEC_VP9_FRAME_TYPE; | |
| 100 | ||
| 101 | // block transform size | |
| 102 | typedef enum { | |
| 103 | CODEC_VP9_TX_4X4 = 0, // 4x4 transform | |
| 104 | CODEC_VP9_TX_8X8 = 1, // 8x8 transform | |
| 105 | CODEC_VP9_TX_16X16 = 2, // 16x16 transform | |
| 106 | CODEC_VP9_TX_32X32 = 3, // 32x32 transform | |
| 107 | CODEC_VP9_TX_SELECTABLE = 4, // selectable transform | |
| 108 | CODEC_VP9_TX_SIZES = 4, | |
| 109 | } CODEC_VP9_TX_SIZE; | |
| 110 | ||
| 111 | typedef enum CODEC_VP9_PARTITION_TYPE { | |
| 112 | CODEC_VP9_PARTITION_NONE, | |
| 113 | CODEC_VP9_PARTITION_HORZ, | |
| 114 | CODEC_VP9_PARTITION_VERT, | |
| 115 | CODEC_VP9_PARTITION_SPLIT, | |
| 116 | CODEC_VP9_PARTITION_TYPES, | |
| 117 | CODECHAL_VP9_PARTITION_INVALID = CODEC_VP9_PARTITION_TYPES | |
| 118 | } CODEC_VP9_PARTITION_TYPE; | |
| 119 | ||
| 120 | typedef uint8_t CODEC_VP9_COEFF_PROBS_MODEL[CODEC_VP9_REF_TYPES][CODEC_VP9_COEF_BANDS] | |
| 121 | [CODEC_VP9_PREV_COEF_CONTEXTS] | |
| 122 | [CODEC_VP9_UNCONSTRAINED_NODES]; | |
| 123 | ||
| 124 | static const uint16_t CODECHAL_VP9_QUANT_DC[CODEC_VP9_QINDEX_RANGE] = { | |
| 125 | 4, 8, 8, 9, 10, 11, 12, 12, | |
| 126 | 13, 14, 15, 16, 17, 18, 19, 19, | |
| 127 | 20, 21, 22, 23, 24, 25, 26, 26, | |
| 128 | 27, 28, 29, 30, 31, 32, 32, 33, | |
| 129 | 34, 35, 36, 37, 38, 38, 39, 40, | |
| 130 | 41, 42, 43, 43, 44, 45, 46, 47, | |
| 131 | 48, 48, 49, 50, 51, 52, 53, 53, | |
| 132 | 54, 55, 56, 57, 57, 58, 59, 60, | |
| 133 | 61, 62, 62, 63, 64, 65, 66, 66, | |
| 134 | 67, 68, 69, 70, 70, 71, 72, 73, | |
| 135 | 74, 74, 75, 76, 77, 78, 78, 79, | |
| 136 | 80, 81, 81, 82, 83, 84, 85, 85, | |
| 137 | 87, 88, 90, 92, 93, 95, 96, 98, | |
| 138 | 99, 101, 102, 104, 105, 107, 108, 110, | |
| 139 | 111, 113, 114, 116, 117, 118, 120, 121, | |
| 140 | 123, 125, 127, 129, 131, 134, 136, 138, | |
| 141 | 140, 142, 144, 146, 148, 150, 152, 154, | |
| 142 | 156, 158, 161, 164, 166, 169, 172, 174, | |
| 143 | 177, 180, 182, 185, 187, 190, 192, 195, | |
| 144 | 199, 202, 205, 208, 211, 214, 217, 220, | |
| 145 | 223, 226, 230, 233, 237, 240, 243, 247, | |
| 146 | 250, 253, 257, 261, 265, 269, 272, 276, | |
| 147 | 280, 284, 288, 292, 296, 300, 304, 309, | |
| 148 | 313, 317, 322, 326, 330, 335, 340, 344, | |
| 149 | 349, 354, 359, 364, 369, 374, 379, 384, | |
| 150 | 389, 395, 400, 406, 411, 417, 423, 429, | |
| 151 | 435, 441, 447, 454, 461, 467, 475, 482, | |
| 152 | 489, 497, 505, 513, 522, 530, 539, 549, | |
| 153 | 559, 569, 579, 590, 602, 614, 626, 640, | |
| 154 | 654, 668, 684, 700, 717, 736, 755, 775, | |
| 155 | 796, 819, 843, 869, 896, 925, 955, 988, | |
| 156 | 1022, 1058, 1098, 1139, 1184, 1232, 1282, 1336, | |
| 157 | }; | |
| 158 | ||
| 159 | static const uint16_t CODECHAL_VP9_QUANT_AC[CODEC_VP9_QINDEX_RANGE] = { | |
| 160 | 4, 8, 9, 10, 11, 12, 13, 14, | |
| 161 | 15, 16, 17, 18, 19, 20, 21, 22, | |
| 162 | 23, 24, 25, 26, 27, 28, 29, 30, | |
| 163 | 31, 32, 33, 34, 35, 36, 37, 38, | |
| 164 | 39, 40, 41, 42, 43, 44, 45, 46, | |
| 165 | 47, 48, 49, 50, 51, 52, 53, 54, | |
| 166 | 55, 56, 57, 58, 59, 60, 61, 62, | |
| 167 | 63, 64, 65, 66, 67, 68, 69, 70, | |
| 168 | 71, 72, 73, 74, 75, 76, 77, 78, | |
| 169 | 79, 80, 81, 82, 83, 84, 85, 86, | |
| 170 | 87, 88, 89, 90, 91, 92, 93, 94, | |
| 171 | 95, 96, 97, 98, 99, 100, 101, 102, | |
| 172 | 104, 106, 108, 110, 112, 114, 116, 118, | |
| 173 | 120, 122, 124, 126, 128, 130, 132, 134, | |
| 174 | 136, 138, 140, 142, 144, 146, 148, 150, | |
| 175 | 152, 155, 158, 161, 164, 167, 170, 173, | |
| 176 | 176, 179, 182, 185, 188, 191, 194, 197, | |
| 177 | 200, 203, 207, 211, 215, 219, 223, 227, | |
| 178 | 231, 235, 239, 243, 247, 251, 255, 260, | |
| 179 | 265, 270, 275, 280, 285, 290, 295, 300, | |
| 180 | 305, 311, 317, 323, 329, 335, 341, 347, | |
| 181 | 353, 359, 366, 373, 380, 387, 394, 401, | |
| 182 | 408, 416, 424, 432, 440, 448, 456, 465, | |
| 183 | 474, 483, 492, 501, 510, 520, 530, 540, | |
| 184 | 550, 560, 571, 582, 593, 604, 615, 627, | |
| 185 | 639, 651, 663, 676, 689, 702, 715, 729, | |
| 186 | 743, 757, 771, 786, 801, 816, 832, 848, | |
| 187 | 864, 881, 898, 915, 933, 951, 969, 988, | |
| 188 | 1007, 1026, 1046, 1066, 1087, 1108, 1129, 1151, | |
| 189 | 1173, 1196, 1219, 1243, 1267, 1292, 1317, 1343, | |
| 190 | 1369, 1396, 1423, 1451, 1479, 1508, 1537, 1567, | |
| 191 | 1597, 1628, 1660, 1692, 1725, 1759, 1793, 1828, | |
| 192 | }; | |
| 193 | ||
| 194 | static const uint16_t CODECHAL_VP9_QUANT_DC_10[CODEC_VP9_QINDEX_RANGE] = { | |
| 195 | 4, 9, 10, 13, 15, 17, 20, 22, | |
| 196 | 25, 28, 31, 34, 37, 40, 43, 47, | |
| 197 | 50, 53, 57, 60, 64, 68, 71, 75, | |
| 198 | 78, 82, 86, 90, 93, 97, 101, 105, | |
| 199 | 109, 113, 116, 120, 124, 128, 132, 136, | |
| 200 | 140, 143, 147, 151, 155, 159, 163, 166, | |
| 201 | 170, 174, 178, 182, 185, 189, 193, 197, | |
| 202 | 200, 204, 208, 212, 215, 219, 223, 226, | |
| 203 | 230, 233, 237, 241, 244, 248, 251, 255, | |
| 204 | 259, 262, 266, 269, 273, 276, 280, 283, | |
| 205 | 287, 290, 293, 297, 300, 304, 307, 310, | |
| 206 | 314, 317, 321, 324, 327, 331, 334, 337, | |
| 207 | 343, 350, 356, 362, 369, 375, 381, 387, | |
| 208 | 394, 400, 406, 412, 418, 424, 430, 436, | |
| 209 | 442, 448, 454, 460, 466, 472, 478, 484, | |
| 210 | 490, 499, 507, 516, 525, 533, 542, 550, | |
| 211 | 559, 567, 576, 584, 592, 601, 609, 617, | |
| 212 | 625, 634, 644, 655, 666, 676, 687, 698, | |
| 213 | 708, 718, 729, 739, 749, 759, 770, 782, | |
| 214 | 795, 807, 819, 831, 844, 856, 868, 880, | |
| 215 | 891, 906, 920, 933, 947, 961, 975, 988, | |
| 216 | 1001, 1015, 1030, 1045, 1061, 1076, 1090, 1105, | |
| 217 | 1120, 1137, 1153, 1170, 1186, 1202, 1218, 1236, | |
| 218 | 1253, 1271, 1288, 1306, 1323, 1342, 1361, 1379, | |
| 219 | 1398, 1416, 1436, 1456, 1476, 1496, 1516, 1537, | |
| 220 | 1559, 1580, 1601, 1624, 1647, 1670, 1692, 1717, | |
| 221 | 1741, 1766, 1791, 1817, 1844, 1871, 1900, 1929, | |
| 222 | 1958, 1990, 2021, 2054, 2088, 2123, 2159, 2197, | |
| 223 | 2236, 2276, 2319, 2363, 2410, 2458, 2508, 2561, | |
| 224 | 2616, 2675, 2737, 2802, 2871, 2944, 3020, 3102, | |
| 225 | 3188, 3280, 3375, 3478, 3586, 3702, 3823, 3953, | |
| 226 | 4089, 4236, 4394, 4559, 4737, 4929, 5130, 5347, | |
| 227 | }; | |
| 228 | ||
| 229 | static const uint16_t CODECHAL_VP9_QUANT_AC_10[CODEC_VP9_QINDEX_RANGE] = { | |
| 230 | 4, 9, 11, 13, 16, 18, 21, 24, | |
| 231 | 27, 30, 33, 37, 40, 44, 48, 51, | |
| 232 | 55, 59, 63, 67, 71, 75, 79, 83, | |
| 233 | 88, 92, 96, 100, 105, 109, 114, 118, | |
| 234 | 122, 127, 131, 136, 140, 145, 149, 154, | |
| 235 | 158, 163, 168, 172, 177, 181, 186, 190, | |
| 236 | 195, 199, 204, 208, 213, 217, 222, 226, | |
| 237 | 231, 235, 240, 244, 249, 253, 258, 262, | |
| 238 | 267, 271, 275, 280, 284, 289, 293, 297, | |
| 239 | 302, 306, 311, 315, 319, 324, 328, 332, | |
| 240 | 337, 341, 345, 349, 354, 358, 362, 367, | |
| 241 | 371, 375, 379, 384, 388, 392, 396, 401, | |
| 242 | 409, 417, 425, 433, 441, 449, 458, 466, | |
| 243 | 474, 482, 490, 498, 506, 514, 523, 531, | |
| 244 | 539, 547, 555, 563, 571, 579, 588, 596, | |
| 245 | 604, 616, 628, 640, 652, 664, 676, 688, | |
| 246 | 700, 713, 725, 737, 749, 761, 773, 785, | |
| 247 | 797, 809, 825, 841, 857, 873, 889, 905, | |
| 248 | 922, 938, 954, 970, 986, 1002, 1018, 1038, | |
| 249 | 1058, 1078, 1098, 1118, 1138, 1158, 1178, 1198, | |
| 250 | 1218, 1242, 1266, 1290, 1314, 1338, 1362, 1386, | |
| 251 | 1411, 1435, 1463, 1491, 1519, 1547, 1575, 1603, | |
| 252 | 1631, 1663, 1695, 1727, 1759, 1791, 1823, 1859, | |
| 253 | 1895, 1931, 1967, 2003, 2039, 2079, 2119, 2159, | |
| 254 | 2199, 2239, 2283, 2327, 2371, 2415, 2459, 2507, | |
| 255 | 2555, 2603, 2651, 2703, 2755, 2807, 2859, 2915, | |
| 256 | 2971, 3027, 3083, 3143, 3203, 3263, 3327, 3391, | |
| 257 | 3455, 3523, 3591, 3659, 3731, 3803, 3876, 3952, | |
| 258 | 4028, 4104, 4184, 4264, 4348, 4432, 4516, 4604, | |
| 259 | 4692, 4784, 4876, 4972, 5068, 5168, 5268, 5372, | |
| 260 | 5476, 5584, 5692, 5804, 5916, 6032, 6148, 6268, | |
| 261 | 6388, 6512, 6640, 6768, 6900, 7036, 7172, 7312, | |
| 262 | }; | |
| 263 | ||
| 264 | typedef struct _CODEC_VP9_SEG_PARAMS | |
| 265 | { | |
| 266 | union | |
| 267 | { | |
| 268 | struct | |
| 269 | { | |
| 270 | uint16_t SegmentReferenceEnabled : 1; // [0..1] | |
| 271 | uint16_t SegmentReference : 2; // [0..3] | |
| 272 | uint16_t SegmentReferenceSkipped : 1; // [0..1] | |
| 273 | uint16_t ReservedField3 : 12; // [0] | |
| 274 | } fields; | |
| 275 | uint32_t value; | |
| 276 | } SegmentFlags; | |
| 277 | ||
| 278 | uint8_t FilterLevel[4][2]; // [0..63] | |
| 279 | uint16_t LumaACQuantScale; // | |
| 280 | uint16_t LumaDCQuantScale; // | |
| 281 | uint16_t ChromaACQuantScale; // | |
| 282 | uint16_t ChromaDCQuantScale; // | |
| 283 | } CODEC_VP9_SEG_PARAMS, *PCODEC_VP9_SEG_PARAMS; | |
| 284 | ||
| 285 | #endif | |
| 286 |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_decode_avc.h | |
| 23 | //! \brief Defines decode AVC types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to AVC decode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_DECODE_AVC_H__ | |
| 27 | #define __CODEC_DEF_DECODE_AVC_H__ | |
| 28 | ||
| 29 | #include "codec_def_common_avc.h" | |
| 30 | ||
| 31 | //Check whether interview prediction is used through POC | |
| 32 | #define CodecHal_IsInterviewPred(currPic, currPoc, avcRefListIdx) ( ((avcRefListIdx)!=(currPic).FrameIdx) && \ | |
| 33 | (!CodecHal_PictureIsTopField(currPic) && (ppAvcRefList[avcRefListIdx]->iFieldOrderCnt[1] == (currPoc)[1]) || \ | |
| 34 | !CodecHal_PictureIsBottomField(currPic) && (ppAvcRefList[avcRefListIdx]->iFieldOrderCnt[0] == (currPoc)[0])) && \ | |
| 35 | ((currPic).FrameIdx != 0x7f)) | |
| 36 | ||
| 37 | typedef struct _CODEC_AVC_DMV_LIST | |
| 38 | { | |
| 39 | uint8_t ucFrameId; | |
| 40 | bool bInUse; | |
| 41 | bool bReUse; | |
| 42 | } CODEC_AVC_DMV_LIST, *PCODEC_AVC_DMV_LIST; | |
| 43 | ||
| 44 | //! | |
| 45 | //! \enum AvcChromaFormatIdc | |
| 46 | //! \brief AVC chroma format Idc | |
| 47 | //! | |
| 48 | enum AvcChromaFormatIdc | |
| 49 | { | |
| 50 | avcChromaFormatMono = 0, | |
| 51 | avcChromaFormat420 = 1, | |
| 52 | avcChromaFormat422 = 2, | |
| 53 | avcChromaFormat444 = 3, | |
| 54 | }; | |
| 55 | ||
| 56 | // H.264 Picture Parameters Buffer | |
| 57 | typedef struct _CODEC_AVC_PIC_PARAMS | |
| 58 | { | |
| 59 | /*! \brief Uncompressed destination surface of the frame for the current decoded picture. | |
| 60 | * | |
| 61 | * The long_term_ref_flag has no meaning. The valid value range for Curr.FrameIdx is [0..126]. Value 127 or 0x7F can be treated as an invalid surface index. | |
| 62 | */ | |
| 63 | CODEC_PICTURE CurrPic; | |
| 64 | /*! \brief FrameIdx for each entry specifies the surface index for all pictures that are or will be referred to by the current or future pictures. | |
| 65 | * | |
| 66 | * The valid entries are indexed from 0 to 126, inclusive. The PicFlags of non-valid entries (including the picture of the entry which is not referred by current picture or future pictures) should take value PICTURE_INVALID. A PicFlags setting of PICTURE_LONG_TERM_REFERENCE indicates if the picture is a long term reference or not. | |
| 67 | * NOTE: for interlace (field) pictures, the FrameIdx field of two RefFrameList entries may have same value and point to same reference surface. And in this case, application should allocate buffer size with double picture height to hold the whole picture. | |
| 68 | */ | |
| 69 | CODEC_PICTURE RefFrameList[CODEC_AVC_MAX_NUM_REF_FRAME]; | |
| 70 | ||
| 71 | uint16_t pic_width_in_mbs_minus1; //!< Same as AVC syntax element. | |
| 72 | /*! \brief The height of the frame in MBs minus 1. | |
| 73 | * | |
| 74 | * Derived from pic_height_in_map_units_minus1: pic_height_in_map_units_minus1 << uint16_t(frame_mbs_only_flag == 0) | |
| 75 | */ | |
| 76 | uint16_t pic_height_in_mbs_minus1; | |
| 77 | uint8_t bit_depth_luma_minus8; //!< Same as AVC syntax element. | |
| 78 | uint8_t bit_depth_chroma_minus8; //!< Same as AVC syntax element. | |
| 79 | uint8_t num_ref_frames; //!< Same as AVC syntax element. | |
| 80 | /*! \brief Contains the picture order counts (POC) for the current frame | |
| 81 | * | |
| 82 | * If field_pic_flag is 0: | |
| 83 | * \n - CurrFieldOrderCnt[0] contains the top field order count for the current picture | |
| 84 | * \n - CurrFieldOrderCnt[1] contains the bottom field order count for the current picture | |
| 85 | * \n If field_pic_flag is 1 and CurrPic.PicFlags indicates that this is a top field: | |
| 86 | * \n - CurrFieldOrderCnt[0] contains the top field order count for the current picture | |
| 87 | * \n - CurrFieldOrderCnt[1] | |
| 88 | * \n If field_pic_flag is 1 and CurrPic.PicFlags indicates that this is a bottom field: | |
| 89 | * \n - CurrFieldOrderCnt[0] should be 0 or ignored | |
| 90 | * \n - CurrFieldOrderCnt[1] contains the bottom field order count for the current picture | |
| 91 | */ | |
| 92 | int32_t CurrFieldOrderCnt[2]; | |
| 93 | /*! \brief Contains the POCs for the reference frames in RefFrameList. | |
| 94 | * | |
| 95 | * For each entry FieldOrderCntList[i][j]: | |
| 96 | * \n - i: the picture index | |
| 97 | * \n - j: 0 specifies the top field order count and 1 specifies the bottom field order count | |
| 98 | * \n If a entry i in RefFrameList is not relevant (it is not used for reference) or valid, the entry FieldOrderCount[i][0 and 1] should be 0. | |
| 99 | */ | |
| 100 | int32_t FieldOrderCntList[16][2]; | |
| 101 | ||
| 102 | union | |
| 103 | { | |
| 104 | struct | |
| 105 | { | |
| 106 | uint32_t chroma_format_idc : 2; //!< Same as AVC syntax element. | |
| 107 | uint32_t residual_colour_transform_flag : 1; //!< Same as AVC syntax element. | |
| 108 | uint32_t frame_mbs_only_flag : 1; //!< Same as AVC syntax element. | |
| 109 | uint32_t mb_adaptive_frame_field_flag : 1; //!< Same as AVC syntax element. | |
| 110 | uint32_t direct_8x8_inference_flag : 1; //!< Same as AVC syntax element. | |
| 111 | uint32_t : 1; | |
| 112 | uint32_t log2_max_frame_num_minus4 : 4; //!< Same as AVC syntax element. | |
| 113 | uint32_t pic_order_cnt_type : 2; //!< Same as AVC syntax element. | |
| 114 | uint32_t log2_max_pic_order_cnt_lsb_minus4 : 4; //!< Same as AVC syntax element. | |
| 115 | uint32_t delta_pic_order_always_zero_flag : 1; //!< Same as AVC syntax element. | |
| 116 | }; | |
| 117 | uint32_t value; | |
| 118 | } seq_fields; | |
| 119 | ||
| 120 | uint8_t num_slice_groups_minus1; //!< Same as AVC syntax element. | |
| 121 | uint8_t slice_group_map_type; //!< Same as AVC syntax element. | |
| 122 | uint16_t slice_group_change_rate_minus1; //!< Same as AVC syntax element. | |
| 123 | char pic_init_qp_minus26; //!< Same as AVC syntax element. | |
| 124 | char chroma_qp_index_offset; //!< Same as AVC syntax element. | |
| 125 | char second_chroma_qp_index_offset; //!< Same as AVC syntax element. | |
| 126 | ||
| 127 | union | |
| 128 | { | |
| 129 | struct | |
| 130 | { | |
| 131 | uint32_t entropy_coding_mode_flag : 1; //!< Same as AVC syntax element. | |
| 132 | uint32_t weighted_pred_flag : 1; //!< Same as AVC syntax element. | |
| 133 | uint32_t weighted_bipred_idc : 2; //!< Same as AVC syntax element. | |
| 134 | uint32_t transform_8x8_mode_flag : 1; //!< Same as AVC syntax element. | |
| 135 | uint32_t field_pic_flag : 1; //!< Same as AVC syntax element. | |
| 136 | uint32_t constrained_intra_pred_flag : 1; //!< Same as AVC syntax element. | |
| 137 | uint32_t pic_order_present_flag : 1; //!< Same as AVC syntax element. | |
| 138 | uint32_t deblocking_filter_control_present_flag : 1; //!< Same as AVC syntax element. | |
| 139 | uint32_t redundant_pic_cnt_present_flag : 1; //!< Same as AVC syntax element. | |
| 140 | uint32_t reference_pic_flag : 1; //!< Same as AVC syntax element. | |
| 141 | uint32_t IntraPicFlag : 1; //!< All MBs in frame use intra prediction mode. | |
| 142 | }; | |
| 143 | uint32_t value; | |
| 144 | } pic_fields; | |
| 145 | ||
| 146 | // Short format specific | |
| 147 | uint8_t num_ref_idx_l0_active_minus1; //!< Same as AVC syntax element. | |
| 148 | uint8_t num_ref_idx_l1_active_minus1; //!< Same as AVC syntax element. | |
| 149 | /*! \brief Contains the value of FrameNum or LongTermRefIdx depending on the PicFlags for the frame. | |
| 150 | * | |
| 151 | * Each entry in FrameNumList has a corresponding entry in RefFrameList, if an entry in RefFrameList is not relevant (it is not used for reference) or valid, the entry in FrameNumList should be 0. | |
| 152 | */ | |
| 153 | uint16_t FrameNumList[16]; | |
| 154 | /*! \brief Denotes "non-existing" frames as defined in the AVC specification. | |
| 155 | * | |
| 156 | * The flag is accessed by: Flag(i) = (NonExistingFrameFlags >> i) & 1. If Flag(i) is 1, frame i is marked as "non-existing", otherwise the frame is existing. | |
| 157 | */ | |
| 158 | uint16_t NonExistingFrameFlags; | |
| 159 | /*! \brief Denotes "used for reference" frames as defined in the AVC specification. | |
| 160 | * | |
| 161 | * The flag is accessed by: | |
| 162 | * \n - FlagTop(i) = (UsedForReferenceFlags >> (2 * i)) & 1 | |
| 163 | * \n - FlagBottom(i) = (UsedForReferenceFlags >> (2 * i + 1)) & 1 | |
| 164 | * \n If FlagTop(i) is 1, the top field or frame numger i is marked as "used for reference"; if FlagBottom(i) is 1 then then bottom field of frame i is marked as "used for reference". If either is 0 then the frame is not marked as "used for reference". | |
| 165 | */ | |
| 166 | uint32_t UsedForReferenceFlags; | |
| 167 | uint16_t frame_num; //!< Same as AVC syntax element. | |
| 168 | ||
| 169 | /*! \brief Arbitrary number set by the host decoder to use as a tag in the status report feedback data. | |
| 170 | * | |
| 171 | * The value should not equal 0, and should be different in each call to Execute. | |
| 172 | */ | |
| 173 | uint32_t StatusReportFeedbackNumber; | |
| 174 | } CODEC_AVC_PIC_PARAMS, *PCODEC_AVC_PIC_PARAMS; | |
| 175 | ||
| 176 | // H.264 Decode Slice Parameter Buffer (Long/Short format) | |
| 177 | typedef struct _CODEC_AVC_SLICE_PARAMS | |
| 178 | { | |
| 179 | uint32_t slice_data_size; //!< Number of bytes in the bitstream buffer for this slice. | |
| 180 | uint32_t slice_data_offset; //!< The offset to the NAL start code for this slice. | |
| 181 | ||
| 182 | // Long format specific | |
| 183 | uint16_t slice_data_bit_offset; //!< Bit offset from NAL start code to the beginning of slice data. | |
| 184 | uint16_t first_mb_in_slice; //!< Same as AVC syntax element. | |
| 185 | uint16_t NumMbsForSlice; //!< Number of MBs in the bitstream associated with this slice. | |
| 186 | uint8_t slice_type; //!< Same as AVC syntax element. | |
| 187 | uint8_t direct_spatial_mv_pred_flag; //!< Same as AVC syntax element. | |
| 188 | uint8_t num_ref_idx_l0_active_minus1; //!< Same as AVC syntax element. | |
| 189 | uint8_t num_ref_idx_l1_active_minus1; //!< Same as AVC syntax element. | |
| 190 | uint8_t cabac_init_idc; //!< Same as AVC syntax element. | |
| 191 | char slice_qp_delta; //!< Same as AVC syntax element. | |
| 192 | uint8_t disable_deblocking_filter_idc; //!< Same as AVC syntax element. | |
| 193 | char slice_alpha_c0_offset_div2; //!< Same as AVC syntax element. | |
| 194 | char slice_beta_offset_div2; //!< Same as AVC syntax element. | |
| 195 | /*! \brief Specifies the reference picture lists 0 and 1 | |
| 196 | * | |
| 197 | * Contains field/frame information concerning the reference in PicFlags. RefPicList[i][j]: | |
| 198 | * \n - i: the reference picture list (0 or 1) | |
| 199 | * \n - j: if the PicFlags are not PICTURE_INVALID, the index variable j is a reference to entry j in teh reference picture list. | |
| 200 | */ | |
| 201 | CODEC_PICTURE RefPicList[2][32]; | |
| 202 | uint8_t luma_log2_weight_denom; //!< Same as AVC syntax element. | |
| 203 | uint8_t chroma_log2_weight_denom; //!< Same as AVC syntax element. | |
| 204 | /*! \brief Specifies the weights and offsets used for explicit mode weighted prediction. | |
| 205 | * | |
| 206 | * Weigths[i][j][k][m]: | |
| 207 | * \n - i: the reference picture list (0 or 1) | |
| 208 | * \n - j: reference to entry j in RefPicList (has range [0...31]) | |
| 209 | * \n - k: the YUV component (0 = luma, 1 = Cb chroma, 2 = Cr chroma) | |
| 210 | * \n - m: the weight or offset used in the weighted prediction process (0 = weight, 1 = offset) | |
| 211 | */ | |
| 212 | int16_t Weights[2][32][3][2]; | |
| 213 | uint16_t slice_id; //!< Same as AVC syntax element. | |
| 214 | uint16_t first_mb_in_next_slice; //!< If there is a subsequent slice, specifies first_mb_in_slice for the next slice, otherwise is 0. | |
| 215 | } CODEC_AVC_SLICE_PARAMS, *PCODEC_AVC_SLICE_PARAMS; | |
| 216 | ||
| 217 | // AVC MVC Extension Picture Parameter Set | |
| 218 | // (sent along with regular _CODEC_AVC_PIC_PARAMS) | |
| 219 | typedef struct _CODEC_MVC_EXT_PIC_PARAMS | |
| 220 | { | |
| 221 | uint16_t CurrViewID; | |
| 222 | uint8_t anchor_pic_flag; | |
| 223 | uint8_t inter_view_flag; | |
| 224 | uint8_t NumInterViewRefsL0; | |
| 225 | uint8_t NumInterViewRefsL1; | |
| 226 | union | |
| 227 | { | |
| 228 | uint8_t bPicFlags; | |
| 229 | struct | |
| 230 | { | |
| 231 | uint8_t SwitchToAVC : 1; | |
| 232 | uint8_t Reserved7Bits : 7; | |
| 233 | }; | |
| 234 | }; | |
| 235 | uint8_t Reserved8Bits; | |
| 236 | uint16_t ViewIDList[16]; | |
| 237 | uint16_t InterViewRefList[2][16]; | |
| 238 | } CODEC_MVC_EXT_PIC_PARAMS, *PCODEC_MVC_EXT_PIC_PARAMS; | |
| 239 | ||
| 240 | #endif // __CODEC_DEF_DECODE_AVC_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_decode_hevc.h | |
| 23 | //! \brief Defines decode HEVC types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to HEVC decode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_DECODE_HEVC_H__ | |
| 27 | #define __CODEC_DEF_DECODE_HEVC_H__ | |
| 28 | ||
| 29 | #include "codec_def_common_hevc.h" | |
| 30 | ||
| 31 | #define CODEC_NUM_REF_HEVC_MV_BUFFERS CODEC_MAX_NUM_REF_FRAME_HEVC | |
| 32 | #define CODEC_NUM_HEVC_MV_BUFFERS (CODEC_NUM_REF_HEVC_MV_BUFFERS + 1) | |
| 33 | #define CODEC_NUM_HEVC_INITIAL_MV_BUFFERS 6 | |
| 34 | #define HEVC_NUM_MAX_TILE_ROW 22 | |
| 35 | #define HEVC_NUM_MAX_TILE_COLUMN 20 | |
| 36 | #define CODECHAL_HEVC_MAX_NUM_SLICES_LVL_6 600 | |
| 37 | #define CODECHAL_HEVC_MAX_NUM_SLICES_LVL_5 200 | |
| 38 | #define CODECHAL_HEVC_NUM_DMEM_BUFFERS 32 | |
| 39 | ||
| 40 | #define CODEC_HEVC_NUM_SECOND_BB 32 | |
| 41 | ||
| 42 | #define CODECHAL_HEVC_MIN_LCU 16 | |
| 43 | #define CODECHAL_HEVC_MAX_DIM_FOR_MIN_LCU 4222 | |
| 44 | ||
| 45 | const uint8_t CODECHAL_DECODE_HEVC_Qmatrix_Scan_4x4[16] = { 0, 4, 1, 8, 5, 2, 12, 9, 6, 3, 13, 10, 7, 14, 11, 15 }; | |
| 46 | const uint8_t CODECHAL_DECODE_HEVC_Qmatrix_Scan_8x8[64] = | |
| 47 | { 0, 8, 1, 16, 9, 2, 24, 17, 10, 3, 32, 25, 18, 11, 4, 40, | |
| 48 | 33, 26, 19, 12, 5, 48, 41, 34, 27, 20, 13, 6, 56, 49, 42, 35, | |
| 49 | 28, 21, 14, 7, 57, 50, 43, 36, 29, 22, 15, 58, 51, 44, 37, 30, | |
| 50 | 23, 59, 52, 45, 38, 31, 60, 53, 46, 39, 61, 54, 47, 62, 55, 63 }; | |
| 51 | const uint8_t CODECHAL_DECODE_HEVC_Default_4x4[16] = { 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16 }; | |
| 52 | const uint8_t CODECHAL_DECODE_HEVC_Default_8x8_Intra[64] = | |
| 53 | { 16, 16, 16, 16, 17, 18, 21, 24, 16, 16, 16, 16, 17, 19, 22, 25, | |
| 54 | 16, 16, 17, 18, 20, 22, 25, 29, 16, 16, 18, 21, 24, 27, 31, 36, | |
| 55 | 17, 17, 20, 24, 30, 35, 41, 47, 18, 19, 22, 27, 35, 44, 54, 65, | |
| 56 | 21, 22, 25, 31, 41, 54, 70, 88, 24, 25, 29, 36, 47, 65, 88, 115 }; | |
| 57 | const uint8_t CODECHAL_DECODE_HEVC_Default_8x8_Inter[64] = | |
| 58 | { 16, 16, 16, 16, 17, 18, 20, 24, 16, 16, 16, 17, 18, 20, 24, 25, | |
| 59 | 16, 16, 17, 18, 20, 24, 25, 28, 16, 17, 18, 20, 24, 25, 28, 33, | |
| 60 | 17, 18, 20, 24, 25, 28, 33, 41, 18, 20, 24, 25, 28, 33, 41, 54, | |
| 61 | 20, 24, 25, 28, 33, 41, 54, 71, 24, 25, 28, 33, 41, 54, 71, 91 }; | |
| 62 | ||
| 63 | /*! \brief Picture-level parameters of a compressed picture for HEVC decoding. | |
| 64 | * | |
| 65 | * Note 1: Application only pass in the first num_tile_columns_minus1 tile column widths and first num_tile_rows_minus1 tile row heights. The last width and height need to be calculated by driver from the picture dimension. Values used for data type alignement. Their values should be set to 0, and can be ignored by decoder. | |
| 66 | * Note 2: HEVC host decoder should discard any NAL units with nal_unit_type in the range of [10 – 15, 22 – 63]. | |
| 67 | * Note 3: When tiles_enabled_flag equals 1 and uniform_spacing_flag takes value 1, driver may ignore the values passed in column_width_minus1[] and raw_height_minus1[]. Instead driver should generate and populate these tile dimension values based on picture resolution and num_tile_columns_minus1, num_tile_rows_minus1. It can be referred to formula (6-3) and (6-4) in HEVC spec. | |
| 68 | */ | |
| 69 | typedef struct _CODEC_HEVC_PIC_PARAMS | |
| 70 | { | |
| 71 | /*! \brief Width of decoded pictures in units of minimum luma coding block size. | |
| 72 | * | |
| 73 | * The decoded picture width in units of luma samples equals (PicWidthInMinCbsY) * (1 << (log2_min_coding_block_size_minus3 + 3)). | |
| 74 | */ | |
| 75 | uint16_t PicWidthInMinCbsY; | |
| 76 | /*! \brief Height of decoded pictures in units of minimum luma coding block size. | |
| 77 | * | |
| 78 | * The decoded picture height in units of luma samples equals (PicHeightInMinCbsY) * (1 << (log2_min_coding_block_size_minus3 + 3)). | |
| 79 | */ | |
| 80 | uint16_t PicHeightInMinCbsY; | |
| 81 | ||
| 82 | union | |
| 83 | { | |
| 84 | struct | |
| 85 | { | |
| 86 | uint16_t chroma_format_idc : 2; //!< Same as HEVC syntax element | |
| 87 | uint16_t separate_colour_plane_flag : 1; //!< Same as HEVC syntax element | |
| 88 | uint16_t bit_depth_luma_minus8 : 3; //!< Same as HEVC syntax element | |
| 89 | uint16_t bit_depth_chroma_minus8 : 3; //!< Same as HEVC syntax element | |
| 90 | uint16_t log2_max_pic_order_cnt_lsb_minus4 : 4; //!< Same as HEVC syntax element | |
| 91 | /*! \brief Indicates that no picture reordering is used in the coded video sequence. | |
| 92 | * | |
| 93 | * If equal to 1, the maximum allowed number of pictures preceding any picture in decoding order and succeeding that picture in output order is equal to 0. When NoPicReorderingFlag equal to 0, picture reordering may be used in the coded video sequence. This flag does not affect the decoding process. | |
| 94 | * Note: NoPicReorderingFlag may be set to 1 by the host software decoder when sps_max_num_reorder_pics is equal to 0. However, there is no requirement that NoPicReorderingFlag must be derived from sps_max_num_reorder_pics. | |
| 95 | */ | |
| 96 | uint16_t NoPicReorderingFlag : 1; | |
| 97 | /*! \brief Indicates that B slices are not used in the coded video sequence. | |
| 98 | * | |
| 99 | * This flag does not affect the decoding process. | |
| 100 | * Note: This flag does not correspond to any indication provided in the HEVC bitstream itself. Thus, a host software decoder would need some external information (e.g. as determined at the application level) to be able to set this flag to 1. In the absence of any such available indication, the host software decoder must set this flag to 0. | |
| 101 | */ | |
| 102 | uint16_t NoBiPredFlag : 1; | |
| 103 | uint16_t ReservedBits1 : 1; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 104 | }; | |
| 105 | ||
| 106 | uint16_t wFormatAndSequenceInfoFlags; | |
| 107 | }; | |
| 108 | ||
| 109 | /*! \brief Uncompressed destination surface of the frame for the current decoded picture. | |
| 110 | * | |
| 111 | * The long_term_ref_flag has no meaning. The valid value range for Curr.FrameIdx is [0..126]. Value 127 or 0x7F can be treated as an invalid surface index. | |
| 112 | */ | |
| 113 | CODEC_PICTURE CurrPic; | |
| 114 | ||
| 115 | /*! \brief Number of reference frames in the DPB buffer. | |
| 116 | * | |
| 117 | * Host decoder should set this value to be sps_max_dec_pic_buffering_minus1 of the temporal layer where the current decoding frame is of. The value should be between 0 and 15, inclusive. | |
| 118 | */ | |
| 119 | uint8_t sps_max_dec_pic_buffering_minus1; | |
| 120 | uint8_t log2_min_luma_coding_block_size_minus3; //!< Same as HEVC syntax element | |
| 121 | uint8_t log2_diff_max_min_luma_coding_block_size; //!< Same as HEVC syntax element | |
| 122 | uint8_t log2_min_transform_block_size_minus2; //!< Same as HEVC syntax element | |
| 123 | uint8_t log2_diff_max_min_transform_block_size; //!< Same as HEVC syntax element | |
| 124 | uint8_t max_transform_hierarchy_depth_inter; //!< Same as HEVC syntax element | |
| 125 | uint8_t max_transform_hierarchy_depth_intra; //!< Same as HEVC syntax element | |
| 126 | uint8_t num_short_term_ref_pic_sets; //!< Same as HEVC syntax element | |
| 127 | uint8_t num_long_term_ref_pic_sps; //!< Same as HEVC syntax element | |
| 128 | /*! \brief Same as HEVC syntax element. | |
| 129 | * | |
| 130 | * When long slice control data format is taken, hardware decoder should take values from num_ref_idx_l0_active_minus1 and num_ref_idx_l1_active_minus1 from slice control data structure. | |
| 131 | */ | |
| 132 | uint8_t num_ref_idx_l0_default_active_minus1; | |
| 133 | /*! \brief Same as HEVC syntax element. | |
| 134 | * | |
| 135 | * When long slice control data format is taken, hardware decoder should take values from num_ref_idx_l0_active_minus1 and num_ref_idx_l1_active_minus1 from slice control data structure. | |
| 136 | */ | |
| 137 | uint8_t num_ref_idx_l1_default_active_minus1; | |
| 138 | char init_qp_minus26; //!< Same as HEVC syntax element | |
| 139 | /*! \brief Decoder may ignore this value. | |
| 140 | * | |
| 141 | * This is an redundant parameter which serves as same purpose as wNumBitsForShortTermRPSInSlice. | |
| 142 | */ | |
| 143 | uint8_t ucNumDeltaPocsOfRefRpsIdx; | |
| 144 | /*! \brief Bit count in the bit stream for parsing short_term_ref_pic_set in slice segment header. | |
| 145 | * | |
| 146 | * If short_term_ref_pic_set_sps_flag takes value 1, wNumBitsForShortTermRPSInSlice should be 0. The bit count value is calculated when emulation prevention bytes are removed from raw elementary bit stream. | |
| 147 | */ | |
| 148 | uint16_t wNumBitsForShortTermRPSInSlice; | |
| 149 | uint16_t ReservedBits2; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 150 | ||
| 151 | union | |
| 152 | { | |
| 153 | struct | |
| 154 | { | |
| 155 | uint32_t scaling_list_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 156 | uint32_t amp_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 157 | uint32_t sample_adaptive_offset_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 158 | uint32_t pcm_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 159 | uint32_t pcm_sample_bit_depth_luma_minus1 : 4; //!< Same as HEVC syntax element | |
| 160 | uint32_t pcm_sample_bit_depth_chroma_minus1 : 4; //!< Same as HEVC syntax element | |
| 161 | uint32_t log2_min_pcm_luma_coding_block_size_minus3 : 2; //!< Same as HEVC syntax element | |
| 162 | uint32_t log2_diff_max_min_pcm_luma_coding_block_size : 2; //!< Same as HEVC syntax element | |
| 163 | uint32_t pcm_loop_filter_disabled_flag : 1; //!< Same as HEVC syntax element | |
| 164 | uint32_t long_term_ref_pics_present_flag : 1; //!< Same as HEVC syntax element | |
| 165 | uint32_t sps_temporal_mvp_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 166 | uint32_t strong_intra_smoothing_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 167 | uint32_t dependent_slice_segments_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 168 | uint32_t output_flag_present_flag : 1; //!< Same as HEVC syntax element | |
| 169 | uint32_t num_extra_slice_header_bits : 3; //!< Same as HEVC syntax element | |
| 170 | uint32_t sign_data_hiding_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 171 | uint32_t cabac_init_present_flag : 1; //!< Same as HEVC syntax element | |
| 172 | uint32_t ReservedBits3 : 5; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 173 | }; | |
| 174 | ||
| 175 | uint32_t dwCodingParamToolFlags; | |
| 176 | }; | |
| 177 | ||
| 178 | union | |
| 179 | { | |
| 180 | struct | |
| 181 | { | |
| 182 | uint32_t constrained_intra_pred_flag : 1; //!< Same as HEVC syntax element | |
| 183 | uint32_t transform_skip_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 184 | uint32_t cu_qp_delta_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 185 | uint32_t pps_slice_chroma_qp_offsets_present_flag : 1; //!< Same as HEVC syntax element | |
| 186 | uint32_t weighted_pred_flag : 1; //!< Same as HEVC syntax element | |
| 187 | uint32_t weighted_bipred_flag : 1; //!< Same as HEVC syntax element | |
| 188 | uint32_t transquant_bypass_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 189 | uint32_t tiles_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 190 | uint32_t entropy_coding_sync_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 191 | uint32_t uniform_spacing_flag : 1; //!< Same as HEVC syntax element | |
| 192 | uint32_t loop_filter_across_tiles_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 193 | uint32_t pps_loop_filter_across_slices_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 194 | uint32_t deblocking_filter_override_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 195 | uint32_t pps_deblocking_filter_disabled_flag : 1; //!< Same as HEVC syntax element | |
| 196 | /*! \brief Same as HEVC syntax element. | |
| 197 | * | |
| 198 | * Host decoder should set the value properly based on syntax element restricted_ref_pic_lists_flag. If restricted_ref_pic_lists_flag equals 0, lists_modification_present_flag should be set to 1. | |
| 199 | */ | |
| 200 | uint32_t lists_modification_present_flag : 1; | |
| 201 | uint32_t slice_segment_header_extension_present_flag : 1; //!< Same as HEVC syntax element | |
| 202 | /*! \brief Indicates whether the current picture is an IRAP picture. | |
| 203 | * | |
| 204 | * This flag shall be equal to 1 when the current picture is an IRAP picture and shall be equal to 0 when the current picture is not an IRAP picture. | |
| 205 | */ | |
| 206 | uint32_t IrapPicFlag : 1; | |
| 207 | /*! \brief Indicates whether the current picture is an IDR picture. | |
| 208 | * | |
| 209 | * This flag shall be equal to 1 when the current picture is an IDR picture and shall be equal to 0 when the current picture is not an IDR picture. | |
| 210 | */ | |
| 211 | uint32_t IdrPicFlag : 1; | |
| 212 | /*! \brief Takes value 1 when all the slices are intra slices, 0 otherwise. | |
| 213 | */ | |
| 214 | uint32_t IntraPicFlag : 1; | |
| 215 | /*! \brief CRC values are requested if set to 1. | |
| 216 | */ | |
| 217 | uint32_t RequestCRC : 1; | |
| 218 | /*! \brief Histogram array is requested if set to 1. | |
| 219 | * | |
| 220 | * If set, SFC should be enabled to generate the histogram array per channel. If other operations by SFC are required such as scaling, the histogram is generated against the final pixel buffer after the operation is performed. | |
| 221 | */ | |
| 222 | uint32_t RequestHistogram : 1; | |
| 223 | uint32_t ReservedBits4 : 11; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 224 | }; | |
| 225 | ||
| 226 | uint32_t dwCodingSettingPicturePropertyFlags; | |
| 227 | }; | |
| 228 | ||
| 229 | char pps_cb_qp_offset; //!< Same as HEVC syntax element | |
| 230 | char pps_cr_qp_offset; //!< Same as HEVC syntax element | |
| 231 | uint8_t num_tile_columns_minus1; //!< Same as HEVC syntax element | |
| 232 | uint8_t num_tile_rows_minus1; //!< Same as HEVC syntax element | |
| 233 | uint16_t column_width_minus1[19]; //!< Same as HEVC syntax element | |
| 234 | uint16_t row_height_minus1[21]; //!< Same as HEVC syntax element | |
| 235 | uint8_t diff_cu_qp_delta_depth; //!< Same as HEVC syntax element | |
| 236 | char pps_beta_offset_div2; //!< Same as HEVC syntax element | |
| 237 | char pps_tc_offset_div2; //!< Same as HEVC syntax element | |
| 238 | uint8_t log2_parallel_merge_level_minus2; //!< Same as HEVC syntax element | |
| 239 | ||
| 240 | /*! \brief Picture order count value for the current picture. | |
| 241 | * | |
| 242 | * Value range is -2^31 to 2^31-1, inclusive. | |
| 243 | */ | |
| 244 | int32_t CurrPicOrderCntVal; | |
| 245 | /*! \brief FrameIdx for each entry specifies the surface index for all pictures that are or will be referred to by the current or future pictures. | |
| 246 | * | |
| 247 | * The valid entries are indexed from 0 to 126, inclusive. The PicFlags of non-valid entries (including the picture of the entry which is not referred by current picture or future pictures) should take value PICTURE_INVALID. A PicFlags setting of PICTURE_LONG_TERM_REFERENCE indicates if the picture is a long term reference or not. | |
| 248 | * NOTE: for interlace (field) pictures, the FrameIdx field of two RefFrameList entries may have same value and point to same reference surface. And in this case, application should allocate buffer size with double picture height to hold the whole picture. | |
| 249 | */ | |
| 250 | CODEC_PICTURE RefFrameList[15]; | |
| 251 | /*! \brief Picture order count value for each of the reference pictures in the DPB buffer surface, corresponding to the entries of RefFrameList[15]. | |
| 252 | */ | |
| 253 | int32_t PicOrderCntValList[15]; | |
| 254 | /*! \brief Contain the indices to the RefFrameList[] used in inter predection. | |
| 255 | * | |
| 256 | * The indices to the RefFrameList[] indicate all the reference pictures that may be used in inter prediction of the current picture and that may be used in inter prediction of one or more of the pictures following the current picture in decoding order. | |
| 257 | * When an entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] is not valid, it shall be set to 0xff. Invalid entries shall not be present between valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[]. Valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall have values in the range of 0 to 7, inclusive, and each corresponding entry in RefFrameList[] referred to by a valid entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall not have PicFlags equal to PICTURE_INVALID. Any entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] that is not equal to 0xFF shall not be equal to the value of any other entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] or RefPicSetLtCurr[]. | |
| 258 | */ | |
| 259 | uint8_t RefPicSetStCurrBefore[8]; | |
| 260 | /*! \brief Contain the indices to the RefFrameList[] used in inter predection. | |
| 261 | * | |
| 262 | * The indices to the RefFrameList[] indicate all the reference pictures that may be used in inter prediction of the current picture and that may be used in inter prediction of one or more of the pictures following the current picture in decoding order. | |
| 263 | * When an entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] is not valid, it shall be set to 0xff. Invalid entries shall not be present between valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[]. Valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall have values in the range of 0 to 7, inclusive, and each corresponding entry in RefFrameList[] referred to by a valid entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall not have PicFlags equal to PICTURE_INVALID. Any entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] that is not equal to 0xFF shall not be equal to the value of any other entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] or RefPicSetLtCurr[]. | |
| 264 | */ | |
| 265 | uint8_t RefPicSetStCurrAfter[8]; | |
| 266 | /*! \brief Contain the indices to the RefFrameList[] used in inter predection. | |
| 267 | * | |
| 268 | * The indices to the RefFrameList[] indicate all the reference pictures that may be used in inter prediction of the current picture and that may be used in inter prediction of one or more of the pictures following the current picture in decoding order. | |
| 269 | * When an entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] is not valid, it shall be set to 0xff. Invalid entries shall not be present between valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[]. Valid entries in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall have values in the range of 0 to 7, inclusive, and each corresponding entry in RefFrameList[] referred to by a valid entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] shall not have PicFlags equal to PICTURE_INVALID. Any entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] and RefPicSetLtCurr[] that is not equal to 0xFF shall not be equal to the value of any other entry in RefPicSetStCurrBefore[], RefPicSetStCurrAfter[] or RefPicSetLtCurr[]. | |
| 270 | */ | |
| 271 | uint8_t RefPicSetLtCurr[8]; | |
| 272 | /*! \brief Is a 16 entry array indicating whether or not a picture is a field picture. | |
| 273 | * | |
| 274 | * Each bit of the low 15 bits indicats if the associated picture in DPB is a field picture or not. Specifically, if ((RefFieldPicFlag >> i) & 0x01) > 0, then the referencepicture specified by RefFrameList[i] is a field picture. Otherwise, it is frame picture. For field picture, coresponding bit of RefBottomFieldFlag indicates the field polarity. The MSB, (RefFieldPicFlag >> 15) & 0x01, indicates the field or frame status of current decoded picture, CurrPic. | |
| 275 | */ | |
| 276 | uint16_t RefFieldPicFlag; | |
| 277 | /*! \brief Is a 16 entry array indicating the polarity of a picture. | |
| 278 | * | |
| 279 | * Each bit of the low 15 bits indicats the polarity of the associated reference field picture. If ((RefBottomFieldFlag >> i) & 0x01) > 0, then the reference picture takes odd lines in the surface specified by RefFrameList[i]. And ((RefBottomFieldFlag >> i) & 0x01) = 0 indicates the reference picture takes even lines. The MSB, ((RefBottomFieldFlag >> i) & 0x01), indicates the polarity of the current decoded picture, CurrPic. | |
| 280 | */ | |
| 281 | uint16_t RefBottomFieldFlag; | |
| 282 | /*! \brief Arbitrary number set by the host decoder to use as a tag in the status report feedback data. | |
| 283 | * | |
| 284 | * The value should not equal 0, and should be different in each call to Execute. | |
| 285 | */ | |
| 286 | uint32_t StatusReportFeedbackNumber; | |
| 287 | uint32_t dwLastSliceEndPos; | |
| 288 | ||
| 289 | uint16_t TotalNumEntryPointOffsets; //!< Total entrypoint offset in subset buffer | |
| 290 | } CODEC_HEVC_PIC_PARAMS, *PCODEC_HEVC_PIC_PARAMS; | |
| 291 | ||
| 292 | /*! \brief Slice-level parameters of a compressed picture for HEVC decoding. | |
| 293 | * | |
| 294 | * The slice control buffer is accompanied by a raw bitstream data buffer. The total quantity of data in the bitstream buffer (and the amount of data reported by the host decoder) shall be an integer multiple of 128 bytes. | |
| 295 | */ | |
| 296 | typedef struct _CODEC_HEVC_SLICE_PARAMS | |
| 297 | { | |
| 298 | /*! \brief Number of bytes in the bitstream data buffer that are associated with this slice control data structure. | |
| 299 | * | |
| 300 | * Starting with the byte at the offset given in slice_data_offset. The bitstream data buffer shall not contain additional byte stream NAL units in the bytes following BSNALunitDataLocation up to the location slice_data_offset + slice_data_size. If slice_data_offset + slice_data_size exceeds the boundary of current bitstream data buffer, the excess slice bytes should continue from the first byte of next bitstream data buffer. | |
| 301 | */ | |
| 302 | uint32_t slice_data_size; | |
| 303 | /*! \brief This member locates the NAL unit with nal_unit_type equal to 1 .. 8 for the current slice. | |
| 304 | * | |
| 305 | * At least one bit stream data buffer should be present which is associated with the slice control data buffer. If necessary, multiple bit stream data buffers are allowed, but not suggested. The size of the data in the bitstream data buffer (and the amount of data reported by the host decoder) shall be an integer multiple of 128 bytes. When the end of the slice data is not an even multiple of 128 bytes, the decoder should pad the end of the buffer with zeroes. When more than one bitstream data buffers are present, these data buffers should be in sequential order. They should be treated as if concatenated linearly with no space in between. The value of slice_data_offset is the byte offset, from the start of the first bitstream data buffer, of the first byte of the start code prefix in the byte stream NAL unit that contains the NAL unit with nal_unit_type equal to 1 .. 8. The current slice is the slice associated with this slice control data structure. The bitstream data buffer shall not contain NAL units with values of nal_unit_type outside the range [1 .. 8]. However, the accelerator shall allow any such NAL units to be present and should ignore their content if present. | |
| 306 | * Note: The bitstream data buffer shall contain the full NAL unit byte stream, either encrpted or clear. This means that the buffer will contain emulation_prevention_three_byte syntax elements where those elements are required to be present in a NAL unit, as defined in the HEVC specification. The bitstream data buffer may or may not contrain leading_zero_8bits, zero_byte, and trailing_zero_8bits syntax elements. If present, the accelerator shall ignore these elements. | |
| 307 | */ | |
| 308 | uint32_t slice_data_offset; | |
| 309 | ||
| 310 | // Long format specific | |
| 311 | uint16_t NumEmuPrevnBytesInSliceHdr; //!< Number of emulation prevention bytes in slice head; ByteOffsetToSliceData doesn't include these bytes. | |
| 312 | /*! \brief Byte offset to the location of the first byte of slice_data() data structure for the current slice in the bitstream data buffer. | |
| 313 | * | |
| 314 | * This byte offset is the offset within the RBSP date for the slice, relative to the starting position of the slice_header() in the RBSP. That is, it represents a byte offset after the removal of any emulation_prevention_three_byte syntax elements that precedes the start of the slice_data() in the NAL unit. | |
| 315 | */ | |
| 316 | uint32_t ByteOffsetToSliceData; | |
| 317 | /*! \brief Same as HEVC syntax element. | |
| 318 | * | |
| 319 | * For first slice in the picture, slice_segment_address shall be set to 0. | |
| 320 | */ | |
| 321 | uint32_t slice_segment_address; | |
| 322 | /*! \brief Specifies the surfaces of reference pictures | |
| 323 | * | |
| 324 | * The value of FrameIdx specifies the index of RefFrameList structure. And valid value range is [0..14, 0x7F]. Invalid entries are indicated by setting PicFlags to PICTURE_INVALID and the PicFlags value of PICTURE_LONG_TERM_REFERENCE has no meaning. | |
| 325 | * RefPicIdx[0][] corresponds to reference list 0. | |
| 326 | * RefPicIdx[1][] corresponds to reference list 1. | |
| 327 | * Each list may contain duplicated reference picture indexes. | |
| 328 | */ | |
| 329 | CODEC_PICTURE RefPicList[2][15]; | |
| 330 | union | |
| 331 | { | |
| 332 | uint32_t value; | |
| 333 | struct | |
| 334 | { | |
| 335 | uint32_t LastSliceOfPic : 1; //!< Specifies if current slice is the last slice of picture. | |
| 336 | uint32_t dependent_slice_segment_flag : 1; //!< Same as HEVC syntax element | |
| 337 | uint32_t slice_type : 2; //!< Same as HEVC syntax element | |
| 338 | uint32_t color_plane_id : 2; //!< Same as HEVC syntax element | |
| 339 | uint32_t slice_sao_luma_flag : 1; //!< Same as HEVC syntax element | |
| 340 | uint32_t slice_sao_chroma_flag : 1; //!< Same as HEVC syntax element | |
| 341 | uint32_t mvd_l1_zero_flag : 1; //!< Same as HEVC syntax element | |
| 342 | uint32_t cabac_init_flag : 1; //!< Same as HEVC syntax element | |
| 343 | uint32_t slice_temporal_mvp_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 344 | uint32_t slice_deblocking_filter_disabled_flag : 1; //!< Same as HEVC syntax element | |
| 345 | uint32_t collocated_from_l0_flag : 1; //!< Same as HEVC syntax element | |
| 346 | uint32_t slice_loop_filter_across_slices_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 347 | uint32_t reserved : 18; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 348 | }fields; | |
| 349 | }LongSliceFlags; | |
| 350 | ||
| 351 | /*! \brief Index to the RefPicList[0][] or RefPicList[1][]. | |
| 352 | * | |
| 353 | * It should be derived from HEVC syntax element collocated_ref_idx. When the HEVC syntax element slice_temporal_mvp_enabled_flag takes value 0, collocated_ref_idx should take value 0xFF. Valid value range is [0.. num_ref_idx_l0_active_minus1] or [0..num_ref_idx_l1_active_minus1] depending on collocated_from_l0_flag. If collocated_ref_idx takes a valid value, the corresponding entry of RefFrameList[] must contain a valid surface index. | |
| 354 | */ | |
| 355 | uint8_t collocated_ref_idx; | |
| 356 | /*! \brief Same as HEVC syntax element. | |
| 357 | * | |
| 358 | * If num_ref_idx_active_override_flag == 0, host decoder shall set their values with num_ref_idx_l0_default_minus1, and num_ref_idx_l1_default_minus1. | |
| 359 | */ | |
| 360 | uint8_t num_ref_idx_l0_active_minus1; | |
| 361 | /*! \brief Same as HEVC syntax element. | |
| 362 | * | |
| 363 | * If num_ref_idx_active_override_flag == 0, host decoder shall set their values with num_ref_idx_l0_default_minus1, and num_ref_idx_l1_default_minus1. | |
| 364 | */ | |
| 365 | uint8_t num_ref_idx_l1_active_minus1; | |
| 366 | char slice_qp_delta; //!< Same as HEVC syntax element | |
| 367 | char slice_cb_qp_offset; //!< Same as HEVC syntax element | |
| 368 | char slice_cr_qp_offset; //!< Same as HEVC syntax element | |
| 369 | char slice_beta_offset_div2; //!< Same as HEVC syntax element | |
| 370 | char slice_tc_offset_div2; //!< Same as HEVC syntax element | |
| 371 | /*! \brief Same as HEVC syntax element. | |
| 372 | * | |
| 373 | * Specifies the base 2 logarithm of the denominator for all luma weighting factors. Value range: 0 to 7, inclusive. | |
| 374 | */ | |
| 375 | uint8_t luma_log2_weight_denom; | |
| 376 | /*! \brief Same as HEVC syntax element. | |
| 377 | * | |
| 378 | * Specifies the base 2 logarithm of the denominator for all chroma weighting factors. Value range of luma_log2_weight_denom + delta_chroma_log2_weight_denom: 0 to 7, inclusive. | |
| 379 | */ | |
| 380 | uint8_t delta_chroma_log2_weight_denom; | |
| 381 | ||
| 382 | /*! \brief Same as HEVC syntax element. | |
| 383 | * | |
| 384 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 385 | */ | |
| 386 | char delta_luma_weight_l0[15]; | |
| 387 | /*! \brief Same as HEVC syntax element. | |
| 388 | * | |
| 389 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 390 | */ | |
| 391 | char luma_offset_l0[15]; | |
| 392 | /*! \brief Same as HEVC syntax element. | |
| 393 | * | |
| 394 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 395 | */ | |
| 396 | char delta_chroma_weight_l0[15][2]; | |
| 397 | /*! \brief Same as HEVC syntax element. | |
| 398 | * | |
| 399 | * If the corresponding chroma weight flags are 0, the value should also be set to 0. Please note that for range extension profiles other than main, main10, and their related intra or still image profiles, the data types are defined differrently. | |
| 400 | */ | |
| 401 | char ChromaOffsetL0[15][2]; | |
| 402 | ||
| 403 | /*! \brief Same as HEVC syntax element. | |
| 404 | * | |
| 405 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 406 | */ | |
| 407 | char delta_luma_weight_l1[15]; | |
| 408 | /*! \brief Same as HEVC syntax element. | |
| 409 | * | |
| 410 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 411 | */ | |
| 412 | char luma_offset_l1[15]; | |
| 413 | /*! \brief Same as HEVC syntax element. | |
| 414 | * | |
| 415 | * If the corresponding luma or chroma weight flags are 0, the value should also be set to default value according to HEVC specification. | |
| 416 | */ | |
| 417 | char delta_chroma_weight_l1[15][2]; | |
| 418 | /*! \brief Same as HEVC syntax element. | |
| 419 | * | |
| 420 | * If the corresponding chroma weight flags are 0, the value should also be set to 0. Please note that for range extension profiles other than main, main10, and their related intra or still image profiles, the data types are defined differrently. | |
| 421 | */ | |
| 422 | char ChromaOffsetL1[15][2]; | |
| 423 | ||
| 424 | /*! \brief Same as HEVC syntax element. | |
| 425 | * | |
| 426 | * HEVC spec variable MaxNumMergeCand can be derived by 5 - five_minus_max_num_merge_cand, and specifies the maximum number of merging MVP candidates supported in the slice. Value range: 0 to 4 inclusive. | |
| 427 | */ | |
| 428 | uint8_t five_minus_max_num_merge_cand; | |
| 429 | uint16_t num_entry_point_offsets; // [0..540] | |
| 430 | uint16_t EntryOffsetToSubsetArray; // [0..540] | |
| 431 | } CODEC_HEVC_SLICE_PARAMS, *PCODEC_HEVC_SLICE_PARAMS; | |
| 432 | ||
| 433 | ||
| 434 | /*! \brief Additional picture-level parameters of a compressed picture for HEVC decoding. | |
| 435 | * | |
| 436 | * Defined for profiles main12, main4:2:2 10, main4:2:2 12, main4:4:4, main4:4:4 10, main4:4:4 12 and their related intra and still picture profiles. | |
| 437 | */ | |
| 438 | typedef struct _CODEC_HEVC_EXT_PIC_PARAMS | |
| 439 | { | |
| 440 | union | |
| 441 | { | |
| 442 | struct | |
| 443 | { | |
| 444 | uint32_t transform_skip_rotation_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 445 | uint32_t transform_skip_context_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 446 | uint32_t implicit_rdpcm_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 447 | uint32_t explicit_rdpcm_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 448 | uint32_t extended_precision_processing_flag : 1; //!< Same as HEVC syntax element | |
| 449 | uint32_t intra_smoothing_disabled_flag : 1; //!< Same as HEVC syntax element | |
| 450 | uint32_t high_precision_offsets_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 451 | uint32_t persistent_rice_adaptation_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 452 | uint32_t cabac_bypass_alignment_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 453 | uint32_t cross_component_prediction_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 454 | uint32_t chroma_qp_offset_list_enabled_flag : 1; //!< Same as HEVC syntax element | |
| 455 | uint32_t BitDepthLuma16 : 1; //!< Same as HEVC syntax element | |
| 456 | uint32_t BitDepthChroma16 : 1; //!< Same as HEVC syntax element | |
| 457 | uint32_t ReservedBits5 : 19; //!< Value is used for alignemnt and has no meaning, set to 0. | |
| 458 | } fields; | |
| 459 | uint32_t dwRangeExtensionPropertyFlags; | |
| 460 | } PicRangeExtensionFlags; | |
| 461 | ||
| 462 | uint8_t diff_cu_chroma_qp_offset_depth; //!< Same as HEVC syntax element, [0..3] | |
| 463 | uint8_t chroma_qp_offset_list_len_minus1; //!< Same as HEVC syntax element, [0..5] | |
| 464 | uint8_t log2_sao_offset_scale_luma; //!< Same as HEVC syntax element, [0..6] | |
| 465 | uint8_t log2_sao_offset_scale_chroma; //!< Same as HEVC syntax element, [0..6] | |
| 466 | uint8_t log2_max_transform_skip_block_size_minus2; //!< Same as HEVC syntax element | |
| 467 | char cb_qp_offset_list[6]; //!< Same as HEVC syntax element, [-12..12] | |
| 468 | char cr_qp_offset_list[6]; //!< Same as HEVC syntax element, [-12..12] | |
| 469 | } CODEC_HEVC_EXT_PIC_PARAMS, *PCODEC_HEVC_EXT_PIC_PARAMS; | |
| 470 | ||
| 471 | ||
| 472 | /*! \brief Additional range extention slice-level parameters of a compressed picture for HEVC decoding. | |
| 473 | * | |
| 474 | * HEVC range extension profiles extend the luma and chroma offset values from 8 bits to 16 bits. | |
| 475 | */ | |
| 476 | typedef struct _CODEC_HEVC_EXT_SLICE_PARAMS | |
| 477 | { | |
| 478 | /*! \brief Same as HEVC syntax element. | |
| 479 | * | |
| 480 | * These set of values are the most significant 8-bit part of the corresponding luma_offset_l0[]. Combining with the luma_offset_l0[] will give the final values respectively. The sign for each parameter is determined by the sign of corresponding luma_offset_l0[]. | |
| 481 | */ | |
| 482 | int16_t luma_offset_l0[15]; | |
| 483 | /*! \brief Same as HEVC syntax element. | |
| 484 | * | |
| 485 | * These set of values are the most significant 8-bit part of the corresponding chroma_offset_l0[]. Combining with the chroma_offset_l0[] will give the final values respectively. The sign for each parameter is determined by the sign of corresponding chroma_offset_l0[]. | |
| 486 | */ | |
| 487 | int16_t ChromaOffsetL0[15][2]; | |
| 488 | /*! \brief Same as HEVC syntax element. | |
| 489 | * | |
| 490 | * These set of values are the most significant 8-bit part of the corresponding luma_offset_l1[]. Combining with the luma_offset_l1[] will give the final values respectively. The sign for each parameter is determined by the sign of corresponding luma_offset_l1[]. | |
| 491 | */ | |
| 492 | int16_t luma_offset_l1[15]; | |
| 493 | /*! \brief Same as HEVC syntax element. | |
| 494 | * | |
| 495 | * These set of values are the most significant 8-bit part of the corresponding chroma_offset_l1[]. Combining with the chroma_offset_l1[] will give the final values respectively. The sign for each parameter is determined by the sign of corresponding chroma_offset_l1[]. | |
| 496 | */ | |
| 497 | int16_t ChromaOffsetL1[15][2]; | |
| 498 | ||
| 499 | bool cu_chroma_qp_offset_enabled_flag; //!< Same as HEVC syntax element | |
| 500 | ||
| 501 | // For Screen Content Extension | |
| 502 | char slice_act_y_qp_offset; // [-12..12] | |
| 503 | char slice_act_cb_qp_offset; // [-12..12] | |
| 504 | char slice_act_cr_qp_offset; // [-12..12] | |
| 505 | unsigned char use_integer_mv_flag; | |
| 506 | } CODEC_HEVC_EXT_SLICE_PARAMS, *PCODEC_HEVC_EXT_SLICE_PARAMS; | |
| 507 | ||
| 508 | typedef struct _CODEC_HEVC_SUBSET_PARAMS | |
| 509 | { | |
| 510 | uint32_t entry_point_offset_minus1[440]; | |
| 511 | } CODEC_HEVC_SUBSET_PARAMS, *PCODEC_HEVC_SUBSET_PARAMS; | |
| 512 | #endif // __CODEC_DEF_DECODE_HEVC_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_decode_vc1.h | |
| 23 | //! \brief Defines decode VC1 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to JPEG decode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_DECODE_VC1_H__ | |
| 27 | #define __CODEC_DEF_DECODE_VC1_H__ | |
| 28 | ||
| 29 | // VC1 reference flags | |
| 30 | #define CODECHAL_WMV9_RANGE_ADJUSTMENT 0x00100000 | |
| 31 | #define CODECHAL_VC1_PROGRESSIVE 0x00200000 | |
| 32 | #define CODECHAL_VC1_TOP_FIELD_COMP 0x00010000 | |
| 33 | #define CODECHAL_VC1_TOP_FIELD_COMP_2 0x00020000 | |
| 34 | #define CODECHAL_VC1_BOT_FIELD_COMP 0x00040000 | |
| 35 | #define CODECHAL_VC1_BOT_FIELD_COMP_2 0x00080000 | |
| 36 | #define CODECHAL_VC1_FRAME_COMP (CODECHAL_VC1_TOP_FIELD_COMP | CODECHAL_VC1_BOT_FIELD_COMP) | |
| 37 | #define CODECHAL_VC1_ALL_COMP 0x000F0000 | |
| 38 | ||
| 39 | //! | |
| 40 | //! \enum Vc1FramPictureType | |
| 41 | //! \brief VC1 fram picture Types | |
| 42 | //! | |
| 43 | enum Vc1FramPictureType | |
| 44 | { | |
| 45 | vc1IFrame = 0, | |
| 46 | vc1PFrame, | |
| 47 | vc1BFrame, | |
| 48 | vc1BIFrame, | |
| 49 | vc1SkippedFrame | |
| 50 | }; | |
| 51 | ||
| 52 | //! | |
| 53 | //! \enum Vc1FieldPictureType | |
| 54 | //! \brief VC1 field picture Types | |
| 55 | //! | |
| 56 | enum Vc1FieldPictureType | |
| 57 | { | |
| 58 | vc1IIField = 0, | |
| 59 | vc1IPField, | |
| 60 | vc1PIField, | |
| 61 | vc1PPField, | |
| 62 | vc1BBField, | |
| 63 | vc1BBIField, | |
| 64 | vc1BIBField, | |
| 65 | vc1BIBIField | |
| 66 | }; | |
| 67 | ||
| 68 | //! | |
| 69 | //! \enum Vc1QuantizerType | |
| 70 | //! \brief VC-1 Spec Table 259: Quantizer Specification | |
| 71 | //! | |
| 72 | enum Vc1QuantizerType | |
| 73 | { | |
| 74 | vc1QuantizerImplicit = 0, // specified at frame level | |
| 75 | vc1QuantizerExplicit, // specified at frame level | |
| 76 | vc1QuantizerNonuniform, // used for all frames | |
| 77 | vc1QuantizerUniform // used for all frames | |
| 78 | }; | |
| 79 | ||
| 80 | typedef struct _CODEC_VC1_PIC_PARAMS | |
| 81 | { | |
| 82 | CODEC_PICTURE CurrPic; | |
| 83 | uint16_t DeblockedPicIdx; | |
| 84 | uint16_t ForwardRefIdx; | |
| 85 | uint16_t BackwardRefIdx; | |
| 86 | ||
| 87 | /* sequence layer for AP or meta data for SP and MP */ | |
| 88 | union | |
| 89 | { | |
| 90 | struct | |
| 91 | { | |
| 92 | uint32_t pulldown : 1; /* SEQUENCE_LAYER::PULLDOWN */ | |
| 93 | uint32_t interlace : 1; /* SEQUENCE_LAYER::INTERLACE */ | |
| 94 | uint32_t tfcntrflag : 1; /* SEQUENCE_LAYER::TFCNTRFLAG */ | |
| 95 | uint32_t finterpflag : 1; /* SEQUENCE_LAYER::FINTERPFLAG */ | |
| 96 | uint32_t psf : 1; /* SEQUENCE_LAYER::PSF */ | |
| 97 | uint32_t multires : 1; /* METADATA::MULTIRES */ | |
| 98 | uint32_t overlap : 1; /* METADATA::OVERLAP */ | |
| 99 | uint32_t syncmarker : 1; /* METADATA::SYNCMARKER */ | |
| 100 | uint32_t rangered : 1; /* METADATA::RANGERED */ | |
| 101 | uint32_t max_b_frames : 3; /* METADATA::MAXBFRAMES */ | |
| 102 | uint32_t AdvancedProfileFlag : 1; | |
| 103 | }; | |
| 104 | uint32_t value; | |
| 105 | } sequence_fields; | |
| 106 | ||
| 107 | uint16_t coded_width; /* ENTRY_POINT_LAYER::CODED_WIDTH */ | |
| 108 | uint16_t coded_height; /* ENTRY_POINT_LAYER::CODED_HEIGHT */ | |
| 109 | union | |
| 110 | { | |
| 111 | struct | |
| 112 | { | |
| 113 | uint32_t broken_link : 1; /* ENTRY_POINT_LAYER::BROKEN_LINK */ | |
| 114 | uint32_t closed_entry : 1; /* ENTRY_POINT_LAYER::CLOSED_ENTRY */ | |
| 115 | uint32_t panscan_flag : 1; /* ENTRY_POINT_LAYER::PANSCAN_FLAG */ | |
| 116 | uint32_t loopfilter : 1; /* ENTRY_POINT_LAYER::LOOPFILTER */ | |
| 117 | }; | |
| 118 | uint32_t value; | |
| 119 | } entrypoint_fields; | |
| 120 | uint8_t conditional_overlap_flag; /* ENTRY_POINT_LAYER::CONDOVER */ | |
| 121 | uint8_t fast_uvmc_flag; /* ENTRY_POINT_LAYER::FASTUVMC */ | |
| 122 | union | |
| 123 | { | |
| 124 | struct | |
| 125 | { | |
| 126 | uint32_t luma_flag : 1; /* ENTRY_POINT_LAYER::RANGE_MAPY_FLAG */ | |
| 127 | uint32_t luma : 3; /* ENTRY_POINT_LAYER::RANGE_MAPY */ | |
| 128 | uint32_t chroma_flag : 1; /* ENTRY_POINT_LAYER::RANGE_MAPUV_FLAG */ | |
| 129 | uint32_t chroma : 3; /* ENTRY_POINT_LAYER::RANGE_MAPUV */ | |
| 130 | }; | |
| 131 | uint32_t range_mapping_enabled; | |
| 132 | } range_mapping_fields; | |
| 133 | ||
| 134 | uint8_t UpsamplingFlag; | |
| 135 | uint8_t ScaleFactor; /* derived from BFRACTION*/ | |
| 136 | uint8_t b_picture_fraction; /* PICTURE_LAYER::BFRACTION */ | |
| 137 | uint8_t cbp_table; /* PICTURE_LAYER::CBPTAB/ICBPTAB */ | |
| 138 | uint8_t mb_mode_table; /* PICTURE_LAYER::MBMODETAB */ | |
| 139 | uint8_t range_reduction_frame; /* PICTURE_LAYER::RANGEREDFRM */ | |
| 140 | uint8_t rounding_control; /* PICTURE_LAYER::RNDCTRL */ | |
| 141 | uint8_t post_processing; /* PICTURE_LAYER::POSTPROC */ | |
| 142 | uint8_t picture_resolution_index; /* PICTURE_LAYER::RESPIC */ | |
| 143 | uint16_t luma_scale; /* PICTURE_LAYER::LUMSCALE */ | |
| 144 | uint16_t luma_shift; /* PICTURE_LAYER::LUMSHIFT */ | |
| 145 | union | |
| 146 | { | |
| 147 | struct | |
| 148 | { | |
| 149 | uint32_t picture_type : 3; /* PICTURE_LAYER::PTYPE */ | |
| 150 | uint32_t frame_coding_mode : 3; /* PICTURE_LAYER::FCM */ | |
| 151 | uint32_t top_field_first : 1; /* PICTURE_LAYER::TFF */ | |
| 152 | uint32_t is_first_field : 1; /* set to 1 if it is the first field */ | |
| 153 | uint32_t intensity_compensation : 1; /* PICTURE_LAYER::INTCOMP */ | |
| 154 | }; | |
| 155 | uint32_t value; | |
| 156 | } picture_fields; | |
| 157 | union | |
| 158 | { | |
| 159 | struct | |
| 160 | { | |
| 161 | uint32_t bitplane_present : 1; | |
| 162 | uint32_t mv_type_mb : 1; /* PICTURE::MVTYPEMB */ | |
| 163 | uint32_t direct_mb : 1; /* PICTURE::DIRECTMB */ | |
| 164 | uint32_t skip_mb : 1; /* PICTURE::SKIPMB */ | |
| 165 | uint32_t field_tx : 1; /* PICTURE::FIELDTX */ | |
| 166 | uint32_t forward_mb : 1; /* PICTURE::FORWARDMB */ | |
| 167 | uint32_t ac_pred : 1; /* PICTURE::ACPRED */ | |
| 168 | uint32_t overflags : 1; /* PICTURE::OVERFLAGS */ | |
| 169 | }; | |
| 170 | uint32_t value; | |
| 171 | } raw_coding; | |
| 172 | ||
| 173 | union | |
| 174 | { | |
| 175 | struct | |
| 176 | { | |
| 177 | uint32_t reference_distance_flag : 1; /* PICTURE_LAYER::REFDIST_FLAG */ | |
| 178 | uint32_t reference_distance : 5; /* PICTURE_LAYER::REFDIST */ | |
| 179 | uint32_t BwdReferenceDistance : 5; | |
| 180 | uint32_t num_reference_pictures : 1; /* PICTURE_LAYER::NUMREF */ | |
| 181 | uint32_t reference_field_pic_indicator : 1; /* PICTURE_LAYER::REFFIELD */ | |
| 182 | uint32_t reference_picture_flag : 1; /* set to 1 if it will be used as a reference picture */ | |
| 183 | }; | |
| 184 | uint32_t value; | |
| 185 | } reference_fields; | |
| 186 | union | |
| 187 | { | |
| 188 | struct | |
| 189 | { | |
| 190 | uint32_t MvMode : 4; | |
| 191 | uint32_t UnifiedMvMode : 3; /* Combination of MVMODE and MVMODE1 */ | |
| 192 | uint32_t mv_table : 3; /* PICTURE_LAYER::MVTAB/IMVTAB */ | |
| 193 | uint32_t two_mv_block_pattern_table : 2; /* PICTURE_LAYER::2MVBPTAB */ | |
| 194 | uint32_t four_mv_switch : 1; /* PICTURE_LAYER::4MVSWITCH */ | |
| 195 | uint32_t four_mv_block_pattern_table : 2; /* PICTURE_LAYER::4MVBPTAB */ | |
| 196 | uint32_t extended_mv_flag : 1; /* ENTRY_POINT_LAYER::EXTENDED_MV */ | |
| 197 | uint32_t extended_mv_range : 2; /* PICTURE_LAYER::MVRANGE */ | |
| 198 | uint32_t extended_dmv_flag : 1; /* ENTRY_POINT_LAYER::EXTENDED_DMV */ | |
| 199 | uint32_t extended_dmv_range : 2; /* PICTURE_LAYER::DMVRANGE */ | |
| 200 | uint32_t four_mv_allowed : 1; /* PICTURE_LAYER::4MVSWITCH */ | |
| 201 | }; | |
| 202 | uint32_t value; | |
| 203 | } mv_fields; | |
| 204 | union | |
| 205 | { | |
| 206 | struct | |
| 207 | { | |
| 208 | uint32_t dquant : 2; /* ENTRY_POINT_LAYER::DQUANT */ | |
| 209 | uint32_t quantizer : 2; /* ENTRY_POINT_LAYER::QUANTIZER */ | |
| 210 | uint32_t half_qp : 1; /* PICTURE_LAYER::HALFQP */ | |
| 211 | uint32_t AltPQuantEdgeMask : 4; /* Derived from DQUANT, DQUANTTFRM, DQPROFILE, DDQSBEDGE, DQDBEDGE, DQBILEVEL*/ | |
| 212 | uint32_t AltPQuantConfig : 2; /* Derived from DQUANT, DQUANTTFRM, DQPROFILE, DDQSBEDGE, DQDBEDGE, DQBILEVEL*/ | |
| 213 | uint32_t pic_quantizer_scale : 5; /* PICTURE_LAYER::PQUANT */ | |
| 214 | uint32_t pic_quantizer_type : 1; /* PICTURE_LAYER::PQUANTIZER */ | |
| 215 | uint32_t alt_pic_quantizer : 5; /* VOPDQUANT::ALTPQUANT */ | |
| 216 | }; | |
| 217 | uint32_t value; | |
| 218 | } pic_quantizer_fields; | |
| 219 | union | |
| 220 | { | |
| 221 | struct | |
| 222 | { | |
| 223 | uint32_t variable_sized_transform_flag : 1; /* ENTRY_POINT_LAYER::VSTRANSFORM */ | |
| 224 | uint32_t mb_level_transform_type_flag : 1; /* PICTURE_LAYER::TTMBF */ | |
| 225 | uint32_t frame_level_transform_type : 2; /* PICTURE_LAYER::TTFRM */ | |
| 226 | uint32_t transform_ac_codingset_idx1 : 2; /* PICTURE_LAYER::TRANSACFRM */ | |
| 227 | uint32_t transform_ac_codingset_idx2 : 2; /* PICTURE_LAYER::TRANSACFRM2 */ | |
| 228 | uint32_t intra_transform_dc_table : 1; /* PICTURE_LAYER::TRANSDCTAB */ | |
| 229 | }; | |
| 230 | uint32_t value; | |
| 231 | } transform_fields; | |
| 232 | ||
| 233 | uint32_t StatusReportFeedbackNumber; | |
| 234 | } CODEC_VC1_PIC_PARAMS, *PCODEC_VC1_PIC_PARAMS; | |
| 235 | ||
| 236 | typedef struct _CODEC_VC1_SLICE_PARAMS | |
| 237 | { | |
| 238 | uint32_t slice_data_size; /* number of bytes in the slice data buffer for this slice */ | |
| 239 | uint32_t slice_data_offset; /* the offset to the first byte of slice data */ | |
| 240 | uint32_t macroblock_offset; /* the offset to the first bit of MB from the first byte of slice data */ | |
| 241 | uint32_t slice_vertical_position; | |
| 242 | uint32_t b_picture_fraction; /* BFRACTION */ | |
| 243 | uint32_t number_macroblocks; /* number of macroblocks in the slice */ | |
| 244 | } CODEC_VC1_SLICE_PARAMS, *PCODEC_VC1_SLICE_PARAMS; | |
| 245 | ||
| 246 | typedef struct _CODEC_VC1_MB_PARAMS | |
| 247 | { | |
| 248 | uint16_t mb_address; | |
| 249 | uint8_t mb_skips_following; /* the number of skipped macroblocks to be generated following the current macroblock */ | |
| 250 | uint8_t num_coef[CODEC_NUM_BLOCK_PER_MB]; /* the number of coefficients in the residual difference data buffer for each block i of the macroblock */ | |
| 251 | uint32_t data_offset; /* data offset in the residual data buffer, byte offset (32-bit multiple index) */ | |
| 252 | uint32_t data_length; /* length of the residual data for the macroblock */ | |
| 253 | union | |
| 254 | { | |
| 255 | struct | |
| 256 | { | |
| 257 | uint16_t intra_mb : 1; | |
| 258 | uint16_t motion_forward : 1; | |
| 259 | uint16_t motion_backward : 1; | |
| 260 | uint16_t motion_4mv : 1; | |
| 261 | uint16_t h261_loopfilter : 1; | |
| 262 | uint16_t field_residual : 1; | |
| 263 | uint16_t mb_scan_method : 2; | |
| 264 | uint16_t motion_type : 2; | |
| 265 | uint16_t host_resid_diff : 1; | |
| 266 | uint16_t reserved : 1; | |
| 267 | uint16_t mvert_field_sel_0 : 1; | |
| 268 | uint16_t mvert_field_sel_1 : 1; | |
| 269 | uint16_t mvert_field_sel_2 : 1; | |
| 270 | uint16_t mvert_field_sel_3 : 1; | |
| 271 | }; | |
| 272 | uint16_t value; | |
| 273 | } mb_type; | |
| 274 | union | |
| 275 | { | |
| 276 | struct | |
| 277 | { | |
| 278 | uint16_t block_coded_pattern : 6; | |
| 279 | uint16_t block_luma_intra : 4; | |
| 280 | uint16_t block_chroma_intra : 1; | |
| 281 | uint16_t : 5; | |
| 282 | }; | |
| 283 | uint16_t value; | |
| 284 | } pattern_code; | |
| 285 | union | |
| 286 | { | |
| 287 | struct | |
| 288 | { | |
| 289 | uint16_t mv_x : 16; | |
| 290 | uint16_t mv_y : 16; | |
| 291 | }; | |
| 292 | uint32_t value; | |
| 293 | } motion_vector[4]; | |
| 294 | } CODEC_VC1_MB_PARAMS, *PCODEC_VC1_MB_PARAMS; | |
| 295 | ||
| 296 | #endif // __CODEC_DEF_DECODE_VC1_H__ | |
| 297 |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_decode_vp9.h | |
| 23 | //! \brief Defines decode VP9 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to VP9 decode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_DECODE_VP9_H__ | |
| 27 | #define __CODEC_DEF_DECODE_VP9_H__ | |
| 28 | ||
| 29 | #include "codec_def_common.h" | |
| 30 | #include "codec_def_common_vp9.h" | |
| 31 | ||
| 32 | #define CODEC_VP9_MAX_SEGMENTS 8 | |
| 33 | #define CODECHAL_MAX_CUR_NUM_REF_FRAME_VP9 3 | |
| 34 | #define CODECHAL_DECODE_VP9_MAX_NUM_REF_FRAME 8 | |
| 35 | #define CODECHAL_VP9_NUM_MV_BUFFERS 2 | |
| 36 | #define VP9_CENC_PRIMITIVE_CMD_OFFSET_IN_DW 16 | |
| 37 | ||
| 38 | //! | |
| 39 | //! \enum CODECHAL_DECODE_VP9_SEG_LVL_FEATURES | |
| 40 | //! VP9 decode segment level | |
| 41 | //! | |
| 42 | typedef enum | |
| 43 | { | |
| 44 | CODECHAL_DECODE_VP9_SEG_LVL_ALT_Q = 0, //!< Use alternate Quantizer | |
| 45 | CODECHAL_DECODE_VP9_SEG_LVL_ALT_LF = 1, //!< Use alternate loop filter value | |
| 46 | CODECHAL_DECODE_VP9_SEG_LVL_REF_FRAME = 2, //!< Optional Segment reference frame | |
| 47 | CODECHAL_DECODE_VP9_SEG_LVL_SKIP = 3, //!< Optional Segment (0,0) + skip mode | |
| 48 | CODECHAL_DECODE_VP9_SEG_LVL_MAX = 4 //!< Number of features supported | |
| 49 | } CODECHAL_DECODE_VP9_SEG_LVL_FEATURES; | |
| 50 | ||
| 51 | //! | |
| 52 | //! \enum CODECHAL_DECODE_VP9_MV_REFERENCE_FRAME | |
| 53 | //! VP9 decode mv reference | |
| 54 | //! | |
| 55 | typedef enum | |
| 56 | { | |
| 57 | CODECHAL_DECODE_VP9_NONE = -1, | |
| 58 | CODECHAL_DECODE_VP9_INTRA_FRAME = 0, | |
| 59 | CODECHAL_DECODE_VP9_LAST_FRAME = 1, | |
| 60 | CODECHAL_DECODE_VP9_GOLDEN_FRAME = 2, | |
| 61 | CODECHAL_DECODE_VP9_ALTREF_FRAME = 3, | |
| 62 | CODECHAL_DECODE_VP9_MAX_REF_FRAMES = 4 | |
| 63 | } CODECHAL_DECODE_VP9_MV_REFERENCE_FRAME; | |
| 64 | ||
| 65 | // VP9 Decode Slice Parameter Buffer | |
| 66 | typedef struct _CODEC_VP9_SLICE_PARAMS { | |
| 67 | uint32_t BSNALunitDataLocation; | |
| 68 | uint32_t SliceBytesInBuffer; | |
| 69 | uint16_t wBadSliceChopping; | |
| 70 | } CODEC_VP9_SLICE_PARAMS, *PCODEC_VP9_SLICE_PARAMS; | |
| 71 | ||
| 72 | // VP9 Picture Parameters Buffer | |
| 73 | typedef struct _CODEC_VP9_PIC_PARAMS | |
| 74 | { | |
| 75 | uint16_t FrameHeightMinus1; // [0..65535] | |
| 76 | uint16_t FrameWidthMinus1; // [0..65535] | |
| 77 | ||
| 78 | union | |
| 79 | { | |
| 80 | struct | |
| 81 | { | |
| 82 | uint32_t frame_type : 1; // [0..1] | |
| 83 | uint32_t show_frame : 1; // [0..1] | |
| 84 | uint32_t error_resilient_mode : 1; // [0..1] | |
| 85 | uint32_t intra_only : 1; // [0..1] | |
| 86 | uint32_t LastRefIdx : 3; // [0..7] | |
| 87 | uint32_t LastRefSignBias : 1; // [0..1] | |
| 88 | uint32_t GoldenRefIdx : 3; // [0..7] | |
| 89 | uint32_t GoldenRefSignBias : 1; // [0..1] | |
| 90 | uint32_t AltRefIdx : 3; // [0..7] | |
| 91 | uint32_t AltRefSignBias : 1; // [0..1] | |
| 92 | uint32_t allow_high_precision_mv : 1; // [0..1] | |
| 93 | uint32_t mcomp_filter_type : 3; // [0..7] | |
| 94 | uint32_t frame_parallel_decoding_mode : 1; // [0..1] | |
| 95 | uint32_t segmentation_enabled : 1; // [0..1] | |
| 96 | uint32_t segmentation_temporal_update : 1; // [0..1] | |
| 97 | uint32_t segmentation_update_map : 1; // [0..1] | |
| 98 | uint32_t reset_frame_context : 2; // [0..3] | |
| 99 | uint32_t refresh_frame_context : 1; // [0..1] | |
| 100 | uint32_t frame_context_idx : 2; // [0..3] | |
| 101 | uint32_t LosslessFlag : 1; // [0..1] | |
| 102 | uint32_t ReservedField : 2; // [0] | |
| 103 | } fields; | |
| 104 | uint32_t value; | |
| 105 | } PicFlags; | |
| 106 | ||
| 107 | CODEC_PICTURE RefFrameList[8]; // [0..127, 0xFF] | |
| 108 | CODEC_PICTURE CurrPic; // [0..127] | |
| 109 | uint8_t filter_level; // [0..63] | |
| 110 | uint8_t sharpness_level; // [0..7] | |
| 111 | uint8_t log2_tile_rows; // [0..2] | |
| 112 | uint8_t log2_tile_columns; // [0..5] | |
| 113 | uint8_t UncompressedHeaderLengthInBytes; // [0..255] | |
| 114 | uint16_t FirstPartitionSize; // [0..65535] | |
| 115 | uint8_t SegTreeProbs[7]; | |
| 116 | uint8_t SegPredProbs[3]; | |
| 117 | ||
| 118 | uint32_t BSBytesInBuffer; | |
| 119 | ||
| 120 | uint32_t StatusReportFeedbackNumber; | |
| 121 | ||
| 122 | uint8_t profile; // [0..3] | |
| 123 | uint8_t BitDepthMinus8; // [0, 2, 4] | |
| 124 | uint8_t subsampling_x; // [0..1] | |
| 125 | uint8_t subsampling_y; // [0..1] | |
| 126 | } CODEC_VP9_PIC_PARAMS, *PCODEC_VP9_PIC_PARAMS; | |
| 127 | ||
| 128 | typedef struct _CODEC_VP9_SEGMENT_PARAMS | |
| 129 | { | |
| 130 | CODEC_VP9_SEG_PARAMS SegData[8]; | |
| 131 | } CODEC_VP9_SEGMENT_PARAMS, *PCODEC_VP9_SEGMENT_PARAMS; | |
| 132 | ||
| 133 | #endif |
| 0 | /* | |
| 1 | * Copyright (c) 2018-2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_encode.h | |
| 23 | //! \brief Defines encode types and macros shared by CodecHal and DDI layer | |
| 24 | //! \details Applies to encode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | ||
| 27 | #ifndef __CODEC_DEF_ENCODE_H__ | |
| 28 | #define __CODEC_DEF_ENCODE_H__ | |
| 29 | #include "mos_os.h" | |
| 30 | ||
| 31 | //! | |
| 32 | //! \struct CodechalEncodeSeiData | |
| 33 | //! \brief Indicate the SeiData parameters | |
| 34 | //! | |
| 35 | struct CodechalEncodeSeiData | |
| 36 | { | |
| 37 | bool newSEIData; | |
| 38 | uint32_t dwSEIDataSize; | |
| 39 | uint32_t dwSEIBufSize; | |
| 40 | uint8_t* pSEIBuffer; | |
| 41 | }; | |
| 42 | ||
| 43 | struct MetaDataOffset | |
| 44 | { | |
| 45 | uint32_t dwEncodeErrorFlags = 0; | |
| 46 | uint32_t dwEncodedBitstreamWrittenBytesCount = 0; | |
| 47 | uint32_t dwWrittenSubregionsCount = 0; | |
| 48 | ||
| 49 | uint32_t dwEncodeStats = 0; | |
| 50 | uint32_t dwAverageQP = 0; | |
| 51 | uint32_t dwIntraCodingUnitsCount = 0; | |
| 52 | uint32_t dwInterCodingUnitsCount = 0; | |
| 53 | uint32_t dwSkipCodingUnitsCount = 0; | |
| 54 | uint32_t dwAverageMotionEstimationXDirection = 0; | |
| 55 | uint32_t dwAverageMotionEstimationYDirection = 0; | |
| 56 | ||
| 57 | uint32_t dwbSize = 0; | |
| 58 | uint32_t dwbStartOffset = 0; | |
| 59 | uint32_t dwbHeaderSize = 0; | |
| 60 | ||
| 61 | uint32_t dwMetaDataSize = 0; | |
| 62 | uint32_t dwMetaDataSubRegionSize = 0; | |
| 63 | }; | |
| 64 | ||
| 65 | //! | |
| 66 | //! \struct EncoderParams | |
| 67 | //! \brief Encoder parameters | |
| 68 | //! | |
| 69 | struct EncoderParams | |
| 70 | { | |
| 71 | CODECHAL_FUNCTION ExecCodecFunction; //!< High level codec functionality requested. | |
| 72 | ||
| 73 | PMOS_SURFACE psRawSurface; //!< Raw surface | |
| 74 | PMOS_SURFACE psReconSurface; //!< reconstructed surface | |
| 75 | PMOS_RESOURCE presBitstreamBuffer; //!< Output buffer for bitstream data. | |
| 76 | PMOS_RESOURCE presMetadataBuffer; //!< Output buffer for meta data. | |
| 77 | PMOS_RESOURCE presMbCodeSurface; //!< PAK objects provided by framework. | |
| 78 | PMOS_SURFACE psMbSegmentMapSurface; //!< [VP9] | |
| 79 | /* \brief [AVC & MPEG2] MB QP data provided by framework. | |
| 80 | * | |
| 81 | * When in CQP mode, the framework can provide this surface that contains a single QpY value for each macroblock to be used for encoding. If it is not provided, the frame level QpY(QpY + slice_qp_delta) will be used for all macroblocks. | |
| 82 | */ | |
| 83 | PMOS_SURFACE psMbQpDataSurface; //!< pointer to surface of Mb QP Data | |
| 84 | PCODEC_ENCODE_MB_CONTROL pMbCtrlBuffer; //!< [AVC] MB contrl map provided by framework | |
| 85 | PMOS_SURFACE psMbDisableSkipMapSurface; //!< [AVC] MB disable skip map provided by framework | |
| 86 | PMOS_SURFACE psCoeffSurface; //!< [VP9] | |
| 87 | PMOS_RESOURCE presCoeffProbabilityBuffer; //!< [VP9] Coefficient probabilities provided by framework. | |
| 88 | bool bNewSeq; //!< Indicates the start of a new sequence. | |
| 89 | bool bPicQuant; //!< Indicates whether the scaling list is for SPS (0) or PPS (1). | |
| 90 | bool bNewQmatrixData; //!< Indicates that new QM data was provided by framework. | |
| 91 | CodechalEncodeSeiData *pSeiData; //!< [AVC & HEVC] Information pertaining to pSeiParamBuffer. | |
| 92 | uint32_t dwSEIDataOffset; //!< [AVC & HEVC] Offset to the first SEI message within pSeiParamBuffer. | |
| 93 | uint8_t *pSeiParamBuffer; //!< [AVC & HEVC] Packed SEI messages provided by the framework | |
| 94 | uint32_t dwNumSlices; //!< Number of slice data structures in pSliceParams. | |
| 95 | uint32_t dwAppDataSize; //!< [JPEG] | |
| 96 | uint32_t dwNumHuffBuffers; //!< [JPEG] | |
| 97 | uint32_t dwMbDataBufferSize; //!< Size of the data contained in presMbCodeSurface | |
| 98 | uint32_t dwBitstreamSize; //!< Maximum amount of data to be output to presBitstreamBuffer. | |
| 99 | bool bNewVuiData; //!< [AVC & MPEG2] Indicates that pVuiParams is present and expected to be valid. | |
| 100 | bool bJpegQuantMatrixSent; //!< [JPEG] Indicates whether a quant matrix was sent by the framework. | |
| 101 | PBSBuffer pBSBuffer; //!< Packed header data provided by the framework to be inserted in the bitstream. | |
| 102 | PCODECHAL_NAL_UNIT_PARAMS *ppNALUnitParams; //!< Information about the packed header data in pBSBuffer. | |
| 103 | uint32_t uiNumNalUnits; //!< Number of NAL units in ppNALUnitParams. | |
| 104 | void *pSlcHeaderData; //!< [AVC, HEVC, & MPEG2] Packed slice header data provided by the framework. | |
| 105 | bool bAcceleratorHeaderPackingCaps; //!< [AVC] Indicates whether or not the driver is packing the slice headers. | |
| 106 | uint32_t uiSlcStructCaps; //!< [AVC] Slice capability information, formatted as CODEC_SLICE_STRUCTS | |
| 107 | bool bMADEnabled; //!< MAD is enabled | |
| 108 | bool bMbQpDataEnabled; //!< [AVC & MPEG2] Indicates that psMbQpDataSurface is present. | |
| 109 | bool bMbDisableSkipMapEnabled; //!< [AVC] Indicates that psMbDisableSkipMapSurface is present. | |
| 110 | bool bReportStatisticsEnabled; //!< [HEVC] Indicates whether statistic reporting is enabled, disabled by default. | |
| 111 | bool bQualityImprovementEnable; //!< [HEVC] Indicates whether quality improvement is enabled, disabled by default. | |
| 112 | bool newSeqHeader; //!< [AVC] Flag for new Sequence Header. | |
| 113 | bool newPpsHeader; //!< [AVC] Flag for new PPS Header. | |
| 114 | bool arbitraryNumMbsInSlice; //!< [AVC] Flag to indicate if the sliceMapSurface needs to be programmed or not. | |
| 115 | ||
| 116 | void *pSeqParams; //!< Sequence parameter set structure defined per standard. | |
| 117 | void *pPicParams; //!< Picture parameter set structure defined per standard. | |
| 118 | void *pVuiParams; //!< [AVC & MPEG2] Picture parameter set structure defined per standard. | |
| 119 | void *pSliceParams; //!< Slice data array defined per standard, expect dwNumSlices entries. | |
| 120 | void *pSegmentParams; //!< [VP9] | |
| 121 | void *pIQMatrixBuffer; //!< [AVC, HEVC, & MPEG2] IQ parameter structure defined per standard. | |
| 122 | ||
| 123 | // AVC Specific Parameters | |
| 124 | void *pIQWeightScaleLists; //!< list of IQ Weight scale | |
| 125 | void *pAVCQCParams; //!< AVC QC parameters | |
| 126 | void *pAVCRoundingParams; //!< AVC rounding parameters | |
| 127 | ||
| 128 | void *pQuantData; | |
| 129 | PMOS_RESOURCE presDistortionDataSurface; | |
| 130 | uint32_t uiFrameRate; | |
| 131 | ||
| 132 | bool bSegmentMapProvided; //!< [VP9] | |
| 133 | ||
| 134 | void *pMpeg2UserDataListHead; //!< [MPEG2] | |
| 135 | ||
| 136 | void *pHuffmanTable; //!< [JPEG] | |
| 137 | void *pQuantizationTable; //!< [JPEG] | |
| 138 | void *pApplicationData; //!< [JPEG] | |
| 139 | ||
| 140 | void *pFeiPicParams; //!< [FEI] | |
| 141 | void *pPreEncParams; //!< [FEI] | |
| 142 | ||
| 143 | // HEVC Specific Parameters | |
| 144 | bool bVdencActive; //!< Indicate if vdenc is active | |
| 145 | bool advanced; //!< Indicate if vdenc is active | |
| 146 | ||
| 147 | MOS_SURFACE rawSurface; //!< Raw surface | |
| 148 | MOS_SURFACE reconSurface; //!< reconstructed surface | |
| 149 | MOS_RESOURCE resBitstreamBuffer; //!< Output buffer for bitstream data. | |
| 150 | MOS_SURFACE mbQpSurface; | |
| 151 | MOS_SURFACE disableSkipMapSurface; //!< [AVC] MB disable skip map provided by framework | |
| 152 | HANDLE gpuAppTaskEvent; // MSDK event handling | |
| 153 | //Call back to application. This informs the application all ENC kernel workload is submitted(in case of HEVC VME) | |
| 154 | //such that Application can make use of render engine when encoder is working on PAK. this helps in efficient utilisation of | |
| 155 | //Render engine for improving the performance as the render engine will be idle when encoder is working on PAK. | |
| 156 | void * plastEncKernelSubmissionCompleteCallback; | |
| 157 | ||
| 158 | ||
| 159 | bool bStreamOutEnable; | |
| 160 | PMOS_RESOURCE pStreamOutBuffer; // StreamOut buffer | |
| 161 | bool bCoeffRoundTag; | |
| 162 | uint32_t uiRoundIntra; | |
| 163 | uint32_t uiRoundInter; | |
| 164 | ||
| 165 | PMOS_RESOURCE presMbInlineData; | |
| 166 | PMOS_RESOURCE presMbConstSurface; | |
| 167 | PMOS_RESOURCE presVMEOutSurface; | |
| 168 | uint32_t uiMVoffset; // App provides PAK objects and MV data in the same surface. This is offset to MV Data. | |
| 169 | bool fullHeaderInAppData; //!< [JPEG] | |
| 170 | uint32_t uiOverallNALPayload; | |
| 171 | MetaDataOffset metaDataOffset; | |
| 172 | void * pSliceHeaderParams; //!< [HEVC] | |
| 173 | ||
| 174 | PMOS_RESOURCE m_presPredication = nullptr; //! \brief [Predication] Resource for predication | |
| 175 | uint64_t m_predicationResOffset = 0; //! \brief [Predication] Offset for Predication resource | |
| 176 | bool m_predicationNotEqualZero = false; //! \brief [Predication] Predication mode | |
| 177 | bool m_predicationEnabled = false; //! \brief [Predication] Indicates whether or not Predication is enabled | |
| 178 | PMOS_RESOURCE *m_tempPredicationBuffer = nullptr; //! \brief [Predication] Temp buffer for Predication | |
| 179 | ||
| 180 | bool m_setMarkerEnabled = false; //! \brief [SetMarker] Indicates whether or not SetMarker is enabled | |
| 181 | PMOS_RESOURCE m_presSetMarker = nullptr; //! \brief [SetMarker] Resource for SetMarker | |
| 182 | }; | |
| 183 | ||
| 184 | #endif // !__CODEC_DEF_ENCODE_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_encode_avc.h | |
| 23 | //! \brief Defines encode AVC types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to AVC encode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_ENCODE_AVC_H__ | |
| 27 | #define __CODEC_DEF_ENCODE_AVC_H__ | |
| 28 | ||
| 29 | #include "codec_def_common_avc.h" | |
| 30 | #include "codec_def_common_encode.h" | |
| 31 | #include "codec_def_common.h" | |
| 32 | ||
| 33 | #define CODEC_AVC_NUM_MAX_DIRTY_RECT 4 | |
| 34 | #define CODEC_AVC_NUM_QP 52 | |
| 35 | ||
| 36 | #define CODEC_AVC_NUM_WP_FRAME 8 | |
| 37 | #define CODEC_AVC_MAX_FORWARD_WP_FRAME 6 | |
| 38 | #define CODEC_AVC_MAX_BACKWARD_WP_FRAME 2 | |
| 39 | #define CODEC_AVC_WP_OUTPUT_L0_START 0 | |
| 40 | #define CODEC_AVC_WP_OUTPUT_L1_START 6 | |
| 41 | ||
| 42 | #define ENCODE_VDENC_AVC_MAX_ROI_NUMBER_G9 3 // Max 4 regions including non-ROI - used from DDI | |
| 43 | #define ENCODE_VDENC_AVC_MAX_ROI_NUMBER_ADV 16 // Max 16 regions including non-ROI - used from DDI | |
| 44 | #define ENCODE_VDENC_AVC_MIN_ROI_DELTA_QP_G9 -8 // Min delta QP for VDEnc ROI | |
| 45 | #define ENCODE_VDENC_AVC_MAX_ROI_DELTA_QP_G9 7 // Max delta QP for VDEnc ROI | |
| 46 | ||
| 47 | #define ENCODE_DP_AVC_MAX_ROI_NUMBER 4 | |
| 48 | #define ENCODE_DP_AVC_MAX_ROI_NUM_BRC 8 | |
| 49 | ||
| 50 | #define ENCODE_VDENC_AVC_MAX_ROI_NUMBER 3 | |
| 51 | ||
| 52 | #define ENCODE_AVC_MAX_SLICES_SUPPORTED 256 // Limted to 256 due to memory constraints. | |
| 53 | ||
| 54 | //AVC | |
| 55 | #define CODECHAL_ENCODE_AVC_ROI_WIDTH_SCALE_FACTOR 16 | |
| 56 | #define CODECHAL_ENCODE_AVC_ROI_FRAME_HEIGHT_SCALE_FACTOR 16 | |
| 57 | #define CODECHAL_ENCODE_AVC_ROI_FIELD_HEIGHT_SCALE_FACTOR 32 | |
| 58 | #define CODECHAL_ENCODE_AVC_MAX_ROI_NUMBER 4 | |
| 59 | ||
| 60 | typedef struct _CODECHAL_ENCODE_AVC_ROUNDING_PARAMS | |
| 61 | { | |
| 62 | bool bEnableCustomRoudingIntra; | |
| 63 | bool bEnableCustomRoudingInter; | |
| 64 | uint32_t dwRoundingIntra; | |
| 65 | uint32_t dwRoundingInter; | |
| 66 | } CODECHAL_ENCODE_AVC_ROUNDING_PARAMS, *PCODECHAL_ENCODE_AVC_ROUNDING_PARAMS; | |
| 67 | ||
| 68 | // video quality control parameters | |
| 69 | typedef struct _CODECHAL_ENCODE_AVC_QUALITY_CTRL_PARAMS | |
| 70 | { | |
| 71 | union | |
| 72 | { | |
| 73 | struct | |
| 74 | { | |
| 75 | // Disables skip check for ENC. | |
| 76 | unsigned int skipCheckDisable : 1; | |
| 77 | // Indicates app will override default driver FTQ settings using FTQEnable. | |
| 78 | unsigned int FTQOverride : 1; | |
| 79 | // Enables/disables FTQ. | |
| 80 | unsigned int FTQEnable : 1; | |
| 81 | // Indicates the app will provide the Skip Threshold LUT to use when FTQ is | |
| 82 | // enabled (FTQSkipThresholdLUT), else default driver thresholds will be used. | |
| 83 | unsigned int FTQSkipThresholdLUTInput : 1; | |
| 84 | // Indicates the app will provide the Skip Threshold LUT to use when FTQ is | |
| 85 | // disabled (NonFTQSkipThresholdLUT), else default driver thresholds will be used. | |
| 86 | unsigned int NonFTQSkipThresholdLUTInput : 1; | |
| 87 | // Control to enable the ENC mode decision algorithm to bias to fewer B Direct/Skip types. | |
| 88 | // Applies only to B frames, all other frames will ignore this setting. | |
| 89 | unsigned int directBiasAdjustmentEnable : 1; | |
| 90 | // Enables global motion bias. | |
| 91 | unsigned int globalMotionBiasAdjustmentEnable : 1; | |
| 92 | // MV cost scaling ratio for HME predictors. It is used when | |
| 93 | // globalMotionBiasAdjustmentEnable == 1, else it is ignored. Values are: | |
| 94 | // 0: set MV cost to be 0 for HME predictor. | |
| 95 | // 1: scale MV cost to be ? of the default value for HME predictor. | |
| 96 | // 2: scale MV cost to be ? of the default value for HME predictor. | |
| 97 | // 3: scale MV cost to be 1/8 of the default value for HME predictor. | |
| 98 | unsigned int HMEMVCostScalingFactor : 2; | |
| 99 | //disable HME | |
| 100 | unsigned int HMEDisable : 1; | |
| 101 | //disable Super HME | |
| 102 | unsigned int SuperHMEDisable : 1; | |
| 103 | //disable Ultra HME | |
| 104 | unsigned int UltraHMEDisable : 1; | |
| 105 | // Force RepartitionCheck | |
| 106 | unsigned int ForceRepartitionCheck : 2; | |
| 107 | ||
| 108 | }; | |
| 109 | unsigned int encControls; | |
| 110 | }; | |
| 111 | ||
| 112 | // Maps QP to skip thresholds when FTQ is enabled. Valid range is 0-255. | |
| 113 | unsigned char FTQSkipThresholdLUT[CODEC_AVC_NUM_QP]; | |
| 114 | // Maps QP to skip thresholds when FTQ is disabled. Valid range is 0-65535. | |
| 115 | unsigned short NonFTQSkipThresholdLUT[CODEC_AVC_NUM_QP]; | |
| 116 | // Reserved for future use. | |
| 117 | unsigned int reserved[8]; | |
| 118 | } CODECHAL_ENCODE_AVC_QUALITY_CTRL_PARAMS, *PCODECHAL_ENCODE_AVC_QUALITY_CTRL_PARAMS; | |
| 119 | ||
| 120 | // AVC VUI Parameters | |
| 121 | typedef struct _CODECHAL_ENCODE_AVC_VUI_PARAMS | |
| 122 | { | |
| 123 | uint32_t aspect_ratio_info_present_flag : 1; | |
| 124 | uint32_t overscan_info_present_flag : 1; | |
| 125 | uint32_t overscan_appropriate_flag : 1; | |
| 126 | uint32_t video_signal_type_present_flag : 1; | |
| 127 | uint32_t video_full_range_flag : 1; | |
| 128 | uint32_t colour_description_present_flag : 1; | |
| 129 | uint32_t chroma_loc_info_present_flag : 1; | |
| 130 | uint32_t timing_info_present_flag : 1; | |
| 131 | uint32_t fixed_frame_rate_flag : 1; | |
| 132 | uint32_t nal_hrd_parameters_present_flag : 1; | |
| 133 | uint32_t vcl_hrd_parameters_present_flag : 1; | |
| 134 | uint32_t low_delay_hrd_flag : 1; | |
| 135 | uint32_t pic_struct_present_flag : 1; | |
| 136 | uint32_t bitstream_restriction_flag : 1; | |
| 137 | uint32_t motion_vectors_over_pic_boundaries_flag : 1; | |
| 138 | uint32_t : 17; | |
| 139 | uint16_t sar_width; | |
| 140 | uint16_t sar_height; | |
| 141 | uint8_t aspect_ratio_idc; | |
| 142 | uint8_t video_format; | |
| 143 | uint8_t colour_primaries; | |
| 144 | uint8_t transfer_characteristics; | |
| 145 | uint8_t matrix_coefficients; | |
| 146 | uint8_t chroma_sample_loc_type_top_field; | |
| 147 | uint8_t chroma_sample_loc_type_bottom_field; | |
| 148 | uint8_t max_bytes_per_pic_denom; | |
| 149 | uint8_t max_bits_per_mb_denom; | |
| 150 | uint8_t log2_max_mv_length_horizontal; | |
| 151 | uint8_t log2_max_mv_length_vertical; | |
| 152 | uint8_t num_reorder_frames; | |
| 153 | uint32_t num_units_in_tick; | |
| 154 | uint32_t time_scale; | |
| 155 | uint8_t max_dec_frame_buffering; | |
| 156 | ||
| 157 | //HRD parameters | |
| 158 | uint8_t cpb_cnt_minus1; | |
| 159 | uint8_t bit_rate_scale; | |
| 160 | uint8_t cpb_size_scale; | |
| 161 | uint32_t bit_rate_value_minus1[32]; | |
| 162 | uint32_t cpb_size_value_minus1[32]; | |
| 163 | uint32_t cbr_flag; // bit 0 represent SchedSelIdx 0 and so on | |
| 164 | uint8_t initial_cpb_removal_delay_length_minus1; | |
| 165 | uint8_t cpb_removal_delay_length_minus1; | |
| 166 | uint8_t dpb_output_delay_length_minus1; | |
| 167 | uint8_t time_offset_length; | |
| 168 | } CODECHAL_ENCODE_AVC_VUI_PARAMS, *PCODECHAL_ENCODE_AVC_VUI_PARAMS; | |
| 169 | ||
| 170 | typedef enum | |
| 171 | { | |
| 172 | CODECHAL_ENCODE_AVC_NAL_UT_RESERVED = 0x00, // Unspecified | |
| 173 | CODECHAL_ENCODE_AVC_NAL_UT_SLICE = 0x01, // Coded Slice - slice_layer_no_partioning_rbsp | |
| 174 | CODECHAL_ENCODE_AVC_NAL_UT_DPA = 0x02, // Coded Data partition A - dpa_layer_rbsp | |
| 175 | CODECHAL_ENCODE_AVC_NAL_UT_DPB = 0x03, // Coded Data partition B - dpa_layer_rbsp | |
| 176 | CODECHAL_ENCODE_AVC_NAL_UT_DPC = 0x04, // Coded Data partition C - dpa_layer_rbsp | |
| 177 | CODECHAL_ENCODE_AVC_NAL_UT_IDR_SLICE = 0x05, // Coded Slice of a IDR Picture - slice_layer_no_partioning_rbsp | |
| 178 | CODECHAL_ENCODE_AVC_NAL_UT_SEI = 0x06, // Supplemental Enhancement Information - sei_rbsp | |
| 179 | CODECHAL_ENCODE_AVC_NAL_UT_SPS = 0x07, // Sequence Parameter Set - seq_parameter_set_rbsp | |
| 180 | CODECHAL_ENCODE_AVC_NAL_UT_PPS = 0x08, // Picture Parameter Set - pic_parameter_set_rbsp | |
| 181 | CODECHAL_ENCODE_AVC_NAL_UT_AUD = 0x09, // Access Unit Delimiter - access_unit_delimiter_rbsp | |
| 182 | CODECHAL_ENCODE_AVC_NAL_UT_EOSEQ = 0x0a, // End of sequence - end_of_seq_rbsp | |
| 183 | CODECHAL_ENCODE_AVC_NAL_UT_EOSTREAM = 0x0b, // End of stream - end_of_stream_rbsp | |
| 184 | CODECHAL_ENCODE_AVC_NAL_UT_FILL = 0x0c, // Filler data - filler_data_rbsp | |
| 185 | CODECHAL_ENCODE_AVC_NAL_UT_SEQEXT = 0x0d, // Sequence parameter set extension - seq_parameter_set_extension_rbsp | |
| 186 | CODECHAL_ENCODE_AVC_NAL_UT_PREFIX = 0x0e, // Prefix NAL unit in scalable extension - prefix_nal_unit_rbsp | |
| 187 | CODECHAL_ENCODE_AVC_NAL_UT_SUBSEQ = 0x0f, // Subset sequence parameter set - subset_seq_parameter_set_rbsp | |
| 188 | /* 0x10..0x12 - Reserved */ | |
| 189 | CODECHAL_ENCODE_AVC_NAL_UT_LAYERNOPART = 0x13, // Coded slice of an auxiliary coded picture without paritioning - slice_layer_without_partitioning_rbsp | |
| 190 | CODECHAL_ENCODE_AVC_NAL_UT_LAYERSCALEEXT = 0x14, // Coded slice in scalable extension - slice_layer_in_scalable_extension_rbsp | |
| 191 | /* 0x15..0x17 - Reserved */ | |
| 192 | /* 0x18..0x1f - Unspcified */ | |
| 193 | ||
| 194 | //this should be the last element of this enum | |
| 195 | //chagne this value if NAL unit type increased | |
| 196 | CODECHAL_ENCODE_AVC_MAX_NAL_TYPE = 0x1f, | |
| 197 | } CODECHAL_ENCODE_AVC_NAL_UNIT_TYPE; | |
| 198 | ||
| 199 | enum | |
| 200 | { | |
| 201 | SLICE_P = 0, | |
| 202 | SLICE_B = 1, | |
| 203 | SLICE_I = 2, | |
| 204 | SLICE_SP = 3, | |
| 205 | SLICE_SI = 4 | |
| 206 | }; | |
| 207 | typedef enum | |
| 208 | { | |
| 209 | CODECHAL_ENCODE_AVC_SINGLE_PASS = 0, | |
| 210 | CODECHAL_ENCODE_AVC_ICHAT = 1, | |
| 211 | CODECHAL_ENCODE_AVC_CAPTURE = 4, | |
| 212 | CODECHAL_ENCODE_AVC_APM = 20 | |
| 213 | } CODECHAL_ENCODE_AVC_ENCODER_USAGE; | |
| 214 | ||
| 215 | const uint8_t Slice_Type[10] = { SLICE_P, SLICE_B, SLICE_I, SLICE_SP, SLICE_SI, SLICE_P, SLICE_B, SLICE_I, SLICE_SP, SLICE_SI }; | |
| 216 | ||
| 217 | typedef struct _CODEC_ROI_MAP | |
| 218 | { | |
| 219 | char PriorityLevelOrDQp; // [-3..3] or [-51..51] | |
| 220 | uint8_t NumRect; | |
| 221 | CODEC_ROI Rect[16]; // disconnected areas which have same PriorityLevelOrDQp | |
| 222 | } CODEC_ROI_MAP, *PCODEC_ROI_MAP; | |
| 223 | ||
| 224 | typedef struct _CODEC_ENCODE_MB_CONTROL | |
| 225 | { | |
| 226 | union | |
| 227 | { | |
| 228 | struct | |
| 229 | { | |
| 230 | uint32_t bForceIntra : 1; | |
| 231 | uint32_t Reserved : 31; | |
| 232 | }; | |
| 233 | uint32_t value; | |
| 234 | } MBParams; | |
| 235 | } CODEC_ENCODE_MB_CONTROL, *PCODEC_ENCODE_MB_CONTROL; | |
| 236 | ||
| 237 | typedef struct _CODEC_PIC_REORDER | |
| 238 | { | |
| 239 | uint32_t PicNum; | |
| 240 | uint32_t POC; | |
| 241 | uint8_t ReorderPicNumIDC; | |
| 242 | uint8_t DiffPicNumMinus1; | |
| 243 | CODEC_PICTURE Picture; | |
| 244 | } CODEC_PIC_REORDER, *PCODEC_PIC_REORDER; | |
| 245 | ||
| 246 | /*! \brief Provides the sequence-level parameters of a compressed picture for AVC encoding. | |
| 247 | * | |
| 248 | * The framework is expected to only send a sequence parameter compressed buffer for the first picture(first Execute() call) in a sequence, associated with a RAP(IDR, CRA, BLA) picture. | |
| 249 | */ | |
| 250 | typedef struct _CODEC_AVC_ENCODE_SEQUENCE_PARAMS | |
| 251 | { | |
| 252 | uint16_t FrameWidth; //!< Width of the frame in pixels. | |
| 253 | uint16_t FrameHeight; //!< Height of the frame in pixels. | |
| 254 | uint8_t Profile; //!< Same as AVC syntax parameter profile_idc. | |
| 255 | uint8_t Level; //!< Same as AVC syntax parameter level_idc. | |
| 256 | ||
| 257 | uint16_t GopPicSize; //!< Distance between IRAP pictures. | |
| 258 | /*! \brief Distance between anchor frames (I or P). | |
| 259 | * | |
| 260 | * Here, P may also means low delay B (GPB) frames. | |
| 261 | * Programming Note: GopPicSize > GopRefDist should be ensured by application. It is required by BRC. | |
| 262 | */ | |
| 263 | uint16_t GopRefDist; | |
| 264 | uint16_t GopOptFlag : 2; | |
| 265 | uint16_t : 6; | |
| 266 | ||
| 267 | uint8_t TargetUsage; | |
| 268 | /*! \brief Specifies rate control method. | |
| 269 | * | |
| 270 | * \n 0: CQP, if set, internal BRC, multi-pass and panic mode will be disabled | |
| 271 | * \n 1: CBR | |
| 272 | * \n 2: VBR | |
| 273 | * \n 3: CQP, see above | |
| 274 | * \n 4: AVBR, if set, HRD compliance is not guaranteed. Buffering period SEI and picture timing SEI messages are not necessary for AVBR. | |
| 275 | * \n 5: Reserved | |
| 276 | * \n 6: Reserved | |
| 277 | * \n 7: Reserved | |
| 278 | * \n 8: LA, look ahead | |
| 279 | * \n 9: ICQ (Intelligent Constant Quality) | |
| 280 | * \n 10: VCM, defined for video converencing | |
| 281 | * \n 11: LA_ICQ | |
| 282 | * \n 12: LA_EXT, defined for server transcoding usage, 1 input video sequence generates several sequences with different bitrate | |
| 283 | * \n 13: LA_HRD, defined for server and client usage, lookahead with HRD and strict handling of maximum bitrate window | |
| 284 | * \n 14: QVBR (Quality Regulated VBR) | |
| 285 | * \n Programming note: Define the minimum value as indicated above for AVBR accuracy & convergence, clamp any value that is less than the minimum value to the minimum value. Define the maximum value for AVBR accuracy as 100 (10%) and for AVBR convergence as 500, clamp any value that is greater than the maximum value to the maximum value. The maximum & minimum value may be adjusted when necessary. If bResetBRC is set to 1 for a non-I picture, driver shall not insert SPS into bitstream. Driver needs to calculate the maximum allowed frame size per profile/level for all RateControlMethod except CQP, and use the calculated value to program kernel for non AVBR modes; for AVBR mode, driver needs to clamp the upper bound of UserMaxFrameSize to the calculated value and use the clamped UserMaxFrameSize to program kernel. If IWD_VBR is set, driver programs it the same as VBR except not to enable panic mode. | |
| 286 | */ | |
| 287 | uint8_t RateControlMethod; | |
| 288 | uint32_t TargetBitRate; //!< Target bit rate Kbit per second | |
| 289 | uint32_t MaxBitRate; //!< Maximum bit rate Kbit per second | |
| 290 | /*! \brief Minimun bit rate Kbit per second. | |
| 291 | * | |
| 292 | * This is used in VBR control. For CBR control, this field is ignored. | |
| 293 | */ | |
| 294 | uint32_t MinBitRate; | |
| 295 | uint16_t FramesPer100Sec; //!< Total frames per 100 second (frame rate fps * 100). | |
| 296 | uint32_t InitVBVBufferFullnessInBit; //!< Initial VBV buffer fullness in bits. | |
| 297 | /*! \brief VBV buffer size in bit unit. | |
| 298 | * | |
| 299 | * The AVC spec defines a max coded picture buffer size for each level. | |
| 300 | */ | |
| 301 | uint32_t VBVBufferSizeInBit; | |
| 302 | /*! \brief Specifies number of reference frames. | |
| 303 | * | |
| 304 | * Should not be greater than driver reported max number of references. | |
| 305 | */ | |
| 306 | uint8_t NumRefFrames; | |
| 307 | ||
| 308 | /*! \brief Same as AVC syntax element. | |
| 309 | * | |
| 310 | * Should not be greater than max SPS set reported by driver. | |
| 311 | */ | |
| 312 | uint8_t seq_parameter_set_id; | |
| 313 | uint8_t chroma_format_idc; //!< Same as AVC syntax element. | |
| 314 | uint8_t bit_depth_luma_minus8; //!< Same as AVC syntax element. | |
| 315 | uint8_t bit_depth_chroma_minus8; //!< Same as AVC syntax element. | |
| 316 | uint8_t log2_max_frame_num_minus4; //!< Same as AVC syntax element. | |
| 317 | uint8_t pic_order_cnt_type; //!< Same as AVC syntax element. | |
| 318 | uint8_t log2_max_pic_order_cnt_lsb_minus4; //!< Same as AVC syntax element. | |
| 319 | uint8_t num_ref_frames_in_pic_order_cnt_cycle; //!< Same as AVC syntax element. | |
| 320 | int32_t offset_for_non_ref_pic; //!< Same as AVC syntax element. | |
| 321 | int32_t offset_for_top_to_bottom_field; //!< Same as AVC syntax element. | |
| 322 | int32_t offset_for_ref_frame[256]; //!< Same as AVC syntax element. | |
| 323 | uint16_t frame_crop_left_offset; //!< Same as AVC syntax element. | |
| 324 | uint16_t frame_crop_right_offset; //!< Same as AVC syntax element. | |
| 325 | uint16_t frame_crop_top_offset; //!< Same as AVC syntax element. | |
| 326 | uint16_t frame_crop_bottom_offset; //!< Same as AVC syntax element. | |
| 327 | ||
| 328 | uint16_t seq_scaling_list_present_flag[12]; //!< Same as AVC syntax element. | |
| 329 | uint16_t seq_scaling_matrix_present_flag : 1; //!< Same as AVC syntax element. | |
| 330 | uint16_t delta_pic_order_always_zero_flag : 1; //!< Same as AVC syntax element. | |
| 331 | uint16_t frame_mbs_only_flag : 1; //!< Same as AVC syntax element. | |
| 332 | uint16_t direct_8x8_inference_flag : 1; //!< Same as AVC syntax element. | |
| 333 | uint16_t vui_parameters_present_flag : 1; //!< Same as AVC syntax element. | |
| 334 | uint16_t frame_cropping_flag : 1; //!< Same as AVC syntax element. | |
| 335 | /*! \brief Specifies that encoded slices returned fit within the slice size specified in the picture parameter set for AVC. | |
| 336 | * | |
| 337 | * When enabled, this overrides the slice structures specified by the application using slice level parameters. | |
| 338 | */ | |
| 339 | uint16_t EnableSliceLevelRateCtrl : 1; | |
| 340 | uint16_t : 8; | |
| 341 | union | |
| 342 | { | |
| 343 | struct | |
| 344 | { | |
| 345 | uint32_t bInitBRC : 1; | |
| 346 | /*! \brief Indicate if a BRC reset is desired to set a new bit rate or frame rate. | |
| 347 | * | |
| 348 | * This setting is only valid if RateControlMethod is AVBR, VBR, CBR, VCM, ICQ, CQL or QVBR and the current picture is an I picture. If the frame resolution is changed, it should be set with IDR picture. It should not be set when RateControlMethod is CBR or CQP. The following table indicates which BRC parameters can be changed via a BRC reset. | |
| 349 | * | |
| 350 | * \n BRC Parameters Changes allowed via reset | |
| 351 | * \n Profile & Level Yes | |
| 352 | * \n UserMaxFrameSize Yes | |
| 353 | * \n InitVBVBufferFullnessInBit No | |
| 354 | * \n TargetBitRate Yes | |
| 355 | * \n VBVBufferSizeInBit No | |
| 356 | * \n MaxBitRate Yes | |
| 357 | * \n FramesPer100Sec * No | |
| 358 | * \n RateControlMethod No | |
| 359 | * \n GopPicSize No | |
| 360 | * \n GopRefDist No | |
| 361 | * \n GopOptFlag Yes | |
| 362 | * \n FrameWidth No | |
| 363 | * \n FrameHeight No | |
| 364 | * \n Note: when resolution (FrameWidth and/or FrameHeight) changes, framework should re-start a new bit stream and not using BRC reset. | |
| 365 | */ | |
| 366 | uint32_t bResetBRC : 1; | |
| 367 | /*! \brief Indicates that current SPS is just a BRC parameter update, not a SPS change to be inserted into the bitstream. | |
| 368 | * | |
| 369 | * When set to 1, current SPS will not be packed and inserted into bitstream by the driver. | |
| 370 | */ | |
| 371 | uint32_t bNoAcceleratorSPSInsertion : 1; | |
| 372 | /*! \brief Indicates the global search options. | |
| 373 | * | |
| 374 | * It is only valid if EnhancedEncInput is reported during capability checking: | |
| 375 | * \n - 0: Default - option internally selected based on target usage | |
| 376 | * \n - 1: Long - SHME enabled | |
| 377 | * \n - 2: Medium - HME only enabled, SHME disabled | |
| 378 | * \n - 3: Short - SHME/HME disabled | |
| 379 | */ | |
| 380 | uint32_t GlobalSearch : 2; | |
| 381 | /*! \brief Indicates the local search options. | |
| 382 | * | |
| 383 | * It is only valid if EnhancedEncInput is reported during capability checking: | |
| 384 | * \n - 0: Default - option internally selected based on target usage | |
| 385 | * \n - 1: Tiny – MaxLenSP = 4, Reference Window = 24x24 SP = Spiral | |
| 386 | * \n - 2: Small – MaxLenSP = 9, Reference Window = 28x28 SP = Spiral | |
| 387 | * \n - 3: Square – MaxLenSP = 16, Reference Window = 32x32 SP = Spiral | |
| 388 | * \n - 4: Diamond – MaxLenSP = 16, Reference Window = 48x40 SP = Diamond | |
| 389 | * \n - 5: Large Diamond – MaxLenSP = 30, Reference Window = 48x40 SP = Diamond | |
| 390 | * \n - 6: Exhaustive – MaxLenSP = 57, Reference Window = 48x40 SP = Spiral | |
| 391 | * \n - 7: Heavy Horizontal – MaxLenSP = 57, Reference Window = 64x32 SP = Spiral | |
| 392 | * \n - 8: Heavy Vertical – MaxLenSP = 57, Reference Window = 32x64 SP = Spiral | |
| 393 | */ | |
| 394 | uint32_t LocalSearch : 4; | |
| 395 | /*! \brief Indicates early skip control. | |
| 396 | * | |
| 397 | * It is only valid if EnhancedEncInput is reported during capability checking: | |
| 398 | * \n - 0: Default, decided internally | |
| 399 | * \n - 1: EarlySkip enabled | |
| 400 | * \n - 2: EarlySkip disabled | |
| 401 | */ | |
| 402 | uint32_t EarlySkip : 2; | |
| 403 | uint32_t Reserved0 : 1; | |
| 404 | /*! \brief Indicates that MB BRC is enabled. | |
| 405 | * | |
| 406 | * It is only valid if MBBRCSupport is reported during capability checking: | |
| 407 | * \n - 0: Default, decided internally based on target usage. | |
| 408 | * \n - 1: MB BRC enabled. | |
| 409 | * \n - 2: MB BRC disabled. | |
| 410 | * \n - Other values are Reserved. | |
| 411 | * \n Currently MB BRC can be applied to all bit rate control methods except CQP. | |
| 412 | */ | |
| 413 | uint32_t MBBRC : 4; | |
| 414 | /*! \brief Indicates trellis control. | |
| 415 | * | |
| 416 | * The Trellis_I, Trellis_P and Trellis_B settings may be combined using bitwise OR like "Trellis_I | Trellis_P" to enable Trellis for I & P. If Trellis_Disabled is set with any combination, Trellis will be disabled. | |
| 417 | * \n - 0: Trellis_Default – Trellis decided internally. | |
| 418 | * \n - 1: Trellis_Disabled – Trellis disabled for all frames/fields. | |
| 419 | * \n - 2: Trellis_I – Trellis enabled for I frames/fields. | |
| 420 | * \n - 4: Trellis_P – Trellis enabled for P frames/fields. | |
| 421 | * \n - 8: Trellis_B – Trellis enabled for B frames/fields. | |
| 422 | */ | |
| 423 | uint32_t Trellis : 4; | |
| 424 | /*! \brief Indicates current sequence is encoded for Temporal Scalability. | |
| 425 | * The driver may or may not use this flag. For example, for VME+PAK AVC encoder MSDK handles all header insertion to indicate a temporal id in the SVC ext slice header and this flag is not used. However, for VDEnc AVC encoder in certain cases BRC is required to know if the current frames are being encoded for temporal scalability and therefore will have extra SVC ext added in the slice header. | |
| 426 | * \n - 0: Default, current sequence is not encoded for Temporal Scalability. | |
| 427 | * \n - 1: current sequence is encoded is encoded for Temporal Scalability. | |
| 428 | */ | |
| 429 | uint32_t bTemporalScalability : 1; | |
| 430 | /*! \brief Indicates ROI[] value is in delta QP or priority. | |
| 431 | * | |
| 432 | * It is valid only when parameter NumROI is greater than 0 and either ROIDeltaQPSupport or ROIBRCPriorityLevelSupport equals to 1. | |
| 433 | * \n - 0: Default, ROI[] value is in priority. | |
| 434 | * \n - 1: ROI[] value is in delta QP. | |
| 435 | * \n Currently only ROIValueInDeltaQP equal 1 is validated for CQP | |
| 436 | */ | |
| 437 | uint32_t ROIValueInDeltaQP : 1; | |
| 438 | /*! \brief Indicates larger P/B frame size than UserMaxPBFrameSize may be used. | |
| 439 | * | |
| 440 | * if enabled, BRC may decide a larger P or B frame size than what UserMaxPBFrameSize dictates when the scene change is detected. | |
| 441 | * \n - 0: Default, normal BRC. | |
| 442 | * \n - 1: BRC may decide larger P/B frame size. | |
| 443 | */ | |
| 444 | uint32_t bAutoMaxPBFrameSizeForSceneChange : 1; | |
| 445 | /* Control the force panic mode through DDI other than user feature key */ | |
| 446 | uint32_t bForcePanicModeControl : 1; | |
| 447 | uint32_t bPanicModeDisable : 1; | |
| 448 | ||
| 449 | /*! \brief Enables streaming buffer in LLC | |
| 450 | * | |
| 451 | * \n - 0 : streaming buffer by LLC is disabled. | |
| 452 | * \n - 1 : streaming buffer by LLC is enabled. | |
| 453 | */ | |
| 454 | uint32_t EnableStreamingBufferLLC : 1; | |
| 455 | /*! \brief Enables streaming buffer in DDR | |
| 456 | * | |
| 457 | * \n - 0 : streaming buffer by DDR is disabled. | |
| 458 | * \n - 1 : streaming buffer by DDR is enabled. | |
| 459 | */ | |
| 460 | uint32_t EnableStreamingBufferDDR : 1; | |
| 461 | /*! \brief Indicates whether or not the encoding is in hierarchical GOP structure, for both RA B and LD B frame types | |
| 462 | * | |
| 463 | * \n - 0 : BRC would treat it as flat structure. | |
| 464 | * \n - 1 : hierarchical structure. | |
| 465 | * \n In another word, this flag is equivalent to Qp Modulation enabling flag. If HierarchicalFlag == 1, app would enable Qp modulation for either random access or low delay hierarchical structure. | |
| 466 | */ | |
| 467 | uint32_t HierarchicalFlag : 1; | |
| 468 | /*! \brief Indicates whether or not the encoding is in low delay mode. | |
| 469 | * | |
| 470 | * \n - 0 : the non-base temporal layers should be coded as random access B frames. | |
| 471 | * \n - 1 : no random access B will be coded. And the coding type could be only I or P. | |
| 472 | * \n Note: this flag only indicates the frame coding type, and is not related to BRC low delay mode. | |
| 473 | */ | |
| 474 | uint32_t LowDelayMode : 1; | |
| 475 | /*! \brief Indicates if current encodin gis lookahead pass. | |
| 476 | * | |
| 477 | * \n - 0 : the current encoding is in the actual encoding pass, and one of the BRC modes (CBR, VBR, etc.) should be selected. | |
| 478 | * \n - 1 : the current encoding is in the lookahead pass. | |
| 479 | * \n Valid only when LookAheadAnalysisSupport in CAP is on and LookAheadDepth > 0. | |
| 480 | */ | |
| 481 | uint32_t bLookAheadPhase : 1; | |
| 482 | uint32_t Reserved1 : 2; | |
| 483 | }; | |
| 484 | uint32_t sFlags; | |
| 485 | }; | |
| 486 | /*! \brief Framework defined maximum frame size in bytes for I frames. | |
| 487 | * | |
| 488 | * Applicable for all RateControlMethod values except CQP; guarantees that the compressed frame size will be less than this value. If UserMaxPBFrameSize equals 0, UserMaxIFrameSize will be used for all frame types. Maximum allowed frame size per profile/level will be calculated in driver and be used when UserMaxIFrameSize and UserMaxPBFrameSize are both set to 0. | |
| 489 | */ | |
| 490 | uint32_t UserMaxFrameSize; | |
| 491 | /*! \brief Framework defined maximum frame size in bytes for P & B frames. | |
| 492 | * | |
| 493 | * Applicable for all RateControlMethod values except CQP; guarantees that the compressed frame size will be less than this value. If UserMaxPBFrameSize equals 0, UserMaxIFrameSize will be used for all frame types. Maximum allowed frame size per profile/level will be calculated in driver and be used when UserMaxIFrameSize and UserMaxPBFrameSize are both set to 0. | |
| 494 | */ | |
| 495 | uint32_t UserMaxPBFrameSize; | |
| 496 | /*! \brief Indicates the measure of quality for ICQ and QVBR | |
| 497 | * | |
| 498 | * The range is from 1 – 51, with 1 being the best quality. | |
| 499 | */ | |
| 500 | uint16_t ICQQualityFactor; | |
| 501 | /*! \brief Indicates the bitrate accuracy for AVBR | |
| 502 | * | |
| 503 | * The range is [1, 100], 1 means one percent, and so on. | |
| 504 | */ | |
| 505 | uint32_t AVBRAccuracy; | |
| 506 | /*! \brief Indicates the bitrate convergence period for AVBR | |
| 507 | * | |
| 508 | * The unit is frame. | |
| 509 | */ | |
| 510 | uint32_t AVBRConvergence; | |
| 511 | ||
| 512 | /*! \brief Indicates the uncompressed input color space | |
| 513 | * | |
| 514 | * Valid only when input is ARGB format. | |
| 515 | */ | |
| 516 | ENCODE_INPUT_COLORSPACE InputColorSpace; | |
| 517 | /*! \brief Provides a hint to encoder about the scenario for the encoding session. | |
| 518 | * | |
| 519 | * BRC algorithm may tune differently based on this info. | |
| 520 | */ | |
| 521 | ENCODE_SCENARIO ScenarioInfo; | |
| 522 | ENCODE_CONTENT ContentInfo; //!< Provides a hint to encoder about the content for the encoding session. | |
| 523 | ||
| 524 | /*! \brief Indicates the tolerance the application has to variations in the frame size. | |
| 525 | * | |
| 526 | * It affects the BRC algorithm used, but may or may not have an effect based on the combination of other BRC parameters. Only valid when the driver reports support for FrameSizeToleranceSupport. | |
| 527 | */ | |
| 528 | ENCODE_FRAMESIZE_TOLERANCE FrameSizeTolerance; | |
| 529 | ||
| 530 | /*! \brief Indicates BRC Sliding window size in terms of number of frames. | |
| 531 | * | |
| 532 | * Defined for CBR and VBR. For other BRC modes or CQP, values are ignored. | |
| 533 | */ | |
| 534 | uint16_t SlidingWindowSize; | |
| 535 | ||
| 536 | /*! \brief Indicates maximun bit rate Kbit per second within the sliding window during. | |
| 537 | * | |
| 538 | * Defined for CBR and VBR. For other BRC modes or CQP, values are ignored. | |
| 539 | */ | |
| 540 | uint32_t MaxBitRatePerSlidingWindow; | |
| 541 | ||
| 542 | /*! \brief Indicates minimun bit rate Kbit per second within the sliding window during. | |
| 543 | * | |
| 544 | * Defined for CBR and VBR. For other BRC modes or CQP, values are ignored. | |
| 545 | */ | |
| 546 | uint32_t MinBitRatePerSlidingWindow; | |
| 547 | ||
| 548 | /*! \brief Indicates number of frames to lookahead. | |
| 549 | * | |
| 550 | * Range is [0~127]. Default is 0 which means lookahead disabled. Valid only when LookaheadBRCSupport is 1. When not 0, application should send LOOKAHEADDATA buffer to driver. | |
| 551 | */ | |
| 552 | uint8_t LookaheadDepth; | |
| 553 | ||
| 554 | uint8_t constraint_set0_flag : 1; //!< Same as AVC syntax element. | |
| 555 | uint8_t constraint_set1_flag : 1; //!< Same as AVC syntax element. | |
| 556 | uint8_t constraint_set2_flag : 1; //!< Same as AVC syntax element. | |
| 557 | uint8_t constraint_set3_flag : 1; //!< Same as AVC syntax element. | |
| 558 | uint8_t : 4; | |
| 559 | uint8_t separate_colour_plane_flag; //!< Same as AVC syntax element. | |
| 560 | bool qpprime_y_zero_transform_bypass_flag; //!< Same as AVC syntax element. | |
| 561 | bool gaps_in_frame_num_value_allowed_flag; //!< Same as AVC syntax element. | |
| 562 | uint16_t pic_width_in_mbs_minus1; //!< Same as AVC syntax element. | |
| 563 | uint16_t pic_height_in_map_units_minus1; //!< Same as AVC syntax element. | |
| 564 | bool mb_adaptive_frame_field_flag; //!< Same as AVC syntax element. | |
| 565 | } CODEC_AVC_ENCODE_SEQUENCE_PARAMS, *PCODEC_AVC_ENCODE_SEQUENCE_PARAMS; | |
| 566 | ||
| 567 | typedef struct _CODEC_AVC_ENCODE_USER_FLAGS | |
| 568 | { | |
| 569 | union | |
| 570 | { | |
| 571 | struct | |
| 572 | { | |
| 573 | /*! \brief Indicates that raw pictures should be used as references instead of recon pictures. | |
| 574 | * | |
| 575 | * Setting to 1 may improve performance at the cost of image quality. The accelerator may or may not support toggling this value on a per frame basis. | |
| 576 | */ | |
| 577 | uint32_t bUseRawPicForRef : 1; | |
| 578 | /*! \brief Indicates whether or not the driver will pack non-slice headers. | |
| 579 | * | |
| 580 | * Applies to ENC + PAK mode only. This flag is only valid only when AcceleratorHeaderPacking = 1, and driver does the header packing. | |
| 581 | * \n - 0: Accelerator will pack AU delimiter, SPS (including VUI if present), PPS, SEI messages if present, end of sequence if indicated, and end of stream if indicated, along with coded slice to form a complete bitstream. | |
| 582 | * \n - 1: Accelerator will just pack coded slice (slice header + data), like in PAK only mode, and the application will pack the rest of the headers. | |
| 583 | */ | |
| 584 | uint32_t bDisableAcceleratorHeaderPacking : 1; | |
| 585 | uint32_t : 5; | |
| 586 | uint32_t bDisableSubMBPartition : 1; //!< Indicates that sub MB partitioning should be disabled. | |
| 587 | /*! \brief Inidicates whether or not emulation byte are inserted. | |
| 588 | * | |
| 589 | * If 1, accelerator will perform start code prefix (0x 00 00 01/02/03/00) search and emulation byte (0x 03) insertion on packed header data. This doesn’t apply to packed slice header data. Packed slice header data must not have emulation byte inserted, accelerator will always perform start code prefix search and emulation byte (0x 03) insertion on packed slice header data. | |
| 590 | * Note: If cabac_zero_word insertion compliance is required, this value should be set to 0. This means the application must perform emulation prevention byte insertion in the frame header. This is due to the restriction in MFX_PAK_INSERT_OBJECT HeaderLengthExcludeFrmSize cannot allow EmulationFlag to be true. | |
| 591 | */ | |
| 592 | uint32_t bEmulationByteInsertion : 1; | |
| 593 | /*! \brief Specifies the type of intra refresh used. | |
| 594 | * | |
| 595 | * Effective only when RollingINtraRefresh capability in use. Applies to P pictures only (not valid with IBP). When used field encoding, B frames, and multiple references are not allowed. | |
| 596 | * \n - 0 : disabled | |
| 597 | * \n - 1 : enabled in colum | |
| 598 | * \n - 2 : enabled in row | |
| 599 | * \n - 3 : enabled in region | |
| 600 | */ | |
| 601 | uint32_t bEnableRollingIntraRefresh : 2; | |
| 602 | ||
| 603 | /*! \brief Specifies if Slice Level Reporitng may be requested for this frame | |
| 604 | * | |
| 605 | * If this flag is set, then slice level parameter reporting will be set up for this frame. Only valid if SliceLevelReportSupport is reported in ENCODE_CAPS, else this flag is ignored. | |
| 606 | * | |
| 607 | */ | |
| 608 | uint32_t bEnableSliceLevelReport : 1; | |
| 609 | ||
| 610 | /*! \brief Specifies if integer mode searching is performed | |
| 611 | * | |
| 612 | * when set to 1, integer mode searching is performed | |
| 613 | * | |
| 614 | */ | |
| 615 | uint32_t bDisableSubpixel : 1; | |
| 616 | ||
| 617 | /*! \brief Specifies if the overlapped operation of intra refresh is disabled | |
| 618 | * | |
| 619 | * It is valid only when bEnableRollingIntraRefresh is on. | |
| 620 | * \n - 0 : default, overlapped Intra refresh is applied | |
| 621 | * \n - 1 : intra refresh without overlap operation | |
| 622 | * | |
| 623 | */ | |
| 624 | uint32_t bDisableRollingIntraRefreshOverlap : 1; | |
| 625 | ||
| 626 | /*! \brief Specifies whether extra partition decision refinement is done after the initial partition decision candidate is determined. | |
| 627 | * | |
| 628 | * It has performance tradeoff for better quality. | |
| 629 | * \n - 0 : DEFAULT - Follow driver default settings. | |
| 630 | * \n - 1 : FORCE_ENABLE - Enable this feature totally for all cases. | |
| 631 | * \n - 2 : FORCE_DISABLE - Disable this feature totally for all cases. | |
| 632 | */ | |
| 633 | uint32_t ForceRepartitionCheck : 2; | |
| 634 | uint32_t bReserved : 16; | |
| 635 | }; | |
| 636 | uint32_t Value; | |
| 637 | }; | |
| 638 | } CODEC_AVC_ENCODE_USER_FLAGS, *PCODEC_AVC_ENCODE_USER_FLAGS; | |
| 639 | ||
| 640 | typedef struct _CODEC_AVC_ENCODE_FORCE_SKIP_PARAMS | |
| 641 | { | |
| 642 | uint32_t Enable; | |
| 643 | uint32_t Xpos; | |
| 644 | uint32_t Ypos; | |
| 645 | uint32_t Width; | |
| 646 | uint32_t Height; | |
| 647 | ||
| 648 | } CODEC_AVC_ENCODE_FORCE_SKIP_PARAMS, *PCODEC_AVC_ENCODE_FORCE_SKIP_PARAMS; | |
| 649 | ||
| 650 | /*! \brief Provides the picture-level parameters of a compressed picture for AVC encoding. | |
| 651 | */ | |
| 652 | typedef struct _CODEC_AVC_ENCODE_PIC_PARAMS | |
| 653 | { | |
| 654 | /*! \brief Specifies the uncompressed source surface of the frame for the current picture to be encode. | |
| 655 | * | |
| 656 | * The PicFlags regarding reference usage are expected to be valid at this time. | |
| 657 | */ | |
| 658 | CODEC_PICTURE CurrOriginalPic; | |
| 659 | /*! \brief Specifies the uncompressed surface of the reconstructed frame for the current encoded picture. | |
| 660 | * | |
| 661 | * The PicFlags regarding reference usage are expected to be valid at this time. | |
| 662 | * The recon surface may be of different format and different bit depth from that of source. | |
| 663 | * The framework needs to specify it through chroma_format_idc and bit_depth_luma_minus8 and | |
| 664 | * bit_depth_chroma_minus8 in SPS data structure. | |
| 665 | */ | |
| 666 | CODEC_PICTURE CurrReconstructedPic; | |
| 667 | /*! \brief Specifies picture coding type. | |
| 668 | * | |
| 669 | * \n 1: I picture | |
| 670 | * \n 2: P picture | |
| 671 | * \n 3: B picture | |
| 672 | */ | |
| 673 | uint8_t CodingType; | |
| 674 | /*! \brief Specifies that field mode coding is in use. | |
| 675 | * | |
| 676 | * Top or bottom field indicated by CurrOriginalPic.PicFlags. | |
| 677 | */ | |
| 678 | uint8_t FieldCodingFlag : 1; | |
| 679 | /*! \brief Specifies that MBAFF coding mode is in use. | |
| 680 | * | |
| 681 | * It shall not be set if NoFieldFrame flag is reported in CodingLimit during capability checking. | |
| 682 | */ | |
| 683 | uint8_t FieldFrameCodingFlag : 1; | |
| 684 | uint8_t : 6; | |
| 685 | /*! \brief Specifies the number of slices per frame or per field in field coding. | |
| 686 | * | |
| 687 | * Note the restriction on slice based on the SliceStructure reported during capability checking. | |
| 688 | */ | |
| 689 | uint32_t NumSlice; | |
| 690 | ||
| 691 | /*! \brief Quantization parameter for Y. | |
| 692 | * | |
| 693 | * Valid range is 0 - 51. If QpY is set to -1, driver will use an internal default value when CQP is not set, otherwise, driver will return error. Please note that, QpY is a frame level QP. QP for each slice is determined by QpY + slice_qp_delta. And QpY + slice_qp_delta should be also in the range of 0 – 51, inclusive. | |
| 694 | */ | |
| 695 | char QpY; | |
| 696 | /*! \brief Each entry of the list specifies the frame index of the reference pictures. | |
| 697 | * | |
| 698 | * The value of FrameIdx specifies the index of RefFrameList structure. And valid value range is [0..14, 0x7F]. Invalid entries are indicated by setting PicFlags to PICTURE_INVALID. | |
| 699 | * RefFrameList[] should include all the reference pictures in DPB, which means either the picture is referred by current picture or future pictures, it should have a valid entry in it. | |
| 700 | */ | |
| 701 | CODEC_PICTURE RefFrameList[CODEC_AVC_MAX_NUM_REF_FRAME]; | |
| 702 | /*! \brief Denotes "used for reference" frames as defined in the AVC specification. | |
| 703 | * | |
| 704 | * The flag is accessed by: | |
| 705 | * \n - FlagTop(i) = (UsedForReferenceFlags >> (2 * i)) & 1 | |
| 706 | * \n - FlagBottom(i) = (UsedForReferenceFlags >> (2 * i + 1)) & 1 | |
| 707 | * \n If FlagTop(i) is 1, the top field or frame numger i is marked as "used for reference"; if FlagBottom(i) is 1 then then bottom field of frame i is marked as "used for reference". If either is 0 then the frame is not marked as "used for reference". | |
| 708 | */ | |
| 709 | uint32_t UsedForReferenceFlags; | |
| 710 | /*! \brief Contains the picture order counts (POC) for the current frame | |
| 711 | * | |
| 712 | * If field_pic_flag is 0: | |
| 713 | * \n - CurrFieldOrderCnt[0] contains the top field order count for the current picture | |
| 714 | * \n - CurrFieldOrderCnt[1] contains the bottom field order count for the current picture | |
| 715 | * \n If field_pic_flag is 1 and CurrPic.PicFlags indicates that this is a top field: | |
| 716 | * \n - CurrFieldOrderCnt[0] contains the top field order count for the current picture | |
| 717 | * \n - CurrFieldOrderCnt[1] | |
| 718 | * \n If field_pic_flag is 1 and CurrPic.PicFlags indicates that this is a bottom field: | |
| 719 | * \n - CurrFieldOrderCnt[0] should be 0 or ignored | |
| 720 | * \n - CurrFieldOrderCnt[1] contains the bottom field order count for the current picture | |
| 721 | */ | |
| 722 | int32_t CurrFieldOrderCnt[2]; | |
| 723 | /*! \brief Contains the POCs for the reference frames in RefFrameList. | |
| 724 | * | |
| 725 | * For each entry FieldOrderCntList[i][j]: | |
| 726 | * \n - i: the picture index | |
| 727 | * \n - j: 0 specifies the top field order count and 1 specifies the bottom field order count | |
| 728 | * \n If a entry i in RefFrameList is not relevant (it is not used for reference) or valid, the entry FieldOrderCount[i][0 and 1] should be 0. | |
| 729 | */ | |
| 730 | int32_t FieldOrderCntList[16][2]; | |
| 731 | uint16_t frame_num; //!< Same as AVC syntax element. | |
| 732 | bool bLastPicInSeq; //!< Indicate whether to insert sequence closing NAL unit. | |
| 733 | bool bLastPicInStream; //!< Indicate whether to insert stream closing NAL unit. | |
| 734 | ||
| 735 | CODEC_AVC_ENCODE_USER_FLAGS UserFlags; | |
| 736 | CODEC_AVC_ENCODE_FORCE_SKIP_PARAMS ForceSkip; | |
| 737 | bool bStreamOutEnbleSinglePassvdenc; | |
| 738 | bool bHMEActiveCtrlFrmApp; | |
| 739 | bool bHMEActive; | |
| 740 | ||
| 741 | /*! \brief Arbitrary number set by the host decoder to use as a tag in the status report feedback data. | |
| 742 | * | |
| 743 | * The value should not equal 0, and should be different in each call to Execute. | |
| 744 | */ | |
| 745 | uint32_t StatusReportFeedbackNumber; | |
| 746 | ||
| 747 | uint8_t bIdrPic; //!< Indicates that the current picture is IDR. | |
| 748 | uint8_t pic_parameter_set_id; //!< Same as AVC syntax element. | |
| 749 | uint8_t seq_parameter_set_id; //!< Same as AVC syntax element. | |
| 750 | uint8_t num_ref_idx_l0_active_minus1; //!< Same as AVC syntax element. | |
| 751 | uint8_t num_ref_idx_l1_active_minus1; //!< Same as AVC syntax element. | |
| 752 | char chroma_qp_index_offset; //!< Same as AVC syntax element. | |
| 753 | char second_chroma_qp_index_offset; //!< Same as AVC syntax element. | |
| 754 | ||
| 755 | uint16_t pic_scaling_list_present_flag[12]; //!< Same as AVC syntax element. | |
| 756 | uint16_t entropy_coding_mode_flag : 1; //!< Same as AVC syntax element. | |
| 757 | uint16_t pic_order_present_flag : 1; //!< Same as AVC syntax element. | |
| 758 | uint16_t weighted_pred_flag : 1; //!< Same as AVC syntax element. | |
| 759 | uint16_t weighted_bipred_idc : 2; //!< Same as AVC syntax element. | |
| 760 | uint16_t constrained_intra_pred_flag : 1; //!< Same as AVC syntax element. | |
| 761 | uint16_t transform_8x8_mode_flag : 1; //!< Same as AVC syntax element. | |
| 762 | uint16_t pic_scaling_matrix_present_flag : 1; //!< Same as AVC syntax element. | |
| 763 | uint16_t RefPicFlag : 1; //!< Indicates that the current picture (raw or recon) may be used as a reference for encoding other pictures. | |
| 764 | /*! \brief Indicates how precise the framework would like BRC to be to reach the ideal requested framesize. | |
| 765 | * | |
| 766 | * The driver will internally make programming decisions based on this parameter, it will be a tradeoff between performance and precision. This flag is ignored if BRC is not enabled (CQP mode). | |
| 767 | * \n - 0: default precision (normal) | |
| 768 | * \n - 1: lowest precision | |
| 769 | * \n - 2: normal precision | |
| 770 | * \n - 3: highest precision | |
| 771 | */ | |
| 772 | uint16_t BRCPrecision : 2; | |
| 773 | /*! \brief Indicates that the allocated source buffer format is a swizzle format from display. | |
| 774 | * | |
| 775 | * Framework still allocates the buffer as a standard FOURCC format. The swizzled format will be reported as supported for the encoder configuration during capability reporting. | |
| 776 | * \n Source/Raw Allocated Buffer Format, DisplayFormatSwizzle, Layout Format in Buffer | |
| 777 | * \n - YUY2, 0, YUY2 | |
| 778 | * \n - YUY2, 1, 2YUY (Y0U0Y1V0) | |
| 779 | * \n - AYUV, 0, AYUV | |
| 780 | * \n - AYUV, 1, YUXV | |
| 781 | */ | |
| 782 | uint16_t bDisplayFormatSwizzle : 1; | |
| 783 | uint16_t : 3; | |
| 784 | ||
| 785 | uint8_t num_slice_groups_minus1; //!< Same as AVC syntax element. | |
| 786 | char pic_init_qp_minus26; //!< Same as AVC syntax element. | |
| 787 | char pic_init_qs_minus26; //!< Same as AVC syntax element. | |
| 788 | bool deblocking_filter_control_present_flag; //!< Same as AVC syntax element. | |
| 789 | bool redundant_pic_cnt_present_flag; //!< Same as AVC syntax element. | |
| 790 | ||
| 791 | // Parameters for RollingI feature | |
| 792 | bool bDisableRollingIntraRefreshOverlap; | |
| 793 | uint8_t EnableRollingIntraRefresh; | |
| 794 | uint8_t IntraRefreshMBNum; | |
| 795 | uint8_t IntraRefreshMBx; | |
| 796 | uint8_t IntraRefreshMBy; | |
| 797 | uint8_t IntraRefreshUnitinMB; | |
| 798 | char IntraRefreshQPDelta; | |
| 799 | uint32_t FirstPFrameIntraInsertionSize; | |
| 800 | ||
| 801 | /*! \brief Indicates the maximum size of each slice in Bytes. | |
| 802 | * | |
| 803 | * This is valid only when EnableSliceLevelRateCtrl is enabled in the sequence level. | |
| 804 | */ | |
| 805 | uint32_t SliceSizeInBytes; | |
| 806 | ||
| 807 | /*! \brief Number of Region Of Interest (ROI). | |
| 808 | * | |
| 809 | * Value range is 0 to 16 inclusively. If no ROI to be set, this value shall be set to 0. | |
| 810 | */ | |
| 811 | uint8_t NumROI; | |
| 812 | uint8_t NumDirtyROI; //!< Number of dirty ROIs [0...4] | |
| 813 | uint8_t NumDeltaQpForNonRectROI; //!< Number of DeltaQP for non-rectangular ROIs [0...16] | |
| 814 | /*! \brief Dictates the value of delta QP for any ROI should be within [MinDeltaQp..MaxDeltaQp] | |
| 815 | * | |
| 816 | * Applies only to BRC case. | |
| 817 | */ | |
| 818 | char MaxDeltaQp; | |
| 819 | /*! \brief Dictates the value of delta QP for any ROI should be within [MinDeltaQp..MaxDeltaQp] | |
| 820 | * | |
| 821 | * Applies only to BRC case. | |
| 822 | */ | |
| 823 | char MinDeltaQp; | |
| 824 | /*! \brief Determine possible DeltaQP values for NonRectROI. For BRC case values should be within [MinDeltaQp..MaxDeltaQp] | |
| 825 | * | |
| 826 | * QP value for the MB is represented by NonRectROIDeltaQpList[QpData - 1], | |
| 827 | * where QpData - UCHAR in ENCODE_MBQPDATA structure. | |
| 828 | * if QpData == 0, the block is in the background, and slice QP (QpY + slice_qp_delta) is applied on this MB. | |
| 829 | */ | |
| 830 | char NonRectROIDeltaQpList[16]; | |
| 831 | /*! \brief Defines ROI settings. | |
| 832 | * | |
| 833 | * Value entries are ROI[0] up to ROI[NumROI – 1], inclusively, if NumROI > 0. And it can be ignored otherwise. | |
| 834 | */ | |
| 835 | CODEC_ROI ROI[16]; | |
| 836 | /*! \brief Distinct delta QP values assigned to the ROI | |
| 837 | * | |
| 838 | * Value entries are distinct and within [MinDeltaQp..MaxDeltaQp]. | |
| 839 | */ | |
| 840 | int8_t ROIDistinctDeltaQp[16]; | |
| 841 | /*! \brief Number of distinct delta QP values assigned to the ROI | |
| 842 | */ | |
| 843 | int8_t NumROIDistinctDeltaQp; | |
| 844 | /*! \brief indicate native ROI / force QP ROI to be used. | |
| 845 | */ | |
| 846 | bool bNativeROI; | |
| 847 | /*! \brief Defines dirty ROI settings. | |
| 848 | * | |
| 849 | * Value entries are DirtyROI[0] up DirtyROI ROI[NumROI – 1], inclusively, if NumDirtyROI > 0. And it can be ignored otherwise. | |
| 850 | */ | |
| 851 | CODEC_ROI DirtyROI[CODEC_AVC_NUM_MAX_DIRTY_RECT]; | |
| 852 | ||
| 853 | CODEC_ROI_MAP ROIMapArray[16]; | |
| 854 | ||
| 855 | /*! \brief Specifies skip frames. | |
| 856 | * | |
| 857 | * 0: Encode as normal, no skip. | |
| 858 | * 1: One or more frames were skipped prior to the current frame, encode the current frame as normal. The driver will pass the NumSkipFrames and SizeSkipFrames to BRC for adjustment. | |
| 859 | */ | |
| 860 | uint8_t SkipFrameFlag; | |
| 861 | /*! \brief The number of frames skipped prior to the current frame. | |
| 862 | * | |
| 863 | * Valid when SkipFlag = 1. | |
| 864 | */ | |
| 865 | uint8_t NumSkipFrames; | |
| 866 | /*! \brief Differs in meaning based on value of SkipFrameFlag | |
| 867 | * | |
| 868 | * SkipFrameFlag = 1, the size of the skipped frames in bits. | |
| 869 | * Note: Currently kernel only supports 16 bits for SizeSkipFrames. | |
| 870 | */ | |
| 871 | uint32_t SizeSkipFrames; | |
| 872 | ||
| 873 | /*! \brief Specifies the minimum Qp to be used for BRC. | |
| 874 | * | |
| 875 | * BRCMaxQp and BRCMinQp may be set at a per frame type (I, P, B) granularity. | |
| 876 | * BRCMaxQp and BRCMinQp should be set to zero if Qp control is not desired. | |
| 877 | * If non-zero min/max QP is passed for I-frame, it will be used for I, P and B frames. | |
| 878 | * If non-zero min/max QP is passed for P-frame also, then P and B frame will be updated to this. I-frame remains unchanged. | |
| 879 | * If non-zero min/max QP is passed for B-frame also, then B-frame will be updated to this. I and P frame remains unchanged. | |
| 880 | * If new QP values are passed in between the sequence, then it will be updated for that frame-type and any other frame types that are not explicitly set. Eg. if min/max QP for P-frame was passed separately, and an update for I-frame is received, then only I-frame values are updated. P and B will continue to use old values. But, if P-frame and B-frame were never explicitly set then updating I-frame will also update P and B. | |
| 881 | * If the application wants to keep the current non-zero min/max QP settings, then min/max QP should be set to zero, so the driver will not change previously set values and continue to use them. | |
| 882 | * Min QP is expected to be less than or equal to Max QP. Driver clamps max QP to [1, 51] and min QP to [1, max QP]. Zero QP is not used. | |
| 883 | * Only single PAK pass is supported plus the IPCM pass. Panic mode is disabled. This is because min/maxQP requirement conflicts with the HRD compliancy requirement, so the HRD compliancy restriction is relaxed. | |
| 884 | */ | |
| 885 | uint8_t ucMinimumQP; | |
| 886 | uint8_t ucMaximumQP; //!< Specifies the maximum Qp to be used for BRC. | |
| 887 | ||
| 888 | uint32_t dwZMvThreshold; //!< Used for static frame detection. | |
| 889 | ||
| 890 | /*! \brief Indicates that an HMEOffset will be sent by the application in HMEOffset for each reference. | |
| 891 | * | |
| 892 | * This offset will be added to the co-located (0, 0) location before HME search is performed. This is only valid if HMEOffsetSupport is reported as supported as a capability, else this flag is ignored. | |
| 893 | */ | |
| 894 | bool bEnableHMEOffset; | |
| 895 | /*! \brief Specifies the HME offsets. | |
| 896 | * | |
| 897 | * Curently the supported range is -128 to +127, programmed in 4x downscaled HME precision, not the original size. HMEOffset[i][j] where: | |
| 898 | * \n - i – RefFrameList Index | |
| 899 | * \n - j – 0 = x, 1 = y Coordinates | |
| 900 | * \n So for example, HMEOffset[i] specifies the (x, y) offset corresponding to the ith entry in RefFrameList. | |
| 901 | * Programming Note: The HME offset must be a multiple of 4x4 to align to the 4x4 HME block, so the driver must align the application supplied value. | |
| 902 | */ | |
| 903 | int16_t HMEOffset[16][2][2]; | |
| 904 | ||
| 905 | /*! \brief Specifies Inter MB partition modes that will be disabled. | |
| 906 | * | |
| 907 | * SubMbPartMask is only valid when bEnableSubMbPartMask is true. Bit0~6 indicate inter 16x16, 16x8, 8x16, 8x8, 8x4, 4x8, 4x4. | |
| 908 | */ | |
| 909 | bool bEnableSubMbPartMask; | |
| 910 | uint8_t SubMbPartMask; | |
| 911 | ||
| 912 | /*! \brief Specifies motion search modes that will be used. | |
| 913 | * | |
| 914 | * SubPelMode is only valid when bEnableSubPelMode is true. Following are valid values of SubPelMode: | |
| 915 | * 0:Integer mode searching | |
| 916 | * 1:Half-pel mode searching | |
| 917 | * 2:Reserved | |
| 918 | * 3:Quarter-pel mode searching | |
| 919 | */ | |
| 920 | bool bEnableSubPelMode; | |
| 921 | uint8_t SubPelMode; | |
| 922 | ||
| 923 | /*! \brief Specifies whether extra partition decision refinement is done after the initial partition decision candidate is determined. | |
| 924 | * | |
| 925 | * It has performance tradeoff for better quality. | |
| 926 | * \n - 0 : DEFAULT - Follow driver default settings. | |
| 927 | * \n - 1 : FORCE_ENABLE - Enable this feature totally for all cases. | |
| 928 | * \n - 2 : FORCE_DISABLE - Disable this feature totally for all cases. | |
| 929 | */ | |
| 930 | uint32_t ForceRepartitionCheck; | |
| 931 | ||
| 932 | /*! \brief Specifies force-to-skip for HRD compliance in BRC kernel that will be disabled. | |
| 933 | * | |
| 934 | * bDisableFrameSkip is only valid for P/B frames | |
| 935 | * 0: force-to-skip will be enabled as required in BRC kernel. Default value. | |
| 936 | * 1: force-to-skip will be disabled in BRC kernel. | |
| 937 | */ | |
| 938 | bool bDisableFrameSkip; | |
| 939 | ||
| 940 | /*! \brief Maximum frame size for all frame types in bytes. | |
| 941 | * | |
| 942 | * Applicable for CQP and multi PAK. If dwMaxFrameSize > 0, driver will do multiple PAK and adjust QP | |
| 943 | * (frame level QP + slice_qp_delta) to make the compressed frame size to be less than this value. | |
| 944 | * If dwMaxFrameSize equals 0, driver will not do multiple PAK and do not adjust QP. | |
| 945 | */ | |
| 946 | uint32_t dwMaxFrameSize; | |
| 947 | ||
| 948 | /*! \brief Total pass number for multiple PAK. | |
| 949 | * | |
| 950 | * Valid range is 0 - 4. If dwNumPasses is set to 0, driver will not do multiple PAK and do not adjust | |
| 951 | * QP (frame level QP + slice_qp_delta), otherwise, driver will do multiple times PAK and in each time | |
| 952 | * the QP will be adjust according deltaQp parameters. | |
| 953 | */ | |
| 954 | uint32_t dwNumPasses; | |
| 955 | ||
| 956 | /*! \brief Delta QP array for each PAK pass. | |
| 957 | * | |
| 958 | * This pointer points to an array of deltaQp, the max array size for AVC encoder is 4. The valid range | |
| 959 | * for each deltaQp is 0 - 51. If the value is out of this valid range, driver will return error. | |
| 960 | * Otherwise, driver will adjust QP (frame level QP + slice_qp_delta) by adding this value in each PAK pass. | |
| 961 | */ | |
| 962 | uint8_t *pDeltaQp; | |
| 963 | ||
| 964 | /*! \brief Specifies target frame size in TCBRC mode. | |
| 965 | * | |
| 966 | * If TCBRCSupport == 1, this parameter enables "Transport Controlled BRC mode" and indicates the desired frame size in bytes. | |
| 967 | * - If the value equals 0, the BRC mode defined in RateControlMethod will take control for that certain frame. | |
| 968 | * If TCBRCSupport == 0, this parameter will be ignored and should be set to 0. The BRC mode defined in RateControlMethod will be applied. | |
| 969 | */ | |
| 970 | uint32_t TargetFrameSize; | |
| 971 | ||
| 972 | /*! \brief Indicates if GPU polling based sync is enabled. | |
| 973 | * | |
| 974 | * Applicaiton sets to 1 to enable GPU polling based sync in driver. | |
| 975 | */ | |
| 976 | bool bEnableSync; | |
| 977 | ||
| 978 | /*! \brief Indicates if the current frame is repeat frame. | |
| 979 | * | |
| 980 | * Applicaiton sets to 1 if current frame is repeat frame. | |
| 981 | */ | |
| 982 | bool bRepeatFrame; | |
| 983 | ||
| 984 | /*! \brief Indicates if enable QP adjustment for current frame. | |
| 985 | * | |
| 986 | * Applicaiton sets to 1 to enable QP adjustment for current frame in CQP mode. | |
| 987 | * When QP adjustment is enabled, driver calls MBBRC kernel to adjust per MB QP for perceptual quality in CQP mode. | |
| 988 | */ | |
| 989 | bool bEnableQpAdjustment; | |
| 990 | ||
| 991 | /*! \brief Indicates marker coordinates in raw surface for GPU polling based sync. | |
| 992 | * | |
| 993 | * In unite of bytes. Valid for encoders which report SyncSupport capability as true. | |
| 994 | */ | |
| 995 | uint16_t SyncMarkerX; | |
| 996 | uint16_t SyncMarkerY; | |
| 997 | ||
| 998 | /*! \brief Point to marker value for GPU polling based sync. | |
| 999 | * | |
| 1000 | * Valid for encoders which report SyncSupport capability as true. | |
| 1001 | */ | |
| 1002 | uint8_t *pSyncMarkerValue; | |
| 1003 | ||
| 1004 | /*! \brief Indicates marker value for GPU polling based sync. | |
| 1005 | * | |
| 1006 | * In unit of bytes. Should be larger than or equal to 4. Valid for encoders which report SyncSupport capability as true. | |
| 1007 | */ | |
| 1008 | uint32_t SyncMarkerSize; | |
| 1009 | ||
| 1010 | /*! \brief hierarchical level plus one for pyramid encoding. | |
| 1011 | * | |
| 1012 | * When HierarchLevelPlus1 > 0, HierarchLevelPlus1 – 1 indicates the current frame’s hierarchical level. | |
| 1013 | * And it is for both random access and low delay hierarchical structure. | |
| 1014 | * HierarchLevelPlus1 == 0 can be treated as meaningless. It is defined as a legacy reason for HEVC. | |
| 1015 | */ | |
| 1016 | uint8_t HierarchLevelPlus1; | |
| 1017 | ||
| 1018 | /*! \brief QP modulation strength for BRC | |
| 1019 | * | |
| 1020 | * Suggestion of the strength of applying Qp delta for the frame specified when Qp modulation is enabled (HierarchicalFlag == 1). | |
| 1021 | * This is a relative number. BRC could use it to infer final delta Qp values for hierarchical frames in mini Gop structure. | |
| 1022 | * Default value 0 means no suggestion for Qp modulation | |
| 1023 | */ | |
| 1024 | uint8_t QpModulationStrength; | |
| 1025 | ||
| 1026 | } CODEC_AVC_ENCODE_PIC_PARAMS, *PCODEC_AVC_ENCODE_PIC_PARAMS; | |
| 1027 | ||
| 1028 | /*! \brief Slice-level parameters of a compressed picture for AVC encoding. | |
| 1029 | */ | |
| 1030 | typedef struct _CODEC_AVC_ENCODE_SLICE_PARAMS | |
| 1031 | { | |
| 1032 | /*! \brief Specifies the number of macroblocks for this slice. | |
| 1033 | * | |
| 1034 | * Note the slice height restriction in picture parameter structure. | |
| 1035 | */ | |
| 1036 | uint32_t NumMbsForSlice; | |
| 1037 | /*! \brief Specifies the reference picture lists 0 and 1 | |
| 1038 | * | |
| 1039 | * Contains field/frame information concerning the reference in PicFlags. RefPicList[i][j]: | |
| 1040 | * \n - i: the reference picture list (0 or 1) | |
| 1041 | * \n - j: if the PicFlags are not PICTURE_INVALID, the index variable j is a reference to entry j in teh reference picture list. | |
| 1042 | */ | |
| 1043 | CODEC_PICTURE RefPicList[CODEC_AVC_NUM_REF_LISTS][CODEC_MAX_NUM_REF_FIELD]; | |
| 1044 | /*! \brief Specifies the weights and offsets used for explicit mode weighted prediction. | |
| 1045 | * | |
| 1046 | * Weigths[i][j][k][m]: | |
| 1047 | * \n - i: the reference picture list (0 or 1) | |
| 1048 | * \n - j: reference to entry j in RefPicList (has range [0...31]) | |
| 1049 | * \n - k: the YUV component (0 = luma, 1 = Cb chroma, 2 = Cr chroma) | |
| 1050 | * \n - m: the weight or offset used in the weighted prediction process (0 = weight, 1 = offset) | |
| 1051 | */ | |
| 1052 | int16_t Weights[2][32][3][2]; | |
| 1053 | ||
| 1054 | uint32_t first_mb_in_slice; //!< Same as AVC syntax element. | |
| 1055 | uint8_t slice_type; //!< Same as AVC syntax element. | |
| 1056 | uint8_t pic_parameter_set_id; //!< Same as AVC syntax element. | |
| 1057 | uint16_t direct_spatial_mv_pred_flag : 1; //!< Same as AVC syntax element. | |
| 1058 | uint16_t num_ref_idx_active_override_flag : 1; //!< Same as AVC syntax element. | |
| 1059 | uint16_t long_term_reference_flag : 1; //!< Same as AVC syntax element. | |
| 1060 | uint16_t : 13; | |
| 1061 | uint16_t idr_pic_id; //!< Same as AVC syntax element. | |
| 1062 | uint16_t pic_order_cnt_lsb; //!< Same as AVC syntax element. | |
| 1063 | int32_t delta_pic_order_cnt_bottom; //!< Same as AVC syntax element. | |
| 1064 | int32_t delta_pic_order_cnt[2]; //!< Same as AVC syntax element. | |
| 1065 | uint8_t num_ref_idx_l0_active_minus1; //!< Same as AVC syntax element. | |
| 1066 | uint8_t num_ref_idx_l1_active_minus1; //!< Same as AVC syntax element. | |
| 1067 | uint8_t num_ref_idx_l0_active_minus1_from_DDI; | |
| 1068 | uint8_t num_ref_idx_l1_active_minus1_from_DDI; | |
| 1069 | uint8_t luma_log2_weight_denom; //!< Same as AVC syntax element. | |
| 1070 | uint8_t chroma_log2_weight_denom; //!< Same as AVC syntax element. | |
| 1071 | uint8_t cabac_init_idc; //!< Same as AVC syntax element. | |
| 1072 | char slice_qp_delta; //!< Same as AVC syntax element. | |
| 1073 | uint8_t disable_deblocking_filter_idc; //!< Same as AVC syntax element. | |
| 1074 | char slice_alpha_c0_offset_div2; //!< Same as AVC syntax element. | |
| 1075 | char slice_beta_offset_div2; //!< Same as AVC syntax element. | |
| 1076 | uint32_t slice_id; //!< Same as AVC syntax element. | |
| 1077 | /*! \brief Indicates that the weighting factors for the luma component are present. | |
| 1078 | * | |
| 1079 | * luma_weight_flag[i] is interpreted as corresponding to L0 when i=0 and L1 when i=1. Each bit n of luma_weight_flag[i] corresponds to the nth entry in reference list i. The framework must obey the caps the driver reported in MaxNum_WeightedPredL0/L1. | |
| 1080 | */ | |
| 1081 | uint32_t luma_weight_flag[2]; | |
| 1082 | /*! \brief Indicates that the weighting factors for the chroma component are present. | |
| 1083 | * | |
| 1084 | * chroma_weight_flag[i] is interpreted as corresponding to L0 when i=0 and L1 when i=1. Each bit n of chroma_weight_flag[i] corresponds to the nth entry in reference list i. The framework must obey the caps the driver reported in MaxNum_WeightedPredL0/L1. | |
| 1085 | */ | |
| 1086 | uint32_t chroma_weight_flag[2]; | |
| 1087 | ||
| 1088 | CODEC_PIC_REORDER PicOrder[2][32]; //!< Set by the driver | |
| 1089 | ||
| 1090 | uint8_t colour_plane_id; //!< Same as AVC syntax element. | |
| 1091 | uint32_t frame_num; //!< Same as AVC syntax element. | |
| 1092 | bool field_pic_flag; //!< Same as AVC syntax element. | |
| 1093 | bool bottom_field_flag; //!< Same as AVC syntax element. | |
| 1094 | uint8_t redundant_pic_cnt; //!< Same as AVC syntax element. | |
| 1095 | char sp_for_switch_flag; //!< Same as AVC syntax element. | |
| 1096 | char slice_qs_delta; //!< Same as AVC syntax element. | |
| 1097 | uint8_t ref_pic_list_reordering_flag_l0 : 1; //!< Same as AVC syntax element. | |
| 1098 | uint8_t ref_pic_list_reordering_flag_l1 : 1; //!< Same as AVC syntax element. | |
| 1099 | uint8_t no_output_of_prior_pics_flag : 1; //!< Same as AVC syntax element. | |
| 1100 | uint8_t adaptive_ref_pic_marking_mode_flag : 1; //!< Same as AVC syntax element. | |
| 1101 | uint8_t : 3; | |
| 1102 | uint32_t MaxFrameNum; //!< Set by the driver: 1 << (pSeqParams[pPicParams->seq_parameter_set_id].log2_max_frame_num_minus4 + 4); | |
| 1103 | uint8_t NumReorder; //!< Set by the driver | |
| 1104 | } CODEC_AVC_ENCODE_SLICE_PARAMS, *PCODEC_AVC_ENCODE_SLICE_PARAMS; | |
| 1105 | ||
| 1106 | // H.264 Inverse Quantization Weight Scale | |
| 1107 | typedef struct _CODEC_AVC_ENCODE_IQ_WEIGTHSCALE_LISTS | |
| 1108 | { | |
| 1109 | uint8_t WeightScale4x4[6][16]; | |
| 1110 | uint8_t WeightScale8x8[2][64]; | |
| 1111 | } CODEC_AVC_ENCODE_IQ_WEIGTHSCALE_LISTS, *PCODEC_AVC_ENCODE_IQ_WEIGTHSCALE_LISTS; | |
| 1112 | ||
| 1113 | // used for PAFF case, 0: frame, 1: tff field, 2: invalid, 3: bff field | |
| 1114 | typedef enum _CODEC_AVC_PIC_CODING_TYPE_VALUE | |
| 1115 | { | |
| 1116 | CODEC_AVC_PIC_CODING_TYPE_FRAME = 0x0, | |
| 1117 | CODEC_AVC_PIC_CODING_TYPE_TFF_FIELD = 0x1, | |
| 1118 | CODEC_AVC_PIC_CODING_TYPE_INVALID = 0x2, | |
| 1119 | CODEC_AVC_PIC_CODING_TYPE_BFF_FIELD = 0x3 | |
| 1120 | } CODEC_AVC_PIC_CODING_TYPE_VALUE; | |
| 1121 | ||
| 1122 | //! | |
| 1123 | //! \struct CodecEncodeAvcFeiPicParams | |
| 1124 | //! \brief Codec encode AVC FEI pic params | |
| 1125 | //! | |
| 1126 | struct CodecEncodeAvcFeiPicParams | |
| 1127 | { | |
| 1128 | MOS_RESOURCE resMBCtrl; // input MB control buffer | |
| 1129 | MOS_RESOURCE resMVData; // ENC MV output buffer or PAK MV input buffer | |
| 1130 | MOS_RESOURCE resMBCode; // ENC MBCode output buffer or PAK MBCode input buffer | |
| 1131 | MOS_RESOURCE resMVPredictor; // input MV predictor surface | |
| 1132 | MOS_RESOURCE resMBQp; // input QP per MB surface | |
| 1133 | MOS_RESOURCE resDistortion; // ENC or ENC_PAK Distortion output surface | |
| 1134 | uint32_t NumMVPredictorsL0; | |
| 1135 | uint32_t NumMVPredictorsL1; | |
| 1136 | ||
| 1137 | bool MbCodeMvEnable; | |
| 1138 | bool DistortionEnable; | |
| 1139 | ||
| 1140 | /** \brief control parameters */ | |
| 1141 | uint32_t SearchPath; | |
| 1142 | uint32_t LenSP; | |
| 1143 | ||
| 1144 | uint32_t SubMBPartMask; | |
| 1145 | uint32_t IntraPartMask; | |
| 1146 | bool MultiPredL0; | |
| 1147 | bool MultiPredL1; | |
| 1148 | uint32_t SubPelMode; | |
| 1149 | uint32_t InterSAD; | |
| 1150 | uint32_t IntraSAD; | |
| 1151 | uint32_t DistortionType; | |
| 1152 | bool RepartitionCheckEnable; | |
| 1153 | bool AdaptiveSearch; | |
| 1154 | bool MVPredictorEnable; | |
| 1155 | bool bMBQp; | |
| 1156 | bool bPerMBInput; | |
| 1157 | bool bMBSizeCtrl; | |
| 1158 | uint32_t RefWidth; | |
| 1159 | uint32_t RefHeight; | |
| 1160 | uint32_t SearchWindow; | |
| 1161 | ||
| 1162 | //add for mutlple pass pak | |
| 1163 | uint32_t dwMaxFrameSize; | |
| 1164 | uint32_t dwNumPasses; //number of QPs | |
| 1165 | uint8_t *pDeltaQp; //list of detla QPs | |
| 1166 | }; | |
| 1167 | #endif // __CODEC_DEF_ENCODE_AVC_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_encode_jpeg.h | |
| 23 | //! \brief Defines encode JPEG types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to JPEG encode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | ||
| 27 | #ifndef __CODEC_DEF_ENCODE_JPEG_H__ | |
| 28 | #define __CODEC_DEF_ENCODE_JPEG_H__ | |
| 29 | ||
| 30 | #include "codec_def_common_jpeg.h" | |
| 31 | #include "codec_def_common_encode.h" | |
| 32 | ||
| 33 | #define JPEG_MAX_NUM_QUANT_TABLE_INDEX 3 // Max 3 quant tables are allowed for encode | |
| 34 | #define JPEG_MAX_QUANT_TABLE 3 // MAx Number of Quantization tables that can be sent by the application | |
| 35 | #define JPEG_NUM_ENCODE_HUFF_BUFF 4 // Total number of Huffman tables that app can send for JPEG encode (2AC and 2DC tables allowed per frame) | |
| 36 | ||
| 37 | // Max supported resolution for JPEG encode is 16K X 16K | |
| 38 | #define ENCODE_JPEG_MAX_PIC_WIDTH 16384 | |
| 39 | #define ENCODE_JPEG_MAX_PIC_HEIGHT 16384 | |
| 40 | ||
| 41 | #define JPEG_MAX_NUM_HUFF_TABLES 2 // Max 2 sets of Huffman Tables are allowed (2AC and 2 DC) | |
| 42 | ||
| 43 | //! | |
| 44 | //! \struct CodecEncodeJpegQuantTable | |
| 45 | //! \brief Define JPEG Quant Table | |
| 46 | //! | |
| 47 | struct CodecEncodeJpegQuantTable | |
| 48 | { | |
| 49 | struct | |
| 50 | { | |
| 51 | uint32_t m_tableID; //!< Table ID | |
| 52 | uint32_t m_precision; //!< Precision | |
| 53 | uint16_t m_qm[JPEG_NUM_QUANTMATRIX]; //!< Quant Matrix | |
| 54 | } m_quantTable[JPEG_MAX_NUM_QUANT_TABLE_INDEX]; //!< Quant table array | |
| 55 | }; | |
| 56 | ||
| 57 | //! | |
| 58 | //! \struct CodecEncodeJpegHuffData | |
| 59 | //! \brief Define Huffman data for JPEG encode | |
| 60 | //! | |
| 61 | struct CodecEncodeJpegHuffData | |
| 62 | { | |
| 63 | uint32_t m_tableClass; //!< table class | |
| 64 | uint32_t m_tableID; //!< table ID | |
| 65 | uint8_t m_bits[JPEG_NUM_HUFF_TABLE_AC_BITS]; //!< AC bits | |
| 66 | uint8_t m_huffVal[JPEG_NUM_HUFF_TABLE_AC_HUFFVAL]; //!< AC Huffman value | |
| 67 | }; | |
| 68 | ||
| 69 | //! | |
| 70 | //! \struct CodecEncodeJpegHuffmanDataArray | |
| 71 | //! \brief Define Huffman data array for JPEG encode | |
| 72 | //! | |
| 73 | struct CodecEncodeJpegHuffmanDataArray | |
| 74 | { | |
| 75 | //!< huffmanData[0] --> Table for DC component of luma | |
| 76 | //!< huffmanData[1] --> Table for AC component of luma | |
| 77 | //!< huffmanData[2] --> Table for DC component of chroma | |
| 78 | //!< huffmanData[3] --> Table for AC component of chroma | |
| 79 | CodecEncodeJpegHuffData m_huffmanData[JPEG_NUM_ENCODE_HUFF_BUFF]; | |
| 80 | }; | |
| 81 | ||
| 82 | //! | |
| 83 | //! \enum CodecEncodeJpegInputSurfaceFormat | |
| 84 | //! \brief matches up with InputSurfaceFormats | |
| 85 | //! (converted from MOS format in ConvertMediaFormatToInputSurfaceFormat()) | |
| 86 | //! May want to unify enums instead of casting | |
| 87 | //! | |
| 88 | enum CodecEncodeJpegInputSurfaceFormat | |
| 89 | { | |
| 90 | codechalJpegNV12 = 1, //!< NV12 surface format | |
| 91 | codechalJpegUYVY = 2, //!< UYVY surface format | |
| 92 | codechalJpegYUY2 = 3, //!< YUY2 surface format | |
| 93 | codechalJpegY8 = 4, //!< Y8 surface format | |
| 94 | codechalJpegRGB = 5 //!< RGB surface format | |
| 95 | }; | |
| 96 | ||
| 97 | //! | |
| 98 | //! \struct CodecEncodeJpegPictureParams | |
| 99 | //! \brief Picture Parameter Set for JPEG Encode | |
| 100 | //! | |
| 101 | struct CodecEncodeJpegPictureParams | |
| 102 | { | |
| 103 | uint32_t m_profile : 2; //!< Profile. 0 -Baseline, 1 - Extended, 2 - Lossless, 3 - Hierarchical | |
| 104 | uint32_t m_progressive : 1; //!< Progressive flag. 1- Progressive, 0 - Sequential | |
| 105 | uint32_t m_huffman : 1; //!< Huffman flag. 1 - Huffman , 0 - Arithmetic | |
| 106 | uint32_t m_interleaved : 1; //!< Interleaved flag. 1 - Interleaved, 0 - NonInterleaved | |
| 107 | uint32_t m_differential : 1; //!< Differential flag. 1 - Differential, 0 - NonDifferential | |
| 108 | ||
| 109 | uint32_t m_picWidth; //!< Picture Width | |
| 110 | uint32_t m_picHeight; //!< Picture Height | |
| 111 | ||
| 112 | uint32_t m_inputSurfaceFormat; //!< Input surface format | |
| 113 | uint32_t m_sampleBitDepth; //!< Sample bit depth | |
| 114 | ||
| 115 | uint32_t m_numComponent; //!< Component Number | |
| 116 | uint8_t m_componentID[4]; //!< Component ID | |
| 117 | uint8_t m_quantTableSelector[4]; //!< Quant table selector | |
| 118 | ||
| 119 | uint32_t m_quality; //!< Quality | |
| 120 | ||
| 121 | uint32_t m_numScan; //!< Scan number | |
| 122 | uint32_t m_numQuantTable; //!< Quant table number | |
| 123 | uint32_t m_numCodingTable; //!< Coding table number | |
| 124 | ||
| 125 | uint32_t m_statusReportFeedbackNumber; //!< Status report feedback number | |
| 126 | ||
| 127 | }; | |
| 128 | ||
| 129 | //! | |
| 130 | //! \struct CodecEncodeJpegScanHeader | |
| 131 | //! \brief Scan Header structure for JPEG Encode | |
| 132 | //! | |
| 133 | struct CodecEncodeJpegScanHeader | |
| 134 | { | |
| 135 | uint32_t m_restartInterval; //!< Restart Interval | |
| 136 | ||
| 137 | uint32_t m_numComponent; //!< Component number | |
| 138 | uint8_t m_componentSelector[4]; //!< Component selector | |
| 139 | uint8_t m_dcCodingTblSelector[4]; //!< DC coding table selector | |
| 140 | uint8_t m_acCodingTblSelector[4]; //!< AC coding table selector | |
| 141 | ||
| 142 | }; | |
| 143 | ||
| 144 | // matrix required to read in the quantization matrix | |
| 145 | static const uint8_t jpeg_qm_scan_8x8[64] = | |
| 146 | { | |
| 147 | // Zig-Zag scan pattern | |
| 148 | 0, 1, 8, 16, 9, 2, 3, 10, | |
| 149 | 17, 24, 32, 25, 18, 11, 4, 5, | |
| 150 | 12, 19, 26, 33, 40, 48, 41, 34, | |
| 151 | 27, 20, 13, 6, 7, 14, 21, 28, | |
| 152 | 35, 42, 49, 56, 57, 50, 43, 36, | |
| 153 | 29, 22, 15, 23, 30, 37, 44, 51, | |
| 154 | 58, 59, 52, 45, 38, 31, 39, 46, | |
| 155 | 53, 60, 61, 54, 47, 55, 62, 63 | |
| 156 | }; | |
| 157 | ||
| 158 | #endif // __CODEC_DEF_ENCODE_JPEG_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_encode_mpeg2.h | |
| 23 | //! \brief Defines encode MPEG2 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to MPEG2 encode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | ||
| 27 | #ifndef __CODEC_DEF_ENCODE_MPEG2_H__ | |
| 28 | #define __CODEC_DEF_ENCODE_MPEG2_H__ | |
| 29 | ||
| 30 | #include "codec_def_common_encode.h" | |
| 31 | #include "codec_def_common_mpeg2.h" | |
| 32 | ||
| 33 | #define CODEC_ENCODE_MPEG2_BRC_PIC_HEADER_SURFACE_SIZE 1024 | |
| 34 | #define CODEC_ENCODE_MPEG2_VBV_BUFFER_SIZE_UNITS (16 * 1024) //!< 16 K bits | |
| 35 | #define CODEC_ENCODE_MPEG2_MAX_NAL_TYPE 0x1f | |
| 36 | ||
| 37 | //! | |
| 38 | //! \enum CodecEncodeMpeg2ExtensionStartCode | |
| 39 | //! \brief Codec encode MPEG2 extension start code | |
| 40 | //! | |
| 41 | enum CodecEncodeMpeg2ExtensionStartCode | |
| 42 | { | |
| 43 | // 0x00 - Reserved | |
| 44 | Mpeg2sequenceExtension = 0x01, | |
| 45 | Mpeg2sequenceDisplayExtension = 0x02, | |
| 46 | Mpeg2quantMatrixExtension = 0x03, | |
| 47 | Mpeg2copyrightExtension = 0x04, | |
| 48 | Mpeg2sequnceScalableExtension = 0x05, | |
| 49 | // 0x06 - Reserved | |
| 50 | Mpeg2pictureDisplayExtension = 0x07, | |
| 51 | Mpeg2pictureCodingExtension = 0x08, | |
| 52 | Mpeg2pictureSpatialScalableExtension = 0x09, | |
| 53 | Mpeg2pictureTemporalScalableExtension = 0x0A | |
| 54 | // 0x0B .. 0x0F - Reserved | |
| 55 | } ; | |
| 56 | ||
| 57 | //! | |
| 58 | //! \struct CodecEncodeMpeg2SequenceParams | |
| 59 | //! \brief MPEG2 Sequence Parameter Set | |
| 60 | //! | |
| 61 | struct CodecEncodeMpeg2SequenceParams | |
| 62 | { | |
| 63 | uint16_t m_frameWidth; //!< Width of picture in unit of pixels | |
| 64 | uint16_t m_frameHeight; //!< Height of picture in unit pixels | |
| 65 | uint8_t m_profile; //!< Profile | |
| 66 | uint8_t m_level; //!< Level | |
| 67 | uint8_t m_chromaFormat; //!< Color sampling formats | |
| 68 | uint8_t m_targetUsage; //!< Target usage number, indicates trade-offs between quality and speed | |
| 69 | ||
| 70 | // ENC + PAK related parameters | |
| 71 | union | |
| 72 | { | |
| 73 | uint16_t m_aratioFrate; //!< Aspect ratio and frame rate | |
| 74 | struct | |
| 75 | { | |
| 76 | uint16_t m_aspectRatio : 4; //!< Aspect ratio | |
| 77 | uint16_t m_frameRateCode : 4; //!< Frame rate Code | |
| 78 | uint16_t m_frameRateExtN : 3; //!< Frame rate extend numerator | |
| 79 | uint16_t m_frameRateExtD : 5; //!< Frame rate extend denominator | |
| 80 | }; | |
| 81 | }; | |
| 82 | ||
| 83 | uint32_t m_bitrate; //!< Bit rate bits per second | |
| 84 | uint32_t m_vbvBufferSize; //!< VBV buffer size in bits | |
| 85 | ||
| 86 | uint8_t m_progressiveSequence : 1; //!< Indicate progressive sequence | |
| 87 | uint8_t m_lowDelay : 1; //!< Indicate low delay | |
| 88 | uint8_t m_resetBRC : 1; //!< Indicate if a BRC reset is desired to set a new bit rate or frame rate | |
| 89 | uint8_t m_noAcceleratorSPSInsertion : 1; //!< Indicates if current SPS is just a BRC parameter update, not a SPS change to be inserted into the bitstream. | |
| 90 | uint8_t m_forcePanicModeControl : 1; // Force to control the panic mode through DDI. | |
| 91 | uint8_t m_panicModeDisable : 1; // Disable the panic mode | |
| 92 | uint8_t m_reserved0 : 2; //!< Reserved | |
| 93 | uint8_t m_rateControlMethod; //!< rate control method, CBR = 1, VBR = 2, AVBR = 4, CQP = 3 | |
| 94 | uint16_t m_reserved1; //!< Reserved | |
| 95 | uint32_t m_maxBitRate; //!< Maximum bit rate, bits/sec | |
| 96 | uint32_t m_minBitRate; //!< Minimum bit rate, bits/sec | |
| 97 | uint32_t m_userMaxFrameSize; //!< Maximum frame size by user | |
| 98 | uint32_t m_initVBVBufferFullnessInBit; //!< Initial VBV buffer fullness size in bits | |
| 99 | uint16_t m_reserved2; //!< Reserved | |
| 100 | uint16_t m_reserved3; //!< Reserved | |
| 101 | } ; | |
| 102 | ||
| 103 | //! | |
| 104 | //! \struct CodecEncodeMpeg2PictureParams | |
| 105 | //! \brief MPEG2 Picture Parameter Set | |
| 106 | //! | |
| 107 | struct CodecEncodeMpeg2PictureParams | |
| 108 | { | |
| 109 | CODEC_PICTURE m_currOriginalPic; //!< The current uncompressed original frame surface for encoding | |
| 110 | CODEC_PICTURE m_currReconstructedPic; //!< The uncompressed frame surface for the current reconstructed picture. | |
| 111 | uint8_t m_pictureCodingType; //!< Coding Type | |
| 112 | uint8_t m_fieldCodingFlag : 1; //!< Indication of field mode coding when set to 1. | |
| 113 | uint8_t m_fieldFrameCodingFlag : 1; //!< Indication interlaced frame coding | |
| 114 | uint8_t m_reserved0 : 2; //!< Reserved | |
| 115 | uint8_t m_interleavedFieldBFF : 1; //!< Indication of input picture layout has top field and bottom field interleaved together | |
| 116 | //!< with bottom field first when set to 1; otherwise (when set to 0) it is | |
| 117 | //!< interleaved with top field first. | |
| 118 | uint8_t m_progressiveField : 1; //!< Indication of input picture layout has only one field picture (half of a frame) stored progressively | |
| 119 | uint8_t m_reserved1 : 2; //!< Reserved | |
| 120 | ||
| 121 | uint8_t m_numSlice; //!< Number of slices per frame; number of slices per field in field coding | |
| 122 | uint8_t m_picBackwardPrediction; //!< Indicates whether any macroblocks of the current picture might include backward prediction | |
| 123 | uint8_t m_bidirectionalAveragingMode; //!< Indicates the rounding method for combining prediction planes in bidirectional motion compensation | |
| 124 | uint8_t m_pic4MVallowed; //!< Picture 4 MV allowed | |
| 125 | CODEC_PICTURE m_refFrameList[2]; //!< List of reference frame buffers | |
| 126 | bool m_useRawPicForRef; //!< Setting to 1 may improve performance at the cost of image quality | |
| 127 | uint32_t m_statusReportFeedbackNumber; //!< The status report feedback data | |
| 128 | ||
| 129 | uint32_t m_alternateScan : 1; //!< Indicate the Inverse Scan method | |
| 130 | uint32_t m_intraVlcFormat : 1; //!< Intra VLC format | |
| 131 | uint32_t m_qscaleType : 1; //!< Quantizer Scale Type | |
| 132 | uint32_t m_concealmentMotionVectors : 1; //!< Indicates if the concealment motion vectors are coded in intra macroblocks | |
| 133 | uint32_t m_framePredFrameDCT : 1; //!< Frame Prediction Frame DCT | |
| 134 | uint32_t m_disableMismatchControl : 1; //!< Disable mismatch control | |
| 135 | uint32_t m_intraDCprecision : 2; //!< Intra DC Precision | |
| 136 | uint32_t m_fcode00 : 4; //!< Used for forward horizontal motion vector prediction | |
| 137 | uint32_t m_fcode01 : 4; //!< Used for forward vertical motion vector prediction | |
| 138 | uint32_t m_fcode10 : 4; //!< Used for backward horizontal motion vector prediction | |
| 139 | uint32_t m_fcode11 : 4; //!< Used for backward vertical motion vector prediction | |
| 140 | uint32_t m_reserved2 : 8; //!< Reserved | |
| 141 | ||
| 142 | // ENC + PAK related parameters | |
| 143 | bool m_lastPicInStream; //!< Indicate the last picture of the stream | |
| 144 | bool m_newGop; //!< Indicates that a new GOP will start with this picture | |
| 145 | ||
| 146 | uint16_t m_gopPicSize; //!< Number of pictures within the current GOP | |
| 147 | uint8_t m_gopRefDist; //!< Distance between I- or P (or GPB) - key frames | |
| 148 | uint8_t m_gopOptFlag : 2; //!< Indicate the additional flags for the GOP specification | |
| 149 | uint8_t m_reserved3 : 6; //!< Reserved | |
| 150 | ||
| 151 | uint32_t m_timeCode : 25;//!< Time code | |
| 152 | uint32_t m_reserved4 : 7; //!< Reserved | |
| 153 | ||
| 154 | uint16_t m_temporalReference : 10;//!< Temporal reference | |
| 155 | uint16_t m_reserved5 : 6; //!< Reserved | |
| 156 | ||
| 157 | uint16_t m_vbvDelay; | |
| 158 | ||
| 159 | uint32_t m_repeatFirstField : 1; //!< Repeat first field | |
| 160 | uint32_t m_compositeDisplayFlag : 1; //!< Composite display flag | |
| 161 | uint32_t m_vaxis : 1; //!< Vaxis | |
| 162 | uint32_t m_fieldSequence : 3; //!< Field sequence | |
| 163 | uint32_t m_subCarrier : 1; //!< Sub carrier | |
| 164 | uint32_t m_burstAmplitude : 7; //!< Burst Amplitude | |
| 165 | uint32_t m_subCarrierPhase : 8; //!< Sub carrier phase | |
| 166 | uint32_t m_reserved6 : 10;//!< Reserved | |
| 167 | ||
| 168 | // Parameters for Skip Frames | |
| 169 | uint8_t m_skipFrameFlag; //!< Skip frame flag | |
| 170 | uint8_t m_numSkipFrames; //!< only reserved for BRC case | |
| 171 | uint32_t m_sizeSkipFrames; //!< only reserved for BRC case | |
| 172 | }; | |
| 173 | ||
| 174 | //! | |
| 175 | //! \struct CodecEncodeMpeg2SliceParmas | |
| 176 | //! \brief MPEG2 Slice Parameters | |
| 177 | //! | |
| 178 | struct CodecEncodeMpeg2SliceParmas | |
| 179 | { | |
| 180 | uint16_t m_numMbsForSlice; //!< Number of macroblocks per slice | |
| 181 | uint16_t m_firstMbX; //!< Specifies the horizontal position of the first macroblock of the slice expressed in units of macroblocks | |
| 182 | uint16_t m_firstMbY; //!< Specifies the vertical position of the first macroblock of the slice expressed in units of macroblocks | |
| 183 | uint16_t m_intraSlice; //!< Indicates slices coded as Intra Slice | |
| 184 | uint8_t m_quantiserScaleCode; //!< Quantier scale code | |
| 185 | }; | |
| 186 | ||
| 187 | //! | |
| 188 | //! \struct CodecEncodeMpeg2VuiParams | |
| 189 | //! \brief MPEG2 VUI Parameters | |
| 190 | //! | |
| 191 | struct CodecEncodeMpeg2VuiParams | |
| 192 | { | |
| 193 | uint32_t m_videoFormat : 3; //!< Indicate the representation of the pictures | |
| 194 | uint32_t m_reserved0 : 4; //!< Reserved | |
| 195 | uint32_t m_colourDescription : 1; //!< Indicate the colour description is presented | |
| 196 | uint32_t m_colourPrimaries : 8; //!< The chromaticity coordinates of the source primaries | |
| 197 | uint32_t m_transferCharacteristics : 8; //!< The opto-electronic transfer characteristic of the source picture | |
| 198 | uint32_t m_matrixCoefficients : 8; //!< The matrix coefficients used in deriving luminance and chrominance signals | |
| 199 | ||
| 200 | uint32_t m_displayHorizontalSize : 14;//!< The horizontal size of the display active region | |
| 201 | uint32_t m_reserved1 : 2; //!< Reserved | |
| 202 | uint32_t m_displayVerticalSize : 14;//!< The vertical size of the display active region | |
| 203 | uint32_t m_reserved2 : 2; //!< Reserved | |
| 204 | }; | |
| 205 | ||
| 206 | //! | |
| 207 | //! \struct CodecEncodeMpeg2QmatixParams | |
| 208 | //! \brief MPEG2 QMATRIX Parameters | |
| 209 | //! | |
| 210 | struct CodecEncodeMpeg2QmatixParams | |
| 211 | { | |
| 212 | uint8_t m_newQmatrix[4]; //!< 0 - intra Y, 1 - inter Y, 2 - intra chroma, 3 - inter chroma | |
| 213 | uint16_t m_qmatrix[4][64]; //!< Quantiser matrix | |
| 214 | }; | |
| 215 | ||
| 216 | //! | |
| 217 | //! \struct CodecEncodeMpeg2UserDataList | |
| 218 | //! \brief Linked List for MPEG-2 User Data | |
| 219 | //! User data may be provided in several pieces. | |
| 220 | //! So a linked list is implemented to keep track of them. | |
| 221 | //! | |
| 222 | struct CodecEncodeMpeg2UserDataList | |
| 223 | { | |
| 224 | void *m_userData; | |
| 225 | uint32_t m_userDataSize; | |
| 226 | CodecEncodeMpeg2UserDataList *m_nextItem; | |
| 227 | }; | |
| 228 | ||
| 229 | #endif // __CODEC_DEF_ENCODE_MPEG2_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2017-2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_encode_vp9.h | |
| 23 | //! \brief Defines encode VP9 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to VP9 encode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_ENCODE_VP9_H__ | |
| 27 | #define __CODEC_DEF_ENCODE_VP9_H__ | |
| 28 | ||
| 29 | #include "codec_def_common_encode.h" | |
| 30 | ||
| 31 | #define CODECHAL_ENCODE_VP9_MAX_NUM_TEMPORAL_LAYERS 8 | |
| 32 | #define ENCODE_VP9_NUM_MAX_L0_REF 3 | |
| 33 | ||
| 34 | typedef enum | |
| 35 | { | |
| 36 | VP9_ENCODED_CHROMA_FORMAT_YUV420 = 0, | |
| 37 | VP9_ENCODED_CHROMA_FORMAT_YUV422 = 1, | |
| 38 | VP9_ENCODED_CHROMA_FORMAT_YUV444 = 2 | |
| 39 | } VP9_ENCODED_CHROMA_FORMAT; | |
| 40 | ||
| 41 | typedef enum | |
| 42 | { | |
| 43 | VP9_ENCODED_BIT_DEPTH_8 = 0, | |
| 44 | VP9_ENCODED_BIT_DEPTH_10 = 1, | |
| 45 | VP9_ENCODED_BIT_DEPTH_12 = 2 | |
| 46 | } VP9_ENCODED_BIT_DEPTH; | |
| 47 | ||
| 48 | typedef struct _CODEC_VP9_ENCODE_SEG_PARAMS | |
| 49 | { | |
| 50 | union | |
| 51 | { | |
| 52 | struct | |
| 53 | { | |
| 54 | uint8_t SegmentReferenceEnabled : 1; | |
| 55 | uint8_t SegmentReference : 2; | |
| 56 | uint8_t SegmentSkipped : 1; | |
| 57 | uint8_t ReservedField3 : 4; | |
| 58 | } fields; | |
| 59 | uint8_t value; | |
| 60 | ||
| 61 | } SegmentFlags; | |
| 62 | ||
| 63 | char SegmentLFLevelDelta; | |
| 64 | int16_t SegmentQIndexDelta; | |
| 65 | ||
| 66 | } CODEC_VP9_ENCODE_SEG_PARAMS, *PCODEC_VP9_ENCODE_SEG_PARAMS; | |
| 67 | ||
| 68 | typedef struct _CODEC_VP9_ENCODE_SEGMENT_PARAMS | |
| 69 | { | |
| 70 | CODEC_VP9_ENCODE_SEG_PARAMS SegData[8]; | |
| 71 | ||
| 72 | } CODEC_VP9_ENCODE_SEGMENT_PARAMS, *PCODEC_VP9_ENCODE_SEGMENT_PARAMS; | |
| 73 | ||
| 74 | typedef struct _CODEC_VP9_ENCODE_SEQUENCE_PARAMS | |
| 75 | { | |
| 76 | uint16_t wMaxFrameWidth; | |
| 77 | uint16_t wMaxFrameHeight; | |
| 78 | uint16_t GopPicSize; | |
| 79 | uint8_t TargetUsage; | |
| 80 | uint8_t RateControlMethod; | |
| 81 | uint32_t TargetBitRate[CODECHAL_ENCODE_VP9_MAX_NUM_TEMPORAL_LAYERS]; | |
| 82 | uint32_t MaxBitRate; | |
| 83 | uint32_t MinBitRate; | |
| 84 | uint32_t InitVBVBufferFullnessInBit; | |
| 85 | uint32_t VBVBufferSizeInBit; | |
| 86 | uint32_t OptimalVBVBufferLevelInBit; | |
| 87 | uint32_t UpperVBVBufferLevelThresholdInBit; | |
| 88 | uint32_t LowerVBVBufferLevelThresholdInBit; | |
| 89 | ||
| 90 | union | |
| 91 | { | |
| 92 | struct | |
| 93 | { | |
| 94 | uint32_t bResetBRC : 1; | |
| 95 | uint32_t bNoFrameHeaderInsertion : 1; | |
| 96 | uint32_t bUseRawReconRef : 1; | |
| 97 | uint32_t MBBRC : 4; // This is not to be set for VP9 VDEnc (G10+), this is removed from DDI, only here to support legacy KBL DP | |
| 98 | uint32_t EnableDynamicScaling : 1; | |
| 99 | uint32_t SourceFormat : 2; | |
| 100 | uint32_t SourceBitDepth : 2; | |
| 101 | uint32_t EncodedFormat : 2; | |
| 102 | uint32_t EncodedBitDepth : 2; | |
| 103 | uint32_t DisplayFormatSwizzle : 1; | |
| 104 | uint32_t bReserved : 15; | |
| 105 | } fields; | |
| 106 | ||
| 107 | uint32_t value; | |
| 108 | } SeqFlags; | |
| 109 | ||
| 110 | uint32_t UserMaxFrameSize; | |
| 111 | uint16_t reserved2; | |
| 112 | uint16_t reserved3; | |
| 113 | FRAME_RATE FrameRate[CODECHAL_ENCODE_VP9_MAX_NUM_TEMPORAL_LAYERS]; | |
| 114 | uint8_t NumTemporalLayersMinus1; | |
| 115 | uint8_t ICQQualityFactor; | |
| 116 | ||
| 117 | ENCODE_INPUT_COLORSPACE InputColorSpace; | |
| 118 | ENCODE_SCENARIO ScenarioInfo; | |
| 119 | ENCODE_CONTENT ContentInfo; | |
| 120 | ENCODE_FRAMESIZE_TOLERANCE FrameSizeTolerance; | |
| 121 | ||
| 122 | } CODEC_VP9_ENCODE_SEQUENCE_PARAMS, *PCODEC_VP9_ENCODE_SEQUENCE_PARAMS; | |
| 123 | ||
| 124 | typedef struct _CODEC_VP9_ENCODE_PIC_PARAMS | |
| 125 | { | |
| 126 | uint16_t SrcFrameHeightMinus1; | |
| 127 | uint16_t SrcFrameWidthMinus1; | |
| 128 | uint16_t DstFrameHeightMinus1; | |
| 129 | uint16_t DstFrameWidthMinus1; | |
| 130 | ||
| 131 | CODEC_PICTURE CurrOriginalPic; | |
| 132 | CODEC_PICTURE CurrReconstructedPic; | |
| 133 | CODEC_PICTURE RefFrameList[8]; | |
| 134 | ||
| 135 | union | |
| 136 | { | |
| 137 | struct | |
| 138 | { | |
| 139 | uint32_t frame_type : 1; | |
| 140 | uint32_t show_frame : 1; | |
| 141 | uint32_t error_resilient_mode : 1; | |
| 142 | uint32_t intra_only : 1; | |
| 143 | uint32_t allow_high_precision_mv : 1; | |
| 144 | uint32_t mcomp_filter_type : 3; | |
| 145 | uint32_t frame_parallel_decoding_mode : 1; | |
| 146 | uint32_t segmentation_enabled : 1; | |
| 147 | uint32_t segmentation_temporal_update : 1; | |
| 148 | uint32_t segmentation_update_map : 1; | |
| 149 | uint32_t reset_frame_context : 2; | |
| 150 | uint32_t refresh_frame_context : 1; | |
| 151 | uint32_t frame_context_idx : 2; | |
| 152 | uint32_t LosslessFlag : 1; | |
| 153 | uint32_t comp_prediction_mode : 2; | |
| 154 | uint32_t super_frame : 1; | |
| 155 | uint32_t seg_id_block_size : 2; | |
| 156 | uint32_t seg_update_data : 1; | |
| 157 | uint32_t reserved : 8; | |
| 158 | } fields; | |
| 159 | ||
| 160 | uint32_t value; | |
| 161 | } PicFlags; | |
| 162 | ||
| 163 | union | |
| 164 | { | |
| 165 | struct | |
| 166 | { | |
| 167 | uint32_t LastRefIdx : 3; | |
| 168 | uint32_t LastRefSignBias : 1; | |
| 169 | uint32_t GoldenRefIdx : 3; | |
| 170 | uint32_t GoldenRefSignBias : 1; | |
| 171 | uint32_t AltRefIdx : 3; | |
| 172 | uint32_t AltRefSignBias : 1; | |
| 173 | ||
| 174 | uint32_t ref_frame_ctrl_l0 : 3; | |
| 175 | uint32_t ref_frame_ctrl_l1 : 3; | |
| 176 | ||
| 177 | uint32_t refresh_frame_flags : 8; | |
| 178 | uint32_t reserved2 : 6; | |
| 179 | } fields; | |
| 180 | ||
| 181 | uint32_t value; | |
| 182 | } RefFlags; | |
| 183 | ||
| 184 | uint8_t LumaACQIndex; | |
| 185 | char LumaDCQIndexDelta; | |
| 186 | char ChromaACQIndexDelta; | |
| 187 | char ChromaDCQIndexDelta; | |
| 188 | ||
| 189 | uint8_t filter_level; // This is not to be set for VP9 VDEnc (G10+), this is removed from DDI, only here to support legacy KBL DP | |
| 190 | uint8_t sharpness_level; // This is not to be set for VP9 VDEnc (G10+), this is removed from DDI, only here to support legacy KBL DP | |
| 191 | ||
| 192 | char LFRefDelta[4]; // This is not to be set for VP9 VDEnc (G10+), this is removed from DDI, only here to support legacy KBL DP | |
| 193 | char LFModeDelta[2]; // This is not to be set for VP9 VDEnc (G10+), this is removed from DDI, only here to support legacy KBL DP | |
| 194 | ||
| 195 | uint16_t BitOffsetForLFRefDelta; | |
| 196 | uint16_t BitOffsetForLFModeDelta; | |
| 197 | uint16_t BitOffsetForLFLevel; | |
| 198 | uint16_t BitOffsetForQIndex; | |
| 199 | uint16_t BitOffsetForFirstPartitionSize; | |
| 200 | uint16_t BitOffsetForSegmentation; | |
| 201 | uint16_t BitSizeForSegmentation; | |
| 202 | ||
| 203 | uint8_t log2_tile_rows; | |
| 204 | uint8_t log2_tile_columns; | |
| 205 | ||
| 206 | uint8_t temporal_id; | |
| 207 | ||
| 208 | uint32_t StatusReportFeedbackNumber; | |
| 209 | ||
| 210 | // Skip Frames | |
| 211 | uint8_t SkipFrameFlag; // [0..2] | |
| 212 | uint8_t NumSkipFrames; | |
| 213 | uint32_t SizeSkipFrames; | |
| 214 | } CODEC_VP9_ENCODE_PIC_PARAMS, *PCODEC_VP9_ENCODE_PIC_PARAMS; | |
| 215 | #endif |
| 19 | 19 | |
| 20 | 20 | # shared |
| 21 | 21 | set(TMP_2_HEADERS_ |
| 22 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_avc.h | |
| 23 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_encode.h | |
| 24 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_hevc.h | |
| 25 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_jpeg.h | |
| 26 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_mpeg2.h | |
| 27 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_common_vp9.h | |
| 28 | 22 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_vp8_probs.h |
| 29 | 23 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_vp9_probs.h |
| 30 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_avc.h | |
| 31 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_hevc.h | |
| 32 | 24 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_jpeg.h |
| 33 | 25 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_mpeg2.h |
| 34 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_vc1.h | |
| 35 | 26 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_vp8.h |
| 36 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_vp9.h | |
| 37 | 27 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode.h |
| 38 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode_avc.h | |
| 39 | 28 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode_hevc.h |
| 40 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode_jpeg.h | |
| 41 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode_mpeg2.h | |
| 42 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode_vp9.h | |
| 43 | 29 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode_vp8.h |
| 44 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_encode.h | |
| 45 | 30 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_cenc_decode.h |
| 46 | 31 | ) |
| 47 | 32 |
| 369 | 369 | &PatchEntryParams)); |
| 370 | 370 | } |
| 371 | 371 | |
| 372 | if (MOS_VEBOX_STATE == pParams->HwCommandType || | |
| 373 | MOS_VEBOX_DI_IECP == pParams->HwCommandType || | |
| 374 | MOS_VEBOX_TILING_CONVERT == pParams->HwCommandType || | |
| 375 | MOS_SFC_STATE == pParams->HwCommandType || | |
| 376 | MOS_STATE_BASE_ADDR == pParams->HwCommandType || | |
| 377 | MOS_SURFACE_STATE == pParams->HwCommandType || | |
| 378 | MOS_SURFACE_STATE_ADV == pParams->HwCommandType || | |
| 379 | MOS_MFX_PIPE_BUF_ADDR == pParams->HwCommandType || | |
| 380 | MOS_MFX_VP8_PIC == pParams->HwCommandType || | |
| 381 | MOS_MFX_BSP_BUF_BASE_ADDR == pParams->HwCommandType || | |
| 382 | MOS_MFX_INDIRECT_OBJ_BASE_ADDR == pParams->HwCommandType || | |
| 383 | MOS_MI_BATCH_BUFFER_START == pParams->HwCommandType) | |
| 384 | { | |
| 385 | HalOcaInterface::DumpResourceInfo(*pCmdBuffer, *pOsInterface, *pParams->presResource, pParams->HwCommandType, | |
| 386 | pParams->dwLocationInCmd, pParams->dwOffset); | |
| 387 | } | |
| 388 | ||
| 372 | 389 | finish: |
| 373 | 390 | return eStatus; |
| 374 | 391 | } |
| 98 | 98 | |
| 99 | 99 | typename TVeboxCmds::VEBOX_SURFACE_STATE_CMD cmd1, cmd2; |
| 100 | 100 | |
| 101 | MEDIA_FEATURE_TABLE *pSkuTable = nullptr; | |
| 102 | pSkuTable = m_osInterface->pfnGetSkuTable(m_osInterface); | |
| 103 | MHW_CHK_NULL(pSkuTable); | |
| 101 | 104 | MHW_CHK_NULL(pCmdBuffer); |
| 102 | 105 | MHW_CHK_NULL(pVeboxSurfaceStateCmdParams); |
| 103 | 106 | |
| 112 | 115 | &cmd1, |
| 113 | 116 | false, |
| 114 | 117 | pVeboxSurfaceStateCmdParams->bDIEnable); |
| 118 | ||
| 119 | if (pVeboxSurfaceStateCmdParams->b3DlutEnable && MEDIA_IS_SKU(pSkuTable, FtrHeight8AlignVE3DLUTDualPipe)) | |
| 120 | { | |
| 121 | cmd1.DW2.Height = MOS_ALIGN_CEIL((cmd1.DW2.Height + 1), 8) - 1; | |
| 122 | MHW_NORMALMESSAGE("Align Input Height as 8x due to 3DlutEnable"); | |
| 123 | } | |
| 124 | ||
| 115 | 125 | Mos_AddCommand(pCmdBuffer, &cmd1, cmd1.byteSize); |
| 116 | 126 | MHW_NORMALMESSAGE("Vebox input Height: %d, Width: %d;", cmd1.DW2.Height, cmd1.DW2.Width); |
| 117 | 127 | |
| 130 | 140 | if (pVeboxSurfaceStateCmdParams->SurfInput.Format == pVeboxSurfaceStateCmdParams->SurfOutput.Format) |
| 131 | 141 | { |
| 132 | 142 | cmd2.DW3.SurfaceFormat = cmd1.DW3.SurfaceFormat; |
| 143 | } | |
| 144 | ||
| 145 | if (pVeboxSurfaceStateCmdParams->b3DlutEnable && MEDIA_IS_SKU(pSkuTable, FtrHeight8AlignVE3DLUTDualPipe)) | |
| 146 | { | |
| 147 | cmd2.DW2.Height = MOS_ALIGN_CEIL((cmd2.DW2.Height + 1), 8) - 1; | |
| 148 | MHW_NORMALMESSAGE("Align Output Height as 8x due to 3DlutEnable"); | |
| 133 | 149 | } |
| 134 | 150 | |
| 135 | 151 | Mos_AddCommand(pCmdBuffer, &cmd2, cmd2.byteSize); |
| 25 | 25 | ) |
| 26 | 26 | |
| 27 | 27 | set(TMP_HEADERS_ |
| 28 | ${CMAKE_CURRENT_LIST_DIR}/mhw_vdbox.h | |
| 29 | 28 | ${CMAKE_CURRENT_LIST_DIR}/mhw_vdbox_hcp_generic.h |
| 30 | 29 | ${CMAKE_CURRENT_LIST_DIR}/mhw_vdbox_hcp_interface.h |
| 31 | 30 | ${CMAKE_CURRENT_LIST_DIR}/mhw_vdbox_huc_generic.h |
| 0 | /* | |
| 1 | * Copyright (c) 2014-2020, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file mhw_vdbox.h | |
| 23 | //! \brief This modules implements HW interface layer to be used on all platforms on all operating systems/DDIs, across MHW components. | |
| 24 | //! | |
| 25 | #ifndef _MHW_VDBOX_H_ | |
| 26 | #define _MHW_VDBOX_H_ | |
| 27 | ||
| 28 | #include "codec_def_encode_avc.h" | |
| 29 | #include "codec_def_encode_jpeg.h" | |
| 30 | #include "codec_def_encode_mpeg2.h" | |
| 31 | #include "codec_def_encode_vp9.h" | |
| 32 | #include "codec_def_decode_vp9.h" | |
| 33 | #include "codec_def_decode_vc1.h" | |
| 34 | #include "codec_def_decode_avc.h" | |
| 35 | #include "codec_def_decode_hevc.h" | |
| 36 | #include "mos_os.h" | |
| 37 | #include "mhw_utilities.h" | |
| 38 | #include "mhw_cp_interface.h" | |
| 39 | ||
| 40 | #define MHW_VDBOX_VC1_BITPLANE_BUFFER_PITCH_SMALL 64 | |
| 41 | #define MHW_VDBOX_VC1_BITPLANE_BUFFER_PITCH_LARGE 128 | |
| 42 | ||
| 43 | #define MHW_VDBOX_MFX_RAW_UV_PLANE_ALIGNMENT_GEN9 4 // starting Gen9 the alignment is relaxed to 4x instead of 16x | |
| 44 | #define MHW_VDBOX_MFX_UV_PLANE_ALIGNMENT_LEGACY 16 | |
| 45 | #define MHW_VDBOX_MFX_RECON_UV_PLANE_ALIGNMENT 16 | |
| 46 | #define MHW_VDBOX_HCP_RAW_UV_PLANE_ALIGNMENT 4 // starting Gen9 the alignment is relaxed to 4x instead of 16x | |
| 47 | #define MHW_VDBOX_HCP_RECON_UV_PLANE_ALIGNMENT 8 | |
| 48 | ||
| 49 | #define MHW_VDBOX_PAK_BITSTREAM_OVERFLOW_SIZE 400 | |
| 50 | #define MHW_VDBOX_PAK_SLICE_HEADER_OVERFLOW_SIZE 50 | |
| 51 | #define MHW_VDBOX_VDENC_DYNAMIC_SLICE_WA_COUNT 1500 | |
| 52 | ||
| 53 | // Rowstore Cache values | |
| 54 | #define MHW_VDBOX_PICWIDTH_1K 1024 | |
| 55 | #define MHW_VDBOX_PICWIDTH_2K 2048 | |
| 56 | #define MHW_VDBOX_PICWIDTH_3K 3072 | |
| 57 | #define MHW_VDBOX_PICWIDTH_4K 4096 | |
| 58 | #define MHW_VDBOX_PICWIDTH_8K 8192 | |
| 59 | #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 256 | |
| 60 | #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 384 | |
| 61 | #define INTRAROWSTORE_MBAFF_BASEADDRESS_PICWIDTH_LESS_THAN_2K 512 | |
| 62 | #define INTRAROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_3K_AND_4K 384 | |
| 63 | #define DEBLOCKINGROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 384 | |
| 64 | #define BSDMPCROWSTORE_BASEADDRESS 0 | |
| 65 | #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_LESS_THAN_2K 128 | |
| 66 | #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 192 | |
| 67 | #define MPRROWSTORE_FRAME_FIELD_BASEADDRESS_PICWIDTH_GREATER_THAN_3K 256 | |
| 68 | #define MPRROWSTORE_MBAFF_BASEADDRESS_PICWIDTH_LESS_THAN_2K 256 | |
| 69 | #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_LESS_THAN_2K 128 | |
| 70 | #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_3K 192 | |
| 71 | #define VDENCROWSTORE_FRAME_BASEADDRESS_PICWIDTH_BETWEEN_3K_AND_4K 256 | |
| 72 | #define HEVCDATROWSTORE_BASEADDRESS 0 | |
| 73 | #define HEVCDFROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 64 | |
| 74 | #define HEVCDFROWSTORE_BASEADDRESS_PICWIDTH_BETWEEN_2K_AND_4K 128 | |
| 75 | #define HEVCSAOROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 320 | |
| 76 | #define VP9HVDROWSTORE_BASEADDRESS 0 | |
| 77 | #define VP9DFROWSTORE_BASEADDRESS_PICWIDTH_LESS_THAN_OR_EQU_TO_2K 32 | |
| 78 | #define MHW_CACHELINE_SIZE 64 | |
| 79 | #define BYTES_PER_DWORD 4 | |
| 80 | #define NUM_PAK_DWS_PER_LCU 5 | |
| 81 | #define NUM_DWS_PER_CU 8 | |
| 82 | ||
| 83 | #define VP9DFROWSTORE_BASEADDRESS_8BIT_PICWIDTH_LESS_THAN_OR_EQU_TO_4K 384 | |
| 84 | #define VP9DATROWSTORE_BASEADDRESS_8BIT_PICWIDTH_LESS_THAN_OR_EQU_TO_4K 64 | |
| 85 | ||
| 86 | typedef enum _MHW_VDBOX_ADDRESS_SHIFT | |
| 87 | { | |
| 88 | MHW_VDBOX_SURFACE_STATE_SHIFT = 0, | |
| 89 | MHW_VDBOX_MFX_GENERAL_STATE_SHIFT = 6, | |
| 90 | MHW_VDBOX_HCP_GENERAL_STATE_SHIFT = 6, | |
| 91 | MHW_VDBOX_HUC_GENERAL_STATE_SHIFT = 6, | |
| 92 | MHW_VDBOX_MFX_UPPER_BOUND_STATE_SHIFT = 12, | |
| 93 | MHW_VDBOX_STATE_BASE_ADDRESS_SHIFT = 12, | |
| 94 | MHW_VDBOX_HCP_UPPER_BOUND_STATE_SHIFT = 12, | |
| 95 | MHW_VDBOX_HUC_UPPER_BOUND_STATE_SHIFT = 12, | |
| 96 | MHW_VDBOX_HUC_IMEM_STATE_SHIFT = 15, | |
| 97 | MHW_VDBOX_HCP_DECODED_BUFFER_SHIFT = 12 | |
| 98 | } MHW_VDBOX_ADDRESS_SHIFT; | |
| 99 | ||
| 100 | typedef enum _MHW_VDBOX_NODE_IND | |
| 101 | { | |
| 102 | MHW_VDBOX_NODE_1 = 0x0, | |
| 103 | MHW_VDBOX_NODE_2 = 0x1, | |
| 104 | MHW_VDBOX_NODE_MAX | |
| 105 | } MHW_VDBOX_NODE_IND; | |
| 106 | ||
| 107 | typedef struct _MHW_VDBOX_AVC_QM_PARAMS | |
| 108 | { | |
| 109 | uint8_t List4x4[6][16]; | |
| 110 | uint8_t List8x8[2][64]; | |
| 111 | } MHW_VDBOX_AVC_QM_PARAMS, *PMHW_VDBOX_AVC_QM_PARAMS; | |
| 112 | ||
| 113 | typedef struct _MHW_VDBOX_HEVC_QM_PARAMS | |
| 114 | { | |
| 115 | uint8_t List4x4[6][16]; | |
| 116 | uint8_t List8x8[6][64]; | |
| 117 | uint8_t List16x16[6][64]; | |
| 118 | uint8_t List32x32[2][64]; | |
| 119 | uint8_t ListDC16x16[6]; | |
| 120 | uint8_t ListDC32x32[2]; | |
| 121 | } MHW_VDBOX_HEVC_QM_PARAMS, *PMHW_VDBOX_HEVC_QM_PARAMS; | |
| 122 | ||
| 123 | typedef enum _HCP_SURFACE_FORMAT | |
| 124 | { | |
| 125 | HCP_SURFACE_FORMAT_YUY2 = 0x0, | |
| 126 | HCP_SURFACE_FORMAT_RGBX8888 = 0x1, | |
| 127 | HCP_SURFACE_FORMAT_AYUV4444 = 0x2, | |
| 128 | HCP_SURFACE_FORMAT_P010_VARIANT = 0x3, | |
| 129 | HCP_SURFACE_FORMAT_PLANAR_420_8 = 0x4, | |
| 130 | HCP_SURFACE_FORMAT_UYVY = 0x5, | |
| 131 | HCP_SURFACE_FORMAT_YVYU = 0x6, | |
| 132 | HCP_SURFACE_FORMAT_VYUY = 0x7, | |
| 133 | HCP_SURFACE_FORMAT_Y210 = 0x8, | |
| 134 | HCP_SURFACE_FORMAT_Y216 = 0x8, | |
| 135 | HCP_SURFACE_FORMAT_RGBA1010102 = 0x9, | |
| 136 | HCP_SURFACE_FORMAT_Y410 = 0xA, | |
| 137 | HCP_SURFACE_FORMAT_NV21 = 0xB, | |
| 138 | HCP_SURFACE_FORMAT_Y416 = 0xC, | |
| 139 | HCP_SURFACE_FORMAT_P010 = 0xD, | |
| 140 | HCP_SURFACE_FORMAT_P016 = 0xE, | |
| 141 | HCP_SURFACE_FORMAT_Y8 = 0xF, | |
| 142 | HCP_SURFACE_FORMAT_Y16 = 0x10, | |
| 143 | HCP_SURFACE_FORMAT_Y216_VARIANT = 0x11, | |
| 144 | HCP_SURFACE_FORMAT_Y416_VARIANT = 0x12, | |
| 145 | HCP_SURFACE_FORMAT_YUYV_VARIANT = 0x13, | |
| 146 | HCP_SURFACE_FORMAT_AYUV4444_VARIANT = 0x14, | |
| 147 | HCP_SURFACE_FORMAT_RESERVED = 0x15, | |
| 148 | } HCP_SURFACE_FORMAT; | |
| 149 | ||
| 150 | typedef enum _PIPE_WORK_MODE | |
| 151 | { | |
| 152 | MHW_VDBOX_HCP_PIPE_WORK_MODE_LEGACY = 0, | |
| 153 | MHW_VDBOX_HCP_PIPE_WORK_MODE_CABAC_FE = 1, | |
| 154 | MHW_VDBOX_HCP_PIPE_WORK_MODE_CODEC_BE = 2, | |
| 155 | MHW_VDBOX_HCP_PIPE_WORK_MODE_CABAC_REAL_TILE = 3, | |
| 156 | }MHW_VDBOX_HCP_PIPE_WORK_MODE; | |
| 157 | ||
| 158 | typedef enum _MULTI_ENGINE_MODE | |
| 159 | { | |
| 160 | MHW_VDBOX_HCP_MULTI_ENGINE_MODE_FE_LEGACY = 0, | |
| 161 | MHW_VDBOX_HCP_MULTI_ENGINE_MODE_LEFT = 1, | |
| 162 | MHW_VDBOX_HCP_MULTI_ENGINE_MODE_RIGHT = 2, | |
| 163 | MHW_VDBOX_HCP_MULTI_ENGINE_MODE_MIDDLE = 3, | |
| 164 | }MHW_VDBOX_HCP_MULTI_ENGINE_MODE; | |
| 165 | ||
| 166 | typedef enum | |
| 167 | { | |
| 168 | MHW_VDBOX_HCP_RT_FIRST_PHASE = 0, //!< First phase | |
| 169 | MHW_VDBOX_HCP_RT_MIDDLE_PHASE = 1, //!< Middle phase | |
| 170 | MHW_VDBOX_HCP_RT_LAST_PHASE = 2 //!< Last phase | |
| 171 | } MHW_HCP_RT_PHASE_INDICATOR; | |
| 172 | ||
| 173 | typedef enum _VDENC_PIPE_NUM_OF_PIPE | |
| 174 | { | |
| 175 | VDENC_PIPE_SINGLE_PIPE = 0, | |
| 176 | VDENC_PIPE_TWO_PIPE = 1, | |
| 177 | VDENC_PIPE_INVALID = 2, | |
| 178 | VDENC_PIPE_FOUR_PIPE = 3, | |
| 179 | }VDENC_PIPE_NUM_OF_PIPE; | |
| 180 | ||
| 181 | typedef enum | |
| 182 | { | |
| 183 | HCP_CHROMA_FORMAT_MONOCHROME = 0, | |
| 184 | HCP_CHROMA_FORMAT_YUV420 = 1, | |
| 185 | HCP_CHROMA_FORMAT_YUV422 = 2, | |
| 186 | HCP_CHROMA_FORMAT_YUV444 = 3 | |
| 187 | } HCP_CHROMA_FORMAT_IDC; | |
| 188 | ||
| 189 | // Media memory compression trigger | |
| 190 | typedef enum _MHW_MEDIA_MEMORY_COMPRESSION_EN | |
| 191 | { | |
| 192 | MHW_MEDIA_MEMCOMP_DISABLED = 0x0, | |
| 193 | MHW_MEDIA_MEMCOMP_ENABLED = 0x1 | |
| 194 | } MHW_MEDIA_MEMORY_COMPRESSION_EN; | |
| 195 | ||
| 196 | // Media memory compression mode | |
| 197 | typedef enum _MHW_MEDIA_MEMORY_COMPRESSION_MODE | |
| 198 | { | |
| 199 | MHW_MEDIA_MEMCOMP_MODE_HORIZONTAL = 0x0, | |
| 200 | MHW_MEDIA_MEMCOMP_MODE_VERTICAL = 0x1, | |
| 201 | } MHW_MEDIA_MEMORY_COMPRESSION_MODE; | |
| 202 | ||
| 203 | //! | |
| 204 | //! \enum ROWSTORE_SCRATCH_BUFFER_CACHE | |
| 205 | //! \brief Rowstore scratch buffer cache select | |
| 206 | //! | |
| 207 | enum ROWSTORE_SCRATCH_BUFFER_CACHE | |
| 208 | { | |
| 209 | BUFFER_TO_LLC = 0x0, | |
| 210 | BUFFER_TO_INTERNALMEDIASTORAGE = 0x1 | |
| 211 | }; | |
| 212 | ||
| 213 | struct MHW_VDBOX_PIPE_MODE_SELECT_PARAMS | |
| 214 | { | |
| 215 | uint32_t Mode = 0; | |
| 216 | bool bStreamOutEnabled = false; | |
| 217 | bool bStreamOutEnabledExtEnabled = false; | |
| 218 | bool bShortFormatInUse = false; | |
| 219 | bool bVC1OddFrameHeight = false; | |
| 220 | bool pakFrmLvlStrmoutEnable = false; | |
| 221 | bool pakPiplnStrmoutEnabled = false; | |
| 222 | ||
| 223 | bool bDeblockerStreamOutEnable = false; | |
| 224 | bool bPostDeblockOutEnable = false; | |
| 225 | bool bPreDeblockOutEnable = false; | |
| 226 | bool bDynamicSliceEnable = false; | |
| 227 | bool bSaoFirstPass = false; | |
| 228 | bool bRdoqEnable = false; | |
| 229 | bool bDynamicScalingEnabled = false; | |
| 230 | ||
| 231 | // VDEnc specific | |
| 232 | bool bVdencEnabled = false; | |
| 233 | bool bVdencStreamInEnable = false; | |
| 234 | uint8_t ucVdencBitDepthMinus8 = 0; | |
| 235 | bool bPakThresholdCheckEnable = false; | |
| 236 | bool bVdencPakObjCmdStreamOutEnable = false; | |
| 237 | bool bBatchBufferInUse = false; | |
| 238 | bool bTlbPrefetchEnable = 0; | |
| 239 | PMHW_BATCH_BUFFER pBatchBuffer = nullptr; | |
| 240 | uint32_t ChromaType = 0; | |
| 241 | MOS_FORMAT Format = {}; | |
| 242 | bool isIFrame = false; | |
| 243 | bool bIBCEnabled = false; | |
| 244 | ||
| 245 | // HuC specific | |
| 246 | uint32_t dwMediaSoftResetCounterValue = 0; | |
| 247 | bool bAdvancedRateControlEnable = false; | |
| 248 | bool bStreamObjectUsed = false; | |
| 249 | // No need to set protection settings | |
| 250 | bool disableProtectionSetting = false; | |
| 251 | virtual ~MHW_VDBOX_PIPE_MODE_SELECT_PARAMS() {} | |
| 252 | }; | |
| 253 | using PMHW_VDBOX_PIPE_MODE_SELECT_PARAMS = MHW_VDBOX_PIPE_MODE_SELECT_PARAMS * ; | |
| 254 | ||
| 255 | typedef struct _MHW_VDBOX_SURFACE_PARAMS | |
| 256 | { | |
| 257 | uint32_t Mode; | |
| 258 | PMOS_SURFACE psSurface; // 2D surface parameters | |
| 259 | uint8_t ucVDirection; | |
| 260 | uint8_t ChromaType; | |
| 261 | uint8_t ucSurfaceStateId; | |
| 262 | uint8_t ucBitDepthLumaMinus8; | |
| 263 | uint8_t ucBitDepthChromaMinus8; | |
| 264 | uint32_t dwUVPlaneAlignment; | |
| 265 | bool bDisplayFormatSwizzle; | |
| 266 | bool bSrc8Pak10Mode; | |
| 267 | bool bColorSpaceSelection; | |
| 268 | bool bVdencDynamicScaling; | |
| 269 | uint32_t dwActualWidth; | |
| 270 | uint32_t dwActualHeight; | |
| 271 | uint32_t dwReconSurfHeight; | |
| 272 | MOS_MEMCOMP_STATE mmcState; | |
| 273 | uint8_t mmcSkipMask; | |
| 274 | uint32_t dwCompressionFormat; | |
| 275 | } MHW_VDBOX_SURFACE_PARAMS, *PMHW_VDBOX_SURFACE_PARAMS; | |
| 276 | ||
| 277 | struct MHW_VDBOX_PIPE_BUF_ADDR_PARAMS | |
| 278 | { | |
| 279 | uint32_t Mode = 0; | |
| 280 | PMOS_SURFACE psPreDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface | |
| 281 | MOS_MEMCOMP_STATE PreDeblockSurfMmcState = MOS_MEMCOMP_DISABLED; | |
| 282 | PMOS_SURFACE psPostDeblockSurface = nullptr; // Pointer to MOS_SURFACE of render surface | |
| 283 | MOS_MEMCOMP_STATE PostDeblockSurfMmcState = MOS_MEMCOMP_DISABLED; | |
| 284 | PMOS_SURFACE psRawSurface = nullptr; // Pointer to MOS_SURFACE of raw surface | |
| 285 | MOS_MEMCOMP_STATE RawSurfMmcState = MOS_MEMCOMP_DISABLED; | |
| 286 | PMOS_SURFACE ps4xDsSurface = nullptr; | |
| 287 | MOS_MEMCOMP_STATE Ps4xDsSurfMmcState = MOS_MEMCOMP_DISABLED; | |
| 288 | PMOS_SURFACE ps8xDsSurface = nullptr; | |
| 289 | MOS_MEMCOMP_STATE Ps8xDsSurfMmcState = MOS_MEMCOMP_DISABLED; | |
| 290 | PMOS_RESOURCE presDataBuffer = nullptr; // Handle of residual difference surface | |
| 291 | PMOS_RESOURCE presReferences[CODEC_MAX_NUM_REF_FRAME] = {}; | |
| 292 | PMOS_RESOURCE presMfdIntraRowStoreScratchBuffer = nullptr; // Handle of MFD Intra Row Store Scratch data surface | |
| 293 | PMOS_RESOURCE presMfdDeblockingFilterRowStoreScratchBuffer = nullptr; // Handle of MFD Deblocking Filter Row Store Scratch data surface | |
| 294 | PMOS_RESOURCE presStreamOutBuffer = nullptr; | |
| 295 | MOS_MEMCOMP_STATE StreamOutBufMmcState = MOS_MEMCOMP_DISABLED; | |
| 296 | PMOS_RESOURCE presMacroblockIldbStreamOutBuffer1 = nullptr; | |
| 297 | PMOS_RESOURCE presMacroblockIldbStreamOutBuffer2 = nullptr; | |
| 298 | PMOS_RESOURCE presSliceSizeStreamOutBuffer = nullptr; | |
| 299 | PMOS_SURFACE psFwdRefSurface0 = nullptr; | |
| 300 | PMOS_SURFACE psFwdRefSurface1 = nullptr; | |
| 301 | PMOS_SURFACE psFwdRefSurface2 = nullptr; | |
| 302 | bool bDynamicScalingEnable = false; | |
| 303 | ||
| 304 | PMOS_RESOURCE presVdencIntraRowStoreScratchBuffer = nullptr; // For VDEnc, Handle of VDEnc Intra Row Store Scratch data surface | |
| 305 | PMOS_RESOURCE presVdencTileRowStoreBuffer = nullptr; | |
| 306 | PMOS_RESOURCE presVdencStreamOutBuffer = nullptr; | |
| 307 | PMOS_RESOURCE presVdencCuObjStreamOutBuffer = nullptr; | |
| 308 | PMOS_RESOURCE presVdencPakObjCmdStreamOutBuffer = nullptr; | |
| 309 | PMOS_RESOURCE presVdencStreamInBuffer = nullptr; | |
| 310 | PMOS_RESOURCE presVdencReferences[CODEC_MAX_NUM_REF_FRAME] = {}; | |
| 311 | PMOS_RESOURCE presVdenc4xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {}; | |
| 312 | PMOS_RESOURCE presVdenc8xDsSurface[CODEC_MAX_NUM_REF_FRAME] = {}; | |
| 313 | ||
| 314 | PMOS_RESOURCE presVdencColocatedMVWriteBuffer = nullptr; // For AVC only | |
| 315 | PMOS_RESOURCE presVdencColocatedMVReadBuffer = nullptr; // For AVC only | |
| 316 | PMOS_RESOURCE presDeblockingFilterTileRowStoreScratchBuffer = nullptr; // For HEVC, VP9 | |
| 317 | PMOS_RESOURCE presDeblockingFilterColumnRowStoreScratchBuffer = nullptr; // For HEVC, VP9 | |
| 318 | PMOS_RESOURCE presMetadataLineBuffer = nullptr; // For HEVC, VP9 | |
| 319 | PMOS_RESOURCE presMetadataTileLineBuffer = nullptr; // For HEVC, VP9 | |
| 320 | PMOS_RESOURCE presMetadataTileColumnBuffer = nullptr; // For HEVC, VP9 | |
| 321 | PMOS_RESOURCE presSaoLineBuffer = nullptr; // For HEVC only | |
| 322 | PMOS_RESOURCE presSaoTileLineBuffer = nullptr; // For HEVC only | |
| 323 | PMOS_RESOURCE presSaoTileColumnBuffer = nullptr; // For HEVC only | |
| 324 | PMOS_RESOURCE presCurMvTempBuffer = nullptr; // For HEVC, VP9 | |
| 325 | PMOS_RESOURCE presColMvTempBuffer[CODEC_MAX_NUM_REF_FRAME] = {}; // For HEVC, VP9 | |
| 326 | PMOS_RESOURCE presLcuBaseAddressBuffer = nullptr; // For HEVC only | |
| 327 | PMOS_RESOURCE presLcuILDBStreamOutBuffer = nullptr; // For HEVC only | |
| 328 | PMOS_RESOURCE presVp9ProbBuffer = nullptr; // For VP9 only | |
| 329 | PMOS_RESOURCE presVp9SegmentIdBuffer = nullptr; // For VP9 only | |
| 330 | PMOS_RESOURCE presHvdLineRowStoreBuffer = nullptr; // For VP9 only | |
| 331 | PMOS_RESOURCE presHvdTileRowStoreBuffer = nullptr; // For VP9 only | |
| 332 | PMOS_RESOURCE presSaoStreamOutBuffer = nullptr; // For HEVC only | |
| 333 | PMOS_RESOURCE presSaoRowStoreBuffer = nullptr; // For HEVC only | |
| 334 | PMOS_SURFACE presP010RTSurface = nullptr; // For HEVC only | |
| 335 | PMOS_RESOURCE presFrameStatStreamOutBuffer = nullptr; | |
| 336 | PMOS_RESOURCE presSseSrcPixelRowStoreBuffer = nullptr; | |
| 337 | PMOS_RESOURCE presSegmentMapStreamIn = nullptr; | |
| 338 | PMOS_RESOURCE presSegmentMapStreamOut = nullptr; | |
| 339 | PMOS_RESOURCE presPakCuLevelStreamoutBuffer = nullptr; | |
| 340 | PMHW_VDBOX_SURFACE_PARAMS pRawSurfParam = nullptr; | |
| 341 | PMHW_VDBOX_SURFACE_PARAMS pDecodedReconParam = nullptr; | |
| 342 | bool bVdencEnabled = false; | |
| 343 | bool bRawIs10Bit = false; | |
| 344 | bool bDecodecReconIs10Bit = false; | |
| 345 | uint32_t dwNumRefIdxL0ActiveMinus1 = 0; | |
| 346 | uint32_t dwNumRefIdxL1ActiveMinus1 = 0; | |
| 347 | uint32_t dwLcuStreamOutOffset = 0; | |
| 348 | uint32_t dwFrameStatStreamOutOffset = 0; | |
| 349 | uint32_t dwVdencStatsStreamOutOffset = 0; | |
| 350 | bool oneOnOneMapping = false; // Flag for indicating using 1:1 ref index mapping for vdenc | |
| 351 | bool isLowDelayB = true; // Flag to indicate if it is LDB | |
| 352 | bool isIFrame = false; // Flag to indicate if it is I frame | |
| 353 | bool isPFrame = false; // Flag to indicate if it is P frame | |
| 354 | bool bIBCEnabled = false; | |
| 355 | uint8_t IBCRefIdxMask = 0; | |
| 356 | PMOS_RESOURCE presVdencCumulativeCuCountStreamoutSurface = nullptr; | |
| 357 | virtual ~MHW_VDBOX_PIPE_BUF_ADDR_PARAMS() {} | |
| 358 | }; | |
| 359 | using PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS = MHW_VDBOX_PIPE_BUF_ADDR_PARAMS * ; | |
| 360 | ||
| 361 | typedef struct _MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS | |
| 362 | { | |
| 363 | uint32_t Mode; | |
| 364 | PMOS_RESOURCE presDataBuffer; | |
| 365 | uint32_t dwDataSize; | |
| 366 | uint32_t dwDataOffset; | |
| 367 | PMOS_RESOURCE presMvObjectBuffer; | |
| 368 | uint32_t dwMvObjectSize; | |
| 369 | uint32_t dwMvObjectOffset; | |
| 370 | PMOS_RESOURCE presPakBaseObjectBuffer; | |
| 371 | uint32_t dwPakBaseObjectSize; | |
| 372 | uint32_t dwPakBaseObjectOffset; | |
| 373 | PMOS_RESOURCE presPakTileSizeStasBuffer; | |
| 374 | uint32_t dwPakTileSizeStasBufferSize; | |
| 375 | uint32_t dwPakTileSizeRecordOffset; | |
| 376 | // used by VP9 | |
| 377 | PMOS_RESOURCE presCompressedHeaderBuffer; | |
| 378 | uint32_t dwCompressedHeaderSize; | |
| 379 | PMOS_RESOURCE presProbabilityDeltaBuffer; | |
| 380 | uint32_t dwProbabilityDeltaSize; | |
| 381 | PMOS_RESOURCE presProbabilityCounterBuffer; | |
| 382 | uint32_t dwProbabilityCounterOffset; | |
| 383 | uint32_t dwProbabilityCounterSize; | |
| 384 | PMOS_RESOURCE presTileRecordBuffer; | |
| 385 | uint32_t dwTileRecordSize; | |
| 386 | PMOS_RESOURCE presCuStatsBuffer; | |
| 387 | uint32_t dwCuStatsSize; | |
| 388 | ||
| 389 | PMOS_RESOURCE presStreamOutObjectBuffer; | |
| 390 | uint32_t dwStreamOutObjectSize; | |
| 391 | uint32_t dwStreamOutObjectOffset; | |
| 392 | } MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS, *PMHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS; | |
| 393 | ||
| 394 | struct MHW_VDBOX_AVC_IMG_PARAMS | |
| 395 | { | |
| 396 | // Decoding Params | |
| 397 | PCODEC_AVC_PIC_PARAMS pAvcPicParams = nullptr; | |
| 398 | PCODEC_MVC_EXT_PIC_PARAMS pMvcExtPicParams = nullptr; | |
| 399 | uint8_t ucActiveFrameCnt = 0; | |
| 400 | // Encoding Params | |
| 401 | PCODEC_AVC_ENCODE_SEQUENCE_PARAMS pEncodeAvcSeqParams = nullptr; | |
| 402 | PCODEC_AVC_ENCODE_PIC_PARAMS pEncodeAvcPicParams = nullptr; | |
| 403 | PCODEC_AVC_ENCODE_SLICE_PARAMS pEncodeAvcSliceParams = nullptr; | |
| 404 | PCODEC_REF_LIST *ppRefList = nullptr; | |
| 405 | CODEC_PIC_ID *pPicIdx = nullptr; | |
| 406 | uint32_t dwTqEnabled = 0; | |
| 407 | uint32_t dwTqRounding = 0; | |
| 408 | uint32_t dwMaxVmvR = 0; | |
| 409 | uint16_t wPicWidthInMb = 0; | |
| 410 | uint16_t wPicHeightInMb = 0; | |
| 411 | uint16_t wSlcHeightInMb = 0; | |
| 412 | uint8_t ucKernelMode = 0; // normal, performance, quality. | |
| 413 | ||
| 414 | //FEI multiple passes PAK ---max frame size | |
| 415 | uint16_t currPass = 0; | |
| 416 | uint8_t *pDeltaQp = nullptr; | |
| 417 | uint32_t dwMaxFrameSize = 0; | |
| 418 | ||
| 419 | bool bIPCMPass = false; | |
| 420 | // VDEnc specific | |
| 421 | bool bVdencEnabled = false; | |
| 422 | bool bVDEncPerfModeEnabled = false; | |
| 423 | bool bVdencStreamInEnabled = false; | |
| 424 | bool bVdencBRCEnabled = false; | |
| 425 | bool bSliceSizeStreamOutEnabled = false; | |
| 426 | bool bCrePrefetchEnable = false; | |
| 427 | bool bPerMBStreamOut = false; | |
| 428 | bool bRollingIRestrictFracCand = false; | |
| 429 | ||
| 430 | uint32_t dwMbSlcThresholdValue = 0; // For VDENC dynamic slice size control | |
| 431 | uint32_t dwVdencSliceMinusBytes = 0; | |
| 432 | uint8_t *pVDEncModeCost = nullptr; | |
| 433 | uint8_t *pVDEncMvCost = nullptr; | |
| 434 | uint8_t *pVDEncHmeMvCost = nullptr; | |
| 435 | uint32_t biWeight = 0; | |
| 436 | virtual ~MHW_VDBOX_AVC_IMG_PARAMS(){} | |
| 437 | }; | |
| 438 | using PMHW_VDBOX_AVC_IMG_PARAMS = MHW_VDBOX_AVC_IMG_PARAMS * ; | |
| 439 | ||
| 440 | typedef struct _MHW_VDBOX_QM_PARAMS | |
| 441 | { | |
| 442 | uint32_t Standard; | |
| 443 | uint32_t Mode; | |
| 444 | PMHW_VDBOX_AVC_QM_PARAMS pAvcIqMatrix; | |
| 445 | CodecMpeg2IqMatrix *pMpeg2IqMatrix; | |
| 446 | CodecJpegQuantMatrix *pJpegQuantMatrix; | |
| 447 | uint32_t JpegQMTableSelector; | |
| 448 | bool bJpegQMRotation; | |
| 449 | PMHW_VDBOX_HEVC_QM_PARAMS pHevcIqMatrix; | |
| 450 | } MHW_VDBOX_QM_PARAMS, *PMHW_VDBOX_QM_PARAMS; | |
| 451 | ||
| 452 | typedef struct _MHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS | |
| 453 | { | |
| 454 | uint32_t uiList; | |
| 455 | uint32_t uiLumaLogWeightDenom; | |
| 456 | uint32_t uiChromaLogWeightDenom; | |
| 457 | uint32_t uiLumaWeightFlag; | |
| 458 | uint32_t uiChromaWeightFlag; | |
| 459 | uint32_t uiNumRefForList; | |
| 460 | int16_t Weights[2][32][3][2]; | |
| 461 | PCODEC_AVC_ENCODE_PIC_PARAMS pAvcPicParams; | |
| 462 | } MHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS, *PMHW_VDBOX_AVC_WEIGHTOFFSET_PARAMS; | |
| 463 | ||
| 464 | typedef struct _MHW_VDBOX_PAK_INSERT_PARAMS | |
| 465 | { | |
| 466 | PBSBuffer pBsBuffer; | |
| 467 | // also reuse dwBitSize for passing SrcDataEndingBitInclusion when (pEncoder->bLastPicInStream || pEncoder->bLastPicInSeq) | |
| 468 | uint32_t dwBitSize; | |
| 469 | uint32_t dwOffset; | |
| 470 | uint32_t uiSkipEmulationCheckCount; | |
| 471 | bool bLastPicInSeq; | |
| 472 | bool bLastPicInStream; | |
| 473 | bool bLastHeader; | |
| 474 | bool bEmulationByteBitsInsert; | |
| 475 | bool bSetLastPicInStreamData; | |
| 476 | bool bSliceHeaderIndicator; | |
| 477 | bool bHeaderLengthExcludeFrmSize; | |
| 478 | uint32_t *pdwMpeg2PicHeaderTotalBufferSize; | |
| 479 | uint32_t *pdwMpeg2PicHeaderDataStartOffset; | |
| 480 | bool bResetBitstreamStartingPos; | |
| 481 | bool bEndOfSlice; | |
| 482 | uint32_t dwLastPicInSeqData; | |
| 483 | uint32_t dwLastPicInStreamData; | |
| 484 | PMHW_BATCH_BUFFER pBatchBufferForPakSlices; | |
| 485 | bool bVdencInUse; | |
| 486 | } MHW_VDBOX_PAK_INSERT_PARAMS, *PMHW_VDBOX_PAK_INSERT_PARAMS; | |
| 487 | ||
| 488 | typedef struct _MHW_VDBOX_VP9_SEGMENT_STATE | |
| 489 | { | |
| 490 | uint32_t Mode; | |
| 491 | PCODEC_VP9_SEGMENT_PARAMS pVp9SegmentParams; | |
| 492 | PCODEC_VP9_ENCODE_SEGMENT_PARAMS pVp9EncodeSegmentParams; | |
| 493 | uint8_t ucCurrentSegmentId; | |
| 494 | uint8_t ucQPIndexLumaAC; | |
| 495 | const uint8_t *pcucLfQpLookup; | |
| 496 | uint8_t *pbSegStateBufferPtr; | |
| 497 | } MHW_VDBOX_VP9_SEGMENT_STATE, *PMHW_VDBOX_VP9_SEGMENT_STATE; | |
| 498 | ||
| 499 | typedef struct _MHW_VDBOX_HCP_BSD_PARAMS | |
| 500 | { | |
| 501 | uint32_t dwBsdDataLength; | |
| 502 | uint32_t dwBsdDataStartOffset; | |
| 503 | } MHW_VDBOX_HCP_BSD_PARAMS, *PMHW_VDBOX_HCP_BSD_PARAMS; | |
| 504 | ||
| 505 | typedef struct _MHW_VDBOX_ROWSTORE_PARAMS | |
| 506 | { | |
| 507 | uint32_t Mode; | |
| 508 | uint32_t dwPicWidth; | |
| 509 | uint32_t bMbaff; | |
| 510 | bool bIsFrame; | |
| 511 | uint8_t ucBitDepthMinus8; | |
| 512 | uint8_t ucChromaFormat; | |
| 513 | uint8_t ucLCUSize; | |
| 514 | } MHW_VDBOX_ROWSTORE_PARAMS, *PMHW_VDBOX_ROWSTORE_PARAMS; | |
| 515 | ||
| 516 | typedef struct _MHW_VDBOX_ROWSTORE_CACHE | |
| 517 | { | |
| 518 | bool bSupported; | |
| 519 | bool bEnabled; | |
| 520 | uint32_t dwAddress; | |
| 521 | } MHW_VDBOX_ROWSTORE_CACHE, *PMHW_VDBOX_ROWSTORE_CACHE; | |
| 522 | ||
| 523 | struct MHW_VDBOX_STATE_CMDSIZE_PARAMS | |
| 524 | { | |
| 525 | bool bShortFormat = false; | |
| 526 | bool bHucDummyStream = false; | |
| 527 | bool bSfcInUse = false; | |
| 528 | uint32_t uNumStoreDataImm = 0; | |
| 529 | uint32_t uNumStoreReg = 0; | |
| 530 | uint32_t uNumMfxWait = 0; | |
| 531 | uint32_t uNumAddConBBEnd = 0; | |
| 532 | uint32_t uNumMiCopy = 0; | |
| 533 | uint32_t uNumMiFlush = 0; | |
| 534 | uint32_t bPerformHucStreamOut = false; | |
| 535 | uint32_t uNumVdPipelineFlush = 0; | |
| 536 | virtual ~MHW_VDBOX_STATE_CMDSIZE_PARAMS() {} | |
| 537 | }; | |
| 538 | using PMHW_VDBOX_STATE_CMDSIZE_PARAMS = MHW_VDBOX_STATE_CMDSIZE_PARAMS * ; | |
| 539 | ||
| 540 | typedef struct _MHW_VDBOX_AVC_SLICE_STATE | |
| 541 | { | |
| 542 | PCODEC_PIC_ID pAvcPicIdx; | |
| 543 | PMOS_RESOURCE presDataBuffer; | |
| 544 | uint32_t dwDataBufferOffset; | |
| 545 | uint32_t dwOffset; | |
| 546 | uint32_t dwLength; | |
| 547 | uint32_t dwSliceIndex; | |
| 548 | bool bLastSlice; | |
| 549 | uint32_t dwTotalBytesConsumed; | |
| 550 | ||
| 551 | // Decoding Only | |
| 552 | PCODEC_AVC_PIC_PARAMS pAvcPicParams; | |
| 553 | PCODEC_MVC_EXT_PIC_PARAMS pMvcExtPicParams; | |
| 554 | PCODEC_AVC_SLICE_PARAMS pAvcSliceParams; | |
| 555 | uint32_t dwNextOffset; | |
| 556 | uint32_t dwNextLength; | |
| 557 | bool bIntelEntrypointInUse; | |
| 558 | bool bPicIdRemappingInUse; | |
| 559 | bool bShortFormatInUse; | |
| 560 | bool bPhantomSlice; | |
| 561 | uint8_t ucDisableDeblockingFilterIdc; | |
| 562 | uint8_t ucSliceBetaOffsetDiv2; | |
| 563 | uint8_t ucSliceAlphaC0OffsetDiv2; | |
| 564 | ||
| 565 | // Encoding Only | |
| 566 | PCODEC_AVC_ENCODE_SEQUENCE_PARAMS pEncodeAvcSeqParams; | |
| 567 | PCODEC_AVC_ENCODE_PIC_PARAMS pEncodeAvcPicParams; | |
| 568 | PCODEC_AVC_ENCODE_SLICE_PARAMS pEncodeAvcSliceParams; | |
| 569 | PBSBuffer pBsBuffer; | |
| 570 | PCODECHAL_NAL_UNIT_PARAMS *ppNalUnitParams; | |
| 571 | PMHW_BATCH_BUFFER pBatchBufferForPakSlices; | |
| 572 | bool bSingleTaskPhaseSupported; | |
| 573 | bool bFirstPass; | |
| 574 | bool bLastPass; | |
| 575 | bool bBrcEnabled; | |
| 576 | bool bRCPanicEnable; | |
| 577 | bool bInsertBeforeSliceHeaders; | |
| 578 | bool bAcceleratorHeaderPackingCaps; | |
| 579 | uint32_t dwBatchBufferForPakSlicesStartOffset; | |
| 580 | uint32_t uiSkipEmulationCheckCount; | |
| 581 | uint32_t dwRoundingValue; | |
| 582 | uint32_t dwRoundingIntraValue; | |
| 583 | bool bRoundingInterEnable; | |
| 584 | uint16_t wFrameFieldHeightInMB; // Frame/field Height in MB | |
| 585 | bool bVdencInUse; | |
| 586 | bool bVdencNoTailInsertion; | |
| 587 | bool oneOnOneMapping = false; | |
| 588 | bool bFullFrameData; | |
| 589 | } MHW_VDBOX_AVC_SLICE_STATE, *PMHW_VDBOX_AVC_SLICE_STATE; | |
| 590 | ||
| 591 | #endif |
| 0 | 0 | /* |
| 1 | * Copyright (c) 2017-2018, Intel Corporation | |
| 1 | * Copyright (c) 2017-2021, Intel Corporation | |
| 2 | 2 | * |
| 3 | 3 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 4 | 4 | * copy of this software and associated documentation files (the "Software"), |
| 657 | 657 | //! |
| 658 | 658 | virtual void CalcAvcImgStateMinMaxBitrate(MHW_VDBOX_AVC_IMG_BITRATE_PARAMS& params); |
| 659 | 659 | |
| 660 | //! | |
| 661 | //! \brief Get new MFX interface, temporal solution before switching from | |
| 662 | //! old interface to new one | |
| 663 | //! | |
| 664 | //! \return pointer to new MFX interface | |
| 665 | //! | |
| 666 | virtual std::shared_ptr<void> GetNewMfxInterface() { return nullptr; } | |
| 667 | ||
| 668 | 660 | //! |
| 669 | 661 | //! \brief Add a resource to the command buffer |
| 670 | 662 | //! \details Internal function to add either a graphics address of a resource or |
| 864 | 856 | //! \brief Destructor |
| 865 | 857 | //! |
| 866 | 858 | virtual ~MhwVdboxMfxInterface() {} |
| 859 | ||
| 860 | //! | |
| 861 | //! \brief Get new MFX interface, temporal solution before switching from | |
| 862 | //! old interface to new one | |
| 863 | //! | |
| 864 | //! \return pointer to new MFX interface | |
| 865 | //! | |
| 866 | virtual std::shared_ptr<void> GetNewMfxInterface() { return nullptr; } | |
| 867 | 867 | |
| 868 | 868 | //! |
| 869 | 869 | //! \brief Judge if decode is in use |
| 960 | 960 | PMOS_INTERFACE pOsInterface, |
| 961 | 961 | int32_t *pFlag); |
| 962 | 962 | |
| 963 | uint32_t (* pfnGetInterfaceVersion) ( | |
| 964 | PMOS_INTERFACE pOsInterface); | |
| 965 | ||
| 963 | 966 | #if MOS_MESSAGES_ENABLED |
| 964 | 967 | |
| 965 | 968 | #define pfnAllocateResource(pOsInterface, pParams, pOsResource) \ |
| 188 | 188 | MT_LOG_ID_BASE = 0x00000000, // marker for tool, don't change this line |
| 189 | 189 | MT_MEM_ALLOC_ERR, |
| 190 | 190 | MT_GRAPHIC_ALLOC_ERR, |
| 191 | MT_ERR_NULL_CHECK, | |
| 192 | MT_ERR_HR_CHECK, | |
| 193 | MT_ERR_MOS_STATUS_CHECK, | |
| 194 | MT_ERR_CONDITION_CHECK, | |
| 195 | MT_ERR_INVALID_ARG, | |
| 196 | MT_ERR_LOCK_SURFACE, | |
| 197 | MT_MOS_GPUCXT_CREATE_FAIL, | |
| 198 | MT_MOS_GPUCXT_INVALID, | |
| 199 | MT_MOS_ADDCMD, | |
| 191 | 200 | MT_LOG_ID_CP_BASE = 0x01000000, |
| 192 | 201 | MT_LOG_ID_VP_BASE = 0x02000000, |
| 202 | MT_VP_BLT_START, | |
| 203 | MT_VP_BLT_END, | |
| 204 | MT_VP_BLT_BYPSSED, | |
| 205 | MT_VP_BLT_FORCE_COLORFILL, | |
| 206 | MT_VP_BLT_FAIL, | |
| 207 | MT_VP_BLT_PROCAMP_PARAM, | |
| 208 | MT_VP_BLT_DN_PARAM, | |
| 209 | MT_VP_BLT_IEF_PARAM, | |
| 210 | MT_VP_BLT_IECP_PARAM, | |
| 211 | MT_VP_BLT_RENDERPASS_DATA, | |
| 212 | MT_VP_BLT_PIPELINE, | |
| 213 | MT_VP_HAL_REALLOC_SURF, | |
| 214 | MT_VP_HAL_RENDER_VE, | |
| 215 | MT_VP_HAL_RENDER_VE_ISNEEDED, | |
| 216 | MT_VP_HAL_RENDER_VE_GETOUTPUTPIPE, | |
| 217 | MT_VP_HAL_RENDER_COMPOSITE, | |
| 218 | MT_VP_KERNEL_CSC, | |
| 219 | MT_VP_KERNEL_RULE, | |
| 220 | MT_VP_VE_SCALABILITY, | |
| 221 | MT_VP_VE_ADJUST_SURFPARAM, | |
| 222 | MT_MEDIA_COPY, | |
| 223 | MT_MEDIA_COPY_CPU, | |
| 224 | MT_MEDIA_COPY_BLT, | |
| 225 | MT_MEDIA_COPY_RENDER, | |
| 226 | MT_MEDIA_COPY_VE, | |
| 227 | MT_MEDIA_COPY_VE_LMITATION, | |
| 193 | 228 | MT_LOG_ID_DEC_BASE = 0x03000000, |
| 194 | 229 | MT_LOG_ID_ENC_BASE = 0x04000000, |
| 195 | 230 | } MT_LOG_ID; |
| 199 | 234 | //! |
| 200 | 235 | typedef enum _MT_PARAM_ID |
| 201 | 236 | { |
| 202 | MT_PARAM_ID_BASE = 0, | |
| 237 | MT_PARAM_ID_BASE = 0, | |
| 203 | 238 | MT_ERROR_CODE, |
| 239 | MT_COMPONENT, | |
| 240 | MT_SUB_COMPONENT, | |
| 241 | MT_CODE_LINE, | |
| 242 | MT_GENERIC_VALUE, | |
| 243 | MT_MOS_GPU_NODE, | |
| 244 | MT_SURF_PTR, | |
| 245 | MT_SURF_ALLOC_HANDLE, | |
| 246 | MT_SURF_WIDTH, | |
| 247 | MT_SURF_HEIGHT, | |
| 248 | MT_SURF_PITCH, | |
| 249 | MT_SURF_MOS_FORMAT, | |
| 250 | MT_SURF_TILE_TYPE, | |
| 251 | MT_SURF_COMP_ABLE, | |
| 252 | MT_SURF_COMP_MODE, | |
| 253 | MT_SURF_GMM_FLAG_GPU, | |
| 254 | MT_SURF_GMM_FLAG_INF, | |
| 255 | MT_SURF_GMM_FLAG_WA, | |
| 256 | MT_SURF_IS_INPUT, | |
| 257 | MT_SURF_IS_OUTPUT, | |
| 258 | MT_RECT_LEFT, | |
| 259 | MT_RECT_TOP, | |
| 260 | MT_RECT_RIGHT, | |
| 261 | MT_RECT_BOTTOM, | |
| 204 | 262 | MT_PARAM_ID_CP_BASE = 0x01000000, |
| 205 | 263 | MT_CP_SESSION_TYPE, |
| 206 | 264 | MT_CP_SESSION_MODE, |
| 207 | 265 | MT_PARAM_ID_VP_BASE = 0x02000000, |
| 266 | MT_VP_HAL_PTR, | |
| 267 | MT_VP_INTERNAL_SURF_TYPE, | |
| 268 | MT_VP_COLORSPACE, | |
| 269 | MT_VP_BLT_PARAM_DATA, | |
| 270 | MT_VP_BLT_PARAM_FLAG, | |
| 271 | MT_VP_BLT_SRC_COUNT, | |
| 272 | MT_VP_BLT_PATH_APO, | |
| 273 | MT_VP_RENDERPASS_FLAG_COMP_NEEDED, | |
| 274 | MT_VP_RENDERPASS_FLAG_HDR_NEEDED, | |
| 275 | MT_VP_RENDERPASS_FLAG_FASTCOLORFILL, | |
| 276 | MT_VP_RENDERPASS_FLAG_BYPASS_HDRKERNEL, | |
| 277 | MT_VP_RENDERPASS_FLAG_USEVEHDRSFC, | |
| 278 | MT_VP_RENDERDATA_OUTPUT_PIPE, | |
| 279 | MT_VP_RENDERDATA_2PASS_CSC, | |
| 280 | MT_VP_RENDERDATA_HDRCSCCUSDS, | |
| 281 | MT_VP_RENDERDATA_HDRSFC, | |
| 282 | MT_VP_RENDERDATA_HDR3DLUT, | |
| 283 | MT_VP_RENDERDATA_HDR1DLUT, | |
| 284 | MT_VP_RENDERDATA_BPROCAMP, | |
| 285 | MT_VP_RENDERDATA_BIECP, | |
| 286 | MT_VP_RENDERDATA_DV_TONAMAPPING, | |
| 287 | MT_VP_RENDER_VE_2PASS_SFC, | |
| 288 | MT_VP_RENDER_VE_USE_HDRTEMPSURF, | |
| 289 | MT_VP_RENDER_VE_HDRMODE, | |
| 290 | MT_VP_RENDER_VE_NEEDED, | |
| 291 | MT_VP_RENDER_VE_HITLIMITATION, | |
| 292 | MT_VP_RENDER_VE_8KFORCERENDER, | |
| 293 | MT_VP_RENDER_VE_CROPPING, | |
| 294 | MT_VP_RENDER_VE_SFCONLYFORVE, | |
| 295 | MT_VP_RENDER_VE_COMPBYPASSFEASIBLE, | |
| 296 | MT_VP_SCALINGMODE_SR, | |
| 297 | MT_VP_SKU_FTR_VERING, | |
| 298 | MT_VP_VE_SCALABILITY_EN, | |
| 299 | MT_VP_VE_SCALABILITY_USE_SFC, | |
| 300 | MT_VP_VE_SCALABILITY_IDX, | |
| 301 | MT_VP_VE_SCALABILITY_START_X, | |
| 302 | MT_VP_VE_SCALABILITY_END_X, | |
| 303 | MT_VP_VE_SCALABILITY_O_START_X, | |
| 304 | MT_VP_VE_SCALABILITY_O_END_X, | |
| 208 | 305 | MT_PARAM_ID_DEC_BASE = 0x03000000, |
| 209 | 306 | MT_PARAM_ID_ENC_BASE = 0x04000000, |
| 210 | 307 | } MT_PARAM_ID; |
| 368 | 368 | MOS_TraceEvent(EVENT_MEDIA_LOG, 3, head, sizeof(head), param, sizeof(param)); \ |
| 369 | 369 | } |
| 370 | 370 | |
| 371 | #define MT_LOG4(id, lvl, p1, v1, p2, v2, p3, v3, p4, v4) \ | |
| 372 | { \ | |
| 373 | int32_t head[] = {id, lvl}; \ | |
| 374 | MT_PARAM param[] = {{p1, v1}, {p2, v2}, {p3, v3}, {p4, v4}}; \ | |
| 375 | MOS_TraceEvent(EVENT_MEDIA_LOG, 4, head, sizeof(head), param, sizeof(param)); \ | |
| 376 | } | |
| 377 | ||
| 378 | #define MT_LOG5(id, lvl, p1, v1, p2, v2, p3, v3, p4, v4, p5, v5) \ | |
| 379 | { \ | |
| 380 | int32_t head[] = {id, lvl}; \ | |
| 381 | MT_PARAM param[] = {{p1, v1}, {p2, v2}, {p3, v3}, {p4, v4}, {p5, v5}}; \ | |
| 382 | MOS_TraceEvent(EVENT_MEDIA_LOG, 5, head, sizeof(head), param, sizeof(param)); \ | |
| 383 | } | |
| 384 | ||
| 385 | #define MT_LOG6(id, lvl, p1, v1, p2, v2, p3, v3, p4, v4, p5, v5, p6, v6) \ | |
| 386 | { \ | |
| 387 | int32_t head[] = {id, lvl}; \ | |
| 388 | MT_PARAM param[] = {{p1, v1}, {p2, v2}, {p3, v3}, {p4, v4}, {p5, v5}, {p6, v6}}; \ | |
| 389 | MOS_TraceEvent(EVENT_MEDIA_LOG, 6, head, sizeof(head), param, sizeof(param)); \ | |
| 390 | } | |
| 391 | ||
| 371 | 392 | #define MT_LOG7(id, lvl, p1, v1, p2, v2, p3, v3, p4, v4, p5, v5, p6, v6, p7, v7) \ |
| 372 | 393 | { \ |
| 373 | 394 | int32_t head[] = {id, lvl}; \ |
| 374 | 395 | MT_PARAM param[] = {{p1, v1}, {p2, v2}, {p3, v3}, {p4, v4}, {p5, v5}, {p6, v6}, {p7, v7}}; \ |
| 375 | MOS_TraceEvent(EVENT_MEDIA_LOG, 4, head, sizeof(head), param, sizeof(param)); \ | |
| 396 | MOS_TraceEvent(EVENT_MEDIA_LOG, 7, head, sizeof(head), param, sizeof(param)); \ | |
| 376 | 397 | } |
| 377 | 398 | |
| 378 | 399 | |
| 415 | 436 | #define MT_LOG1(id, lvl, p1, v1) |
| 416 | 437 | #define MT_LOG2(id, lvl, p1, v1, p2, v2) |
| 417 | 438 | #define MT_LOG3(id, lvl, p1, v1, p2, v2, p3, v3) |
| 439 | #define MT_LOG4(id, lvl, p1, v1, p2, v2, p3, v3, p4, v4) | |
| 440 | #define MT_LOG5(id, lvl, p1, v1, p2, v2, p3, v3, p4, v4, p5, v5) | |
| 441 | #define MT_LOG6(id, lvl, p1, v1, p2, v2, p3, v3, p4, v4, p5, v5, p6, v6) | |
| 418 | 442 | #define MT_LOG7(id, lvl, p1, v1, p2, v2, p3, v3, p4, v4, p5, v5, p6, v6, p7, v7) |
| 419 | 443 | #define MT_ERR(id) |
| 420 | 444 | #define MT_ERR1(id, p1, v1) |
| 365 | 365 | MOS_USER_FEATURE_VALUE_TYPE_UINT32, |
| 366 | 366 | "0", |
| 367 | 367 | "Performance Profiler Multi Process Support"), |
| 368 | MOS_DECLARE_UF_KEY_DBGONLY(__MEDIA_USER_FEATURE_ENABLE_HW_DEBUG_HOOKS_ID, | |
| 368 | MOS_DECLARE_UF_KEY_DBGONLY(__MEDIA_USER_FEATURE_ENABLE_HW_DEBUG_HOOKS_ID, | |
| 369 | 369 | "Enable Media Debug Hooks", |
| 370 | 370 | __MEDIA_USER_FEATURE_SUBKEY_INTERNAL, |
| 371 | 371 | __MEDIA_USER_FEATURE_SUBKEY_REPORT, |
| 374 | 374 | MOS_USER_FEATURE_VALUE_TYPE_INT32, |
| 375 | 375 | "0", |
| 376 | 376 | "Eanble HW debug hooks. 1: enable, 0: disable."), |
| 377 | MOS_DECLARE_UF_KEY_DBGONLY(__MEDIA_USER_FEATURE_VALUE_CODECHAL_FRAME_NUMBER_TO_STOP_ID, | |
| 377 | MOS_DECLARE_UF_KEY_DBGONLY(__MEDIA_USER_FEATURE_VALUE_CODECHAL_FRAME_NUMBER_TO_STOP_ID, | |
| 378 | 378 | "Decode Stop To Frame", |
| 379 | 379 | __MEDIA_USER_FEATURE_SUBKEY_INTERNAL, |
| 380 | 380 | __MEDIA_USER_FEATURE_SUBKEY_REPORT, |
| 383 | 383 | MOS_USER_FEATURE_VALUE_TYPE_INT32, |
| 384 | 384 | "-1", |
| 385 | 385 | "Frame Number To Stop"), |
| 386 | MOS_DECLARE_UF_KEY_DBGONLY(__MEDIA_USER_FEATURE_VALUE_CODECHAL_ENABLE_SW_CRC_ID, | |
| 387 | "Enable SW CRC", | |
| 388 | __MEDIA_USER_FEATURE_SUBKEY_INTERNAL, | |
| 389 | __MEDIA_USER_FEATURE_SUBKEY_REPORT, | |
| 390 | "General", | |
| 391 | MOS_USER_FEATURE_TYPE_USER, | |
| 392 | MOS_USER_FEATURE_VALUE_TYPE_UINT32, | |
| 393 | "0", | |
| 394 | "Enable SW CRC"), | |
| 386 | 395 | MOS_DECLARE_UF_KEY(__MEDIA_USER_FEATURE_VALUE_PERF_PROFILER_REGISTER_1, |
| 387 | 396 | "Perf Profiler Register 1", |
| 388 | 397 | __MEDIA_USER_FEATURE_SUBKEY_PERFORMANCE, |
| 2491 | 2500 | MOS_USER_FEATURE_VALUE_TYPE_INT32, |
| 2492 | 2501 | "0", |
| 2493 | 2502 | "Enable Decode Histogram StreamOut debug. 0:Disable, 1:Enable"), |
| 2503 | MOS_DECLARE_UF_KEY(__MEDIA_USER_FEATURE_VALUE_DECODE_SFC_RGBFORMAT_OUTPUT_DEBUG_ID, | |
| 2504 | "Decode SFC RGB Format Output", | |
| 2505 | __MEDIA_USER_FEATURE_SUBKEY_INTERNAL, | |
| 2506 | __MEDIA_USER_FEATURE_SUBKEY_REPORT, | |
| 2507 | "Decode", | |
| 2508 | MOS_USER_FEATURE_TYPE_USER, | |
| 2509 | MOS_USER_FEATURE_VALUE_TYPE_INT32, | |
| 2510 | "0", | |
| 2511 | "Enable Decode SFC RGB Format debug. 1:RGBP, 2:BGRP, 3:RGB24"), | |
| 2512 | MOS_DECLARE_UF_KEY(__MEDIA_USER_FEATURE_VALUE_DECODE_SFC_LINEAR_OUTPUT_DEBUG_ID, | |
| 2513 | "Decode SFC Linear Output Debug", | |
| 2514 | __MEDIA_USER_FEATURE_SUBKEY_INTERNAL, | |
| 2515 | __MEDIA_USER_FEATURE_SUBKEY_REPORT, | |
| 2516 | "Decode", | |
| 2517 | MOS_USER_FEATURE_TYPE_USER, | |
| 2518 | MOS_USER_FEATURE_VALUE_TYPE_INT32, | |
| 2519 | "0", | |
| 2520 | "Enable Decode SFC Linear Output debug. 0:Disable, 1:Enable"), | |
| 2521 | MOS_DECLARE_UF_KEY_DBGONLY(__MEDIA_USER_FEATURE_VALUE_HEVC_VDENC_TCBRC_ARB_DISABLE_ID, | |
| 2522 | "HEVC VDEnc TCBRC ARB Disable", | |
| 2523 | __MEDIA_USER_FEATURE_SUBKEY_INTERNAL, | |
| 2524 | __MEDIA_USER_FEATURE_SUBKEY_REPORT, | |
| 2525 | "Encode", | |
| 2526 | MOS_USER_FEATURE_TYPE_USER, | |
| 2527 | MOS_USER_FEATURE_VALUE_TYPE_INT32, | |
| 2528 | "0", | |
| 2529 | "Disable TCBRC ARB for HEVC VDEnc"), | |
| 2494 | 2530 | #endif // (_DEBUG || _RELEASE_INTERNAL |
| 2495 | 2531 | MOS_DECLARE_UF_KEY_DBGONLY(__MEDIA_USER_FEATURE_VALUE_STATUS_REPORTING_ENABLE_ID, |
| 2496 | 2532 | "Status Reporting", |
| 4368 | 4404 | MOS_USER_FEATURE_VALUE_TYPE_INT32, |
| 4369 | 4405 | "0", |
| 4370 | 4406 | "Enable protect Mode. 1: enable, 0: disable."), |
| 4407 | MOS_DECLARE_UF_KEY(__MEDIA_USER_FEATURE_VALUE_OLP_IN_USE_ID, | |
| 4408 | "OLP IN USE", | |
| 4409 | __MEDIA_USER_FEATURE_SUBKEY_INTERNAL, | |
| 4410 | __MEDIA_USER_FEATURE_SUBKEY_REPORT, | |
| 4411 | "Report", | |
| 4412 | MOS_USER_FEATURE_TYPE_USER, | |
| 4413 | MOS_USER_FEATURE_VALUE_TYPE_INT32, | |
| 4414 | "0", | |
| 4415 | "Report out whether OLP is in use."), | |
| 4416 | MOS_DECLARE_UF_KEY(__MEDIA_USER_FEATURE_VALUE_SKIP_FRAME_IN_USE_ID, | |
| 4417 | "Skip Frame IN USE", | |
| 4418 | __MEDIA_USER_FEATURE_SUBKEY_INTERNAL, | |
| 4419 | __MEDIA_USER_FEATURE_SUBKEY_REPORT, | |
| 4420 | "Report", | |
| 4421 | MOS_USER_FEATURE_TYPE_USER, | |
| 4422 | MOS_USER_FEATURE_VALUE_TYPE_INT32, | |
| 4423 | "0", | |
| 4424 | "Report out whether skip frame is in use."), | |
| 4371 | 4425 | }; |
| 4372 | 4426 | |
| 4373 | 4427 | PMOS_USER_FEATURE_VALUE const MosUtilities::m_mosUserFeatureDescFields = MOSUserFeatureDescFields; |
| 205 | 205 | #endif |
| 206 | 206 | |
| 207 | 207 | #if MOS_MESSAGES_ENABLED |
| 208 | template<class _Ty> inline | |
| 209 | void MOS_DeleteUtil( | |
| 210 | const char *functionName, | |
| 211 | const char *filename, | |
| 212 | int32_t line, | |
| 213 | _Ty& ptr) | |
| 208 | #define MOS_DeleteUtil(functionName, filename, line, ptr) \ | |
| 209 | if (ptr != nullptr) \ | |
| 210 | { \ | |
| 211 | MosUtilities::MosAtomicDecrement(&MosUtilities::m_mosMemAllocCounter); \ | |
| 212 | MOS_MEMNINJA_FREE_MESSAGE(ptr, functionName, filename, line); \ | |
| 213 | delete(ptr); \ | |
| 214 | ptr = nullptr; \ | |
| 215 | } | |
| 214 | 216 | #else |
| 215 | template<class _Ty> inline | |
| 216 | void MOS_DeleteUtil(_Ty& ptr) | |
| 217 | #define MOS_DeleteUtil(ptr) \ | |
| 218 | if (ptr != nullptr) \ | |
| 219 | { \ | |
| 220 | MosUtilities::MosAtomicDecrement(&MosUtilities::m_mosMemAllocCounter); \ | |
| 221 | MOS_MEMNINJA_FREE_MESSAGE(ptr, functionName, filename, line); \ | |
| 222 | delete(ptr); \ | |
| 223 | ptr = nullptr; \ | |
| 224 | } | |
| 217 | 225 | #endif |
| 218 | { | |
| 226 | ||
| 219 | 227 | #if MOS_MESSAGES_ENABLED |
| 220 | MosUtilities::MosDeleteUtil<_Ty>(functionName, filename, line, ptr); | |
| 228 | #define MOS_DeleteArrayUtil(functionName, filename, line, ptr) \ | |
| 229 | if (ptr != nullptr) \ | |
| 230 | { \ | |
| 231 | MosUtilities::MosAtomicDecrement(&MosUtilities::m_mosMemAllocCounter); \ | |
| 232 | MOS_MEMNINJA_FREE_MESSAGE(ptr, functionName, filename, line); \ | |
| 233 | delete[](ptr); \ | |
| 234 | ptr = nullptr; \ | |
| 235 | } | |
| 221 | 236 | #else |
| 222 | MosUtilities::MosDeleteUtil<_Ty>(ptr); | |
| 237 | #define MOS_DeleteArrayUtil(ptr) \ | |
| 238 | if (ptr != nullptr) \ | |
| 239 | { \ | |
| 240 | MosUtilities::MosAtomicDecrement(&MosUtilities::m_mosMemAllocCounter); \ | |
| 241 | MOS_MEMNINJA_FREE_MESSAGE(ptr, functionName, filename, line); \ | |
| 242 | delete[](ptr); \ | |
| 243 | ptr = nullptr; \ | |
| 244 | } | |
| 223 | 245 | #endif |
| 224 | return; | |
| 225 | } | |
| 226 | ||
| 227 | #if MOS_MESSAGES_ENABLED | |
| 228 | template<class _Ty> inline | |
| 229 | void MOS_DeleteArrayUtil( | |
| 230 | const char *functionName, | |
| 231 | const char *filename, | |
| 232 | int32_t line, | |
| 233 | _Ty& ptr) | |
| 234 | #else | |
| 235 | template <class _Ty> inline | |
| 236 | void MOS_DeleteArrayUtil(_Ty& ptr) | |
| 237 | #endif | |
| 238 | { | |
| 239 | #if MOS_MESSAGES_ENABLED | |
| 240 | MosUtilities::MosDeleteArrayUtil<_Ty>(functionName, filename, line, ptr); | |
| 241 | #else | |
| 242 | MosUtilities::MosDeleteArrayUtil<_Ty>(ptr); | |
| 243 | #endif | |
| 244 | return; | |
| 245 | } | |
| 246 | 246 | |
| 247 | 247 | #if MOS_MESSAGES_ENABLED |
| 248 | 248 | #define MOS_DeleteArray(ptr) MOS_DeleteArrayUtil(__FUNCTION__, __FILE__, __LINE__, ptr) |
| 0 | # Copyright (c) 2017-2019, Intel Corporation | |
| 0 | # Copyright (c) 2017-2021, Intel Corporation | |
| 1 | 1 | # |
| 2 | 2 | # Permission is hereby granted, free of charge, to any person obtaining a |
| 3 | 3 | # copy of this software and associated documentation files (the "Software"), |
| 27 | 27 | ${CMAKE_CURRENT_LIST_DIR}/renderhal.h |
| 28 | 28 | ${CMAKE_CURRENT_LIST_DIR}/renderhal_dsh.h |
| 29 | 29 | ${CMAKE_CURRENT_LIST_DIR}/renderhal_platform_interface.h |
| 30 | ${CMAKE_CURRENT_LIST_DIR}/renderhal_platform_interface_legacy.h | |
| 30 | 31 | ${CMAKE_CURRENT_LIST_DIR}/vphal_renderhal_common.h |
| 31 | 32 | ) |
| 32 | 33 | |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file renderhal_platform_interface_legacy.h | |
| 23 | //! \brief abstract the platfrom specific APIs into one class | |
| 24 | //! | |
| 25 | //! | |
| 26 | //! \file renderhal.h | |
| 27 | //! \brief Render Engine Interfaces shared across platforms | |
| 28 | //! \details Platform Independent Hardware Interfaces | |
| 29 | //! | |
| 30 | #ifndef __RENDERHAL_PLATFORM_INTERFACE_LEGACY_H__ | |
| 31 | #define __RENDERHAL_PLATFORM_INTERFACE_LEGACY_H__ | |
| 32 | ||
| 33 | #include "mos_os.h" | |
| 34 | #include "renderhal.h" | |
| 35 | #include "renderhal_platform_interface.h" | |
| 36 | ||
| 37 | class XRenderHal_Platform_Interface_Legacy : public XRenderHal_Platform_Interface | |
| 38 | { | |
| 39 | public: | |
| 40 | XRenderHal_Platform_Interface_Legacy() {} | |
| 41 | virtual ~XRenderHal_Platform_Interface_Legacy() {} | |
| 42 | }; | |
| 43 | ||
| 44 | #endif // __RENDERHAL_PLATFORM_INTERFACE_LEGACY_H__ |
| 893 | 893 | { |
| 894 | 894 | return DumpBufferInHexDwords(sshData, sshSize); |
| 895 | 895 | } |
| 896 | } | |
| 897 | ||
| 898 | MOS_STATUS MediaDebugInterface::SetSWCrcMode(bool swCrc) | |
| 899 | { | |
| 900 | m_swCRC = swCrc; | |
| 901 | return MOS_STATUS_SUCCESS; | |
| 902 | 896 | } |
| 903 | 897 | |
| 904 | 898 | MOS_STATUS MediaDebugInterface::DumpYUVSurface( |
| 34 | 34 | |
| 35 | 35 | namespace MediaUserSetting { |
| 36 | 36 | |
| 37 | //! The media user setting group | |
| 37 | //! | |
| 38 | //! The media user setting group | |
| 39 | //! Device - for regkeys which are touched per device | |
| 40 | //! Sequence - for regkeys which are touched per video sequence | |
| 41 | //! Frame - for regkeys which are touched per frame | |
| 42 | //! MaxCount - is used to configure size of Configure::m_definitions array | |
| 43 | //! Note: you must not assign any numeric values to the enum items, except for | |
| 44 | //! the device being set to 0 | |
| 45 | //! | |
| 38 | 46 | enum Group |
| 39 | 47 | { |
| 40 | Device, | |
| 48 | Device = 0, | |
| 41 | 49 | Sequence, |
| 42 | 50 | Frame, |
| 43 | 51 | MaxCount |
| 785 | 785 | } |
| 786 | 786 | |
| 787 | 787 | #if (LINUX || ANDROID) |
| 788 | dwGpuTag = pOsContext->GetGPUTag(m_osInterface, pStatusEntry->GpuContextOrdinal); | |
| 788 | dwGpuTag = pOsContext->GetGPUTag(m_osInterface, pStatusEntry->GpuContextOrdinal); | |
| 789 | 789 | #else |
| 790 | dwGpuTag = pOsContext->GetGPUTag(pOsContext->GetGpuContextHandle(pStatusEntry->GpuContextOrdinal, m_osInterface->streamIndex)); | |
| 790 | dwGpuTag = m_osInterface->pfnGetGpuStatusSyncTag(m_osInterface, pStatusEntry->GpuContextOrdinal); | |
| 791 | 791 | #endif |
| 792 | 792 | bDoneByGpu = (dwGpuTag >= pStatusEntry->dwTag); |
| 793 | 793 | bFailedOnSubmitCmd = (pStatusEntry->dwStatus == VPREP_ERROR); |
| 32 | 32 | #include "mhw_vebox.h" |
| 33 | 33 | #include "mhw_sfc.h" |
| 34 | 34 | #include "vp_pipeline_adapter_base.h" |
| 35 | #include "vp_feature_report.h" | |
| 35 | 36 | |
| 36 | 37 | //*----------------------------------------------------------------------------- |
| 37 | 38 | //| DEFINITIONS |
| 132 | 132 | break; |
| 133 | 133 | |
| 134 | 134 | default: |
| 135 | VPHAL_PUBLIC_ASSERTMESSAGE("Unsupported Output ColorSpace."); | |
| 135 | VPHAL_PUBLIC_NORMALMESSAGE("Unsupported Output ColorSpace %d.", (uint32_t)dstCspace); | |
| 136 | 136 | bResult = false; |
| 137 | 137 | break; |
| 138 | 138 | } |
| 274 | 274 | break; |
| 275 | 275 | |
| 276 | 276 | default: |
| 277 | VPHAL_PUBLIC_ASSERTMESSAGE("Unsupported Input ColorSpace for Vebox."); | |
| 277 | VPHAL_PUBLIC_NORMALMESSAGE("Unsupported Input ColorSpace for Vebox %d.", (uint32_t)SrcCspace); | |
| 278 | 278 | } |
| 279 | 279 | |
| 280 | 280 | // Get the output offsets |
| 330 | 330 | break; |
| 331 | 331 | |
| 332 | 332 | default: |
| 333 | VPHAL_PUBLIC_ASSERTMESSAGE("Unsupported Output ColorSpace for Vebox."); | |
| 333 | VPHAL_PUBLIC_NORMALMESSAGE("Unsupported Output ColorSpace for Vebox %d.", (uint32_t)DstCspace); | |
| 334 | 334 | } |
| 335 | 335 | } |
| 336 | 336 | |
| 380 | 380 | return VpHal_Sinc(x) * VpHal_Sinc(x / fLanczosT); |
| 381 | 381 | } |
| 382 | 382 | |
| 383 | bool isSyncFreeNeededForMMCSurface(PVPHAL_SURFACE pSurface, PMOS_INTERFACE pOsInterface) | |
| 383 | bool IsSyncFreeNeededForMMCSurface(PVPHAL_SURFACE pSurface, PMOS_INTERFACE pOsInterface) | |
| 384 | 384 | { |
| 385 | 385 | if (nullptr == pSurface || nullptr == pOsInterface) |
| 386 | 386 | { |
| 507 | 507 | |
| 508 | 508 | // Delete resource if already allocated |
| 509 | 509 | //if free the compressed surface, need set the sync dealloc flag as 1 for sync dealloc for aux table update |
| 510 | if (isSyncFreeNeededForMMCSurface(pSurface, pOsInterface)) | |
| 510 | if (IsSyncFreeNeededForMMCSurface(pSurface, pOsInterface)) | |
| 511 | 511 | { |
| 512 | 512 | resFreeFlags.SynchronousDestroy = 1; |
| 513 | 513 | VPHAL_PUBLIC_NORMALMESSAGE("Set SynchronousDestroy flag for compressed resource %s", pSurfaceName); |
| 529 | 529 | VPHAL_PUBLIC_CHK_STATUS(VpHal_GetSurfaceInfo(pOsInterface, &Info, pSurface)); |
| 530 | 530 | |
| 531 | 531 | *pbAllocated = true; |
| 532 | ||
| 533 | MT_LOG7(MT_VP_HAL_REALLOC_SURF, MT_NORMAL, MT_VP_INTERNAL_SURF_TYPE, pSurfaceName ? *((int64_t*)pSurfaceName) : 0, | |
| 534 | MT_SURF_WIDTH, dwWidth, MT_SURF_HEIGHT, dwHeight, MT_SURF_MOS_FORMAT, Format, MT_SURF_TILE_TYPE, pSurface->TileModeGMM, | |
| 535 | MT_SURF_COMP_ABLE, pSurface->bCompressible, MT_SURF_COMP_MODE, pSurface->CompressionMode); | |
| 532 | 536 | |
| 533 | 537 | finish: |
| 534 | 538 | VPHAL_PUBLIC_ASSERT(eStatus == MOS_STATUS_SUCCESS); |
| 1567 | 1567 | MOS_SURFACE VpHal_ConvertVphalSurfaceToMosSurface( |
| 1568 | 1568 | PVPHAL_SURFACE pSurface); |
| 1569 | 1569 | |
| 1570 | bool IsSyncFreeNeededForMMCSurface(PVPHAL_SURFACE pSurface, PMOS_INTERFACE pOsInterface); | |
| 1571 | ||
| 1570 | 1572 | //! |
| 1571 | 1573 | //! \brief VEBOX IECP parameters |
| 1572 | 1574 | //! |
| 167 | 167 | VPHAL_PUBLIC_CHK_NULL_NO_STATUS_RETURN(pReport); |
| 168 | 168 | |
| 169 | 169 | // Report DI mode |
| 170 | switch (pReport->DeinterlaceMode) | |
| 170 | switch (pReport->GetFeatures().deinterlaceMode) | |
| 171 | 171 | { |
| 172 | 172 | case VPHAL_DI_REPORT_BOB : |
| 173 | 173 | case VPHAL_DI_REPORT_ADI_BOB : |
| 185 | 185 | |
| 186 | 186 | // Report Scaling mode |
| 187 | 187 | pConfigValues->dwCurrentScalingMode = |
| 188 | (pReport->ScalingMode == VPHAL_SCALING_AVS) ? VPDDI_ADVANCEDSCALING : | |
| 189 | (pReport->ScalingMode > VPHAL_SCALING_AVS) ? VPDDI_SUPERRESOLUTIONSCALING : VPDDI_SCALING; | |
| 188 | (pReport->GetFeatures().scalingMode == VPHAL_SCALING_AVS) ? VPDDI_ADVANCEDSCALING : | |
| 189 | (pReport->GetFeatures().scalingMode > VPHAL_SCALING_AVS) ? VPDDI_SUPERRESOLUTIONSCALING : VPDDI_SCALING; | |
| 190 | 190 | |
| 191 | 191 | // Report Output Pipe |
| 192 | pConfigValues->dwCurrentOutputPipeMode = pReport->OutputPipeMode; | |
| 192 | pConfigValues->dwCurrentOutputPipeMode = pReport->GetFeatures().outputPipeMode; | |
| 193 | 193 | |
| 194 | 194 | // Report VE Feature In Use |
| 195 | pConfigValues->dwCurrentVEFeatureInUse = pReport->VEFeatureInUse; | |
| 195 | pConfigValues->dwCurrentVEFeatureInUse = pReport->GetFeatures().veFeatureInUse; | |
| 196 | 196 | |
| 197 | 197 | // Report MMC status |
| 198 | pConfigValues->dwVPMMCInUse = pReport->VPMMCInUse; | |
| 199 | pConfigValues->dwRTCompressible = pReport->RTCompressible; | |
| 200 | pConfigValues->dwRTCompressMode = pReport->RTCompressMode; | |
| 201 | pConfigValues->dwFFDICompressible = pReport->FFDICompressible; | |
| 202 | pConfigValues->dwFFDICompressMode = pReport->FFDICompressMode; | |
| 203 | pConfigValues->dwFFDNCompressible = pReport->FFDNCompressible; | |
| 204 | pConfigValues->dwFFDNCompressMode = pReport->FFDNCompressMode; | |
| 205 | pConfigValues->dwSTMMCompressible = pReport->STMMCompressible; | |
| 206 | pConfigValues->dwSTMMCompressMode = pReport->STMMCompressMode; | |
| 207 | pConfigValues->dwScalerCompressible = pReport->ScalerCompressible; | |
| 208 | pConfigValues->dwScalerCompressMode = pReport->ScalerCompressMode; | |
| 209 | pConfigValues->dwPrimaryCompressible = pReport->PrimaryCompressible; | |
| 210 | pConfigValues->dwPrimaryCompressMode = pReport->PrimaryCompressMode; | |
| 198 | pConfigValues->dwVPMMCInUse = pReport->GetFeatures().vpMMCInUse; | |
| 199 | pConfigValues->dwRTCompressible = pReport->GetFeatures().rtCompressible; | |
| 200 | pConfigValues->dwRTCompressMode = pReport->GetFeatures().rtCompressMode; | |
| 201 | pConfigValues->dwFFDICompressible = pReport->GetFeatures().ffdiCompressible; | |
| 202 | pConfigValues->dwFFDICompressMode = pReport->GetFeatures().ffdiCompressMode; | |
| 203 | pConfigValues->dwFFDNCompressible = pReport->GetFeatures().ffdnCompressible; | |
| 204 | pConfigValues->dwFFDNCompressMode = pReport->GetFeatures().ffdnCompressMode; | |
| 205 | pConfigValues->dwSTMMCompressible = pReport->GetFeatures().stmmCompressible; | |
| 206 | pConfigValues->dwSTMMCompressMode = pReport->GetFeatures().stmmCompressMode; | |
| 207 | pConfigValues->dwScalerCompressible = pReport->GetFeatures().scalerCompressible; | |
| 208 | pConfigValues->dwScalerCompressMode = pReport->GetFeatures().scalerCompressMode; | |
| 209 | pConfigValues->dwPrimaryCompressible = pReport->GetFeatures().primaryCompressible; | |
| 210 | pConfigValues->dwPrimaryCompressMode = pReport->GetFeatures().primaryCompressMode; | |
| 211 | 211 | |
| 212 | 212 | // Report In Place Compositon status |
| 213 | pConfigValues->dwCurrentCompositionMode = pReport->CompositionMode; | |
| 214 | pConfigValues->dwCurrentScdMode = pReport->DiScdMode; | |
| 213 | pConfigValues->dwCurrentCompositionMode = pReport->GetFeatures().compositionMode; | |
| 214 | pConfigValues->dwCurrentScdMode = pReport->GetFeatures().diScdMode; | |
| 215 | 215 | |
| 216 | 216 | VP_DDI_NORMALMESSAGE("VP Feature Report: \ |
| 217 | 217 | OutputPipeMode %d, \ |
| 224 | 224 | PrimaryCompressible %d, \ |
| 225 | 225 | PrimaryCompressMode %d, \ |
| 226 | 226 | CompositionMode %d", |
| 227 | pReport->OutputPipeMode, | |
| 228 | pReport->VEFeatureInUse, | |
| 229 | pReport->ScalingMode, | |
| 230 | pReport->DeinterlaceMode, | |
| 231 | pReport->VPMMCInUse, | |
| 232 | pReport->RTCompressible, | |
| 233 | pReport->RTCompressMode, | |
| 234 | pReport->PrimaryCompressible, | |
| 235 | pReport->PrimaryCompressMode, | |
| 236 | pReport->CompositionMode | |
| 227 | pReport->GetFeatures().outputPipeMode, | |
| 228 | pReport->GetFeatures().veFeatureInUse, | |
| 229 | pReport->GetFeatures().scalingMode, | |
| 230 | pReport->GetFeatures().deinterlaceMode, | |
| 231 | pReport->GetFeatures().vpMMCInUse, | |
| 232 | pReport->GetFeatures().rtCompressible, | |
| 233 | pReport->GetFeatures().rtCompressMode, | |
| 234 | pReport->GetFeatures().primaryCompressible, | |
| 235 | pReport->GetFeatures().primaryCompressMode, | |
| 236 | pReport->GetFeatures().compositionMode | |
| 237 | 237 | ); |
| 238 | 238 | } |
| 239 | 239 | |
| 66 | 66 | FPS_DETECTION_STATES //!< Number of frame rate detection states |
| 67 | 67 | } FPS_DETECTION_STATE; |
| 68 | 68 | |
| 69 | //! | |
| 70 | //! \brief Deinterlace Mode enum | |
| 71 | //! | |
| 72 | typedef enum | |
| 73 | { | |
| 74 | VPDDI_PROGRESSIVE = 0, //!< Progressive mode | |
| 75 | VPDDI_BOB = 1, //!< BOB DI mode | |
| 76 | VPDDI_ADI = 2 //!< ADI mode | |
| 77 | } DI_MODE; | |
| 78 | ||
| 79 | //! | |
| 80 | //! \brief Scaling Mode enum | |
| 81 | //! | |
| 82 | typedef enum | |
| 83 | { | |
| 84 | VPDDI_SCALING = 0, //!< Bilinear scaling | |
| 85 | VPDDI_ADVANCEDSCALING = 1, //!< AVS scaling | |
| 86 | VPDDI_SUPERRESOLUTIONSCALING = 2 //!< Super scaling | |
| 87 | } SCALING_MODE; | |
| 88 | 69 | |
| 89 | 70 | //! |
| 90 | 71 | //! \brief Judge whether the input procamp value is default or not |
| 7282 | 7282 | //! |
| 7283 | 7283 | void CompositeState::SetReporting(PVPHAL_SURFACE pSource) |
| 7284 | 7284 | { |
| 7285 | m_reporting->IEF = pSource->bIEF; | |
| 7286 | m_reporting->ScalingMode = pSource->ScalingMode; | |
| 7287 | m_reporting->DeinterlaceMode = | |
| 7285 | m_reporting->GetFeatures().ief = pSource->bIEF; | |
| 7286 | m_reporting->GetFeatures().scalingMode = pSource->ScalingMode; | |
| 7287 | m_reporting->GetFeatures().deinterlaceMode = | |
| 7288 | 7288 | (IsBobDiEnabled(pSource)) ? VPHAL_DI_REPORT_BOB : |
| 7289 | 7289 | VPHAL_DI_REPORT_PROGRESSIVE; |
| 7290 | 7290 | } |
| 7299 | 7299 | { |
| 7300 | 7300 | VPHAL_RENDER_ASSERT(pReporting); |
| 7301 | 7301 | |
| 7302 | pReporting->IEF = m_reporting->IEF; | |
| 7303 | pReporting->ScalingMode = m_reporting->ScalingMode; | |
| 7304 | ||
| 7305 | if (m_reporting->DeinterlaceMode != VPHAL_DI_REPORT_PROGRESSIVE) | |
| 7306 | { | |
| 7307 | pReporting->DeinterlaceMode = m_reporting->DeinterlaceMode; | |
| 7302 | pReporting->GetFeatures().ief = m_reporting->GetFeatures().ief; | |
| 7303 | pReporting->GetFeatures().scalingMode = m_reporting->GetFeatures().scalingMode; | |
| 7304 | ||
| 7305 | if (m_reporting->GetFeatures().deinterlaceMode != VPHAL_DI_REPORT_PROGRESSIVE) | |
| 7306 | { | |
| 7307 | pReporting->GetFeatures().deinterlaceMode = m_reporting->GetFeatures().deinterlaceMode; | |
| 7308 | 7308 | } |
| 7309 | 7309 | } |
| 7310 | 7310 | |
| 696 | 696 | //---------------------------- |
| 697 | 697 | // VEBOX feature reporting |
| 698 | 698 | //---------------------------- |
| 699 | m_reporting->IECP = IsIECPEnabled(); | |
| 700 | m_reporting->Denoise = pRenderData->bDenoise; | |
| 699 | m_reporting->GetFeatures().iecp = IsIECPEnabled(); | |
| 700 | m_reporting->GetFeatures().denoise = pRenderData->bDenoise; | |
| 701 | 701 | if (pRenderData->bDeinterlace) |
| 702 | 702 | { |
| 703 | m_reporting->DeinterlaceMode = | |
| 703 | m_reporting->GetFeatures().deinterlaceMode = | |
| 704 | 704 | (pRenderData->bSingleField && !pRenderData->bRefValid ) ? |
| 705 | 705 | VPHAL_DI_REPORT_ADI_BOB : // VEBOX BOB |
| 706 | 706 | VPHAL_DI_REPORT_ADI; // ADI |
| 3735 | 3735 | } |
| 3736 | 3736 | |
| 3737 | 3737 | // Feature reporting |
| 3738 | m_reporting->IECP = pRenderData->bIECP; | |
| 3739 | m_reporting->Denoise = pRenderData->bDenoise; | |
| 3738 | m_reporting->GetFeatures().iecp = pRenderData->bIECP; | |
| 3739 | m_reporting->GetFeatures().denoise = pRenderData->bDenoise; | |
| 3740 | 3740 | |
| 3741 | 3741 | if (pRenderData->bDeinterlace) |
| 3742 | 3742 | { |
| 3743 | m_reporting->DeinterlaceMode = | |
| 3743 | m_reporting->GetFeatures().deinterlaceMode = | |
| 3744 | 3744 | (pRenderData->bSingleField && |
| 3745 | 3745 | (!pRenderData->bRefValid || |
| 3746 | 3746 | pSrcSurface->pDeinterlaceParams->DIMode == DI_MODE_BOB)) ? |
| 3789 | 3789 | { //set 2passcsc outputpipe to VPHAL_OUTPUT_PIPE_MODE_COMP for final report. |
| 3790 | 3790 | SET_VPHAL_OUTPUT_PIPE(pRenderData, VPHAL_OUTPUT_PIPE_MODE_COMP); |
| 3791 | 3791 | } |
| 3792 | m_reporting->OutputPipeMode = pRenderData->OutputPipe; | |
| 3793 | m_reporting->VEFeatureInUse = !pRenderData->bVeboxBypass; | |
| 3794 | m_reporting->DiScdMode = pRenderData->VeboxDNDIParams.bSyntheticFrame; | |
| 3792 | m_reporting->GetFeatures().outputPipeMode = pRenderData->OutputPipe; | |
| 3793 | m_reporting->GetFeatures().veFeatureInUse = !pRenderData->bVeboxBypass; | |
| 3794 | m_reporting->GetFeatures().diScdMode = pRenderData->VeboxDNDIParams.bSyntheticFrame; | |
| 3795 | 3795 | |
| 3796 | 3796 | return eStatus; |
| 3797 | 3797 | } |
| 3947 | 3947 | //! |
| 3948 | 3948 | void VPHAL_VEBOX_STATE::CopyFeatureReporting(VphalFeatureReport* pReporting) |
| 3949 | 3949 | { |
| 3950 | pReporting->IECP = m_reporting->IECP; | |
| 3951 | pReporting->Denoise = m_reporting->Denoise; | |
| 3952 | pReporting->DeinterlaceMode = m_reporting->DeinterlaceMode; | |
| 3953 | pReporting->OutputPipeMode = m_reporting->OutputPipeMode; | |
| 3954 | pReporting->VPMMCInUse = bEnableMMC; | |
| 3955 | pReporting->VEFeatureInUse = m_reporting->VEFeatureInUse; | |
| 3950 | pReporting->GetFeatures().iecp = m_reporting->GetFeatures().iecp; | |
| 3951 | pReporting->GetFeatures().denoise = m_reporting->GetFeatures().denoise; | |
| 3952 | pReporting->GetFeatures().deinterlaceMode = m_reporting->GetFeatures().deinterlaceMode; | |
| 3953 | pReporting->GetFeatures().outputPipeMode = m_reporting->GetFeatures().outputPipeMode; | |
| 3954 | pReporting->GetFeatures().vpMMCInUse = bEnableMMC; | |
| 3955 | pReporting->GetFeatures().veFeatureInUse = m_reporting->GetFeatures().veFeatureInUse; | |
| 3956 | 3956 | } |
| 3957 | 3957 | |
| 3958 | 3958 | //! |
| 3964 | 3964 | void VPHAL_VEBOX_STATE::CopyResourceReporting(VphalFeatureReport* pReporting) |
| 3965 | 3965 | { |
| 3966 | 3966 | // Report Vebox intermediate surface |
| 3967 | pReporting->FFDICompressible = m_reporting->FFDICompressible; | |
| 3968 | pReporting->FFDICompressMode = m_reporting->FFDICompressMode; | |
| 3969 | pReporting->FFDNCompressible = m_reporting->FFDNCompressible; | |
| 3970 | pReporting->FFDNCompressMode = m_reporting->FFDNCompressMode; | |
| 3971 | pReporting->STMMCompressible = m_reporting->STMMCompressible; | |
| 3972 | pReporting->STMMCompressMode = m_reporting->STMMCompressMode; | |
| 3973 | pReporting->ScalerCompressible = m_reporting->ScalerCompressible; | |
| 3974 | pReporting->ScalerCompressMode = m_reporting->ScalerCompressMode; | |
| 3975 | pReporting->DiScdMode = m_reporting->DiScdMode; | |
| 3967 | pReporting->GetFeatures().ffdiCompressible = m_reporting->GetFeatures().ffdiCompressible; | |
| 3968 | pReporting->GetFeatures().ffdiCompressMode = m_reporting->GetFeatures().ffdiCompressMode; | |
| 3969 | pReporting->GetFeatures().ffdnCompressible = m_reporting->GetFeatures().ffdnCompressible; | |
| 3970 | pReporting->GetFeatures().ffdnCompressMode = m_reporting->GetFeatures().ffdnCompressMode; | |
| 3971 | pReporting->GetFeatures().stmmCompressible = m_reporting->GetFeatures().stmmCompressible; | |
| 3972 | pReporting->GetFeatures().stmmCompressMode = m_reporting->GetFeatures().stmmCompressMode; | |
| 3973 | pReporting->GetFeatures().scalerCompressible = m_reporting->GetFeatures().scalerCompressible; | |
| 3974 | pReporting->GetFeatures().scalerCompressMode = m_reporting->GetFeatures().scalerCompressMode; | |
| 3975 | pReporting->GetFeatures().diScdMode = m_reporting->GetFeatures().diScdMode; | |
| 3976 | 3976 | } |
| 3977 | 3977 | |
| 3978 | 3978 | //! |
| 4268 | 4268 | dwSurfaceHeight = pInSurface->dwHeight; |
| 4269 | 4269 | surfaceFormat = pOutSurface->Format; |
| 4270 | 4270 | surfaceColorSpace = pOutSurface->ColorSpace; |
| 4271 | ||
| 4272 | if (IS_YUV_FORMAT(pOutSurface->Format)) | |
| 4273 | { | |
| 4274 | surfaceFormat = Format_R10G10B10A2; | |
| 4275 | surfaceColorSpace = (IS_COLOR_SPACE_BT2020(pOutSurface->ColorSpace)) ? CSpace_BT2020_RGB : CSpace_sRGB; | |
| 4276 | } | |
| 4271 | 4277 | |
| 4272 | 4278 | // Hdr intermediate surface should be Y tile for best performance |
| 4273 | 4279 | VPHAL_RENDER_CHK_STATUS(VpHal_ReAllocateSurface( |
| 4680 | 4686 | |
| 4681 | 4687 | finish: |
| 4682 | 4688 | VPHAL_RENDER_NORMALMESSAGE("VPOutputPipe = %d, VEFeatureInUse = %d", |
| 4683 | pRenderer->GetReport()->OutputPipeMode, pRenderer->GetReport()->VEFeatureInUse); | |
| 4689 | pRenderer->GetReport()->GetFeatures().outputPipeMode, pRenderer->GetReport()->GetFeatures().veFeatureInUse); | |
| 4684 | 4690 | |
| 4685 | 4691 | return eStatus; |
| 4686 | 4692 | } |
| 62 | 62 | #define NOISE_LOWTEMPORALPIXELDIFF_THRESHOLD_DEFAULT 6 |
| 63 | 63 | #define NOISE_TEMPORALPIXELDIFF_THRESHOLD_DEFAULT 12 |
| 64 | 64 | #define NOISE_SUMABSTEMPORALDIFF_THRESHOLD_DEFAULT 128 |
| 65 | ||
| 66 | //! | |
| 67 | //! \brief Spatial Denoise Definitions | |
| 68 | //! | |
| 69 | #define NOSIE_GNE_CHROMA_THRESHOLD 1850 | |
| 70 | #define NOSIE_GNE_LUMA_THRESHOLD 32000 | |
| 65 | 71 | |
| 66 | 72 | // Pixel Range Threshold Array Denoise Definitions for SKL+ 5x5 Bilateral Filter |
| 67 | 73 | #define NOISE_BLF_RANGE_THRESHOLD_ADP_NLVL 1 |
| 256 | 256 | //non lockable resource enabled, we can't lock source surface |
| 257 | 257 | eStatus = MOS_STATUS_NULL_POINTER; |
| 258 | 258 | VPHAL_MEMORY_DECOMP_ASSERTMESSAGE("Failed to lock non-lockable input resource, buffer copy failed, eStatus:%d.\n", eStatus); |
| 259 | MT_ERR1(MT_ERR_LOCK_SURFACE, MT_SURF_IS_INPUT, 1); | |
| 259 | 260 | break; |
| 260 | 261 | } |
| 261 | 262 | |
| 266 | 267 | eStatus = MOS_STATUS_NULL_POINTER; |
| 267 | 268 | m_osInterface->pfnUnlockResource(m_osInterface, &sourceSurface.OsResource); |
| 268 | 269 | VPHAL_MEMORY_DECOMP_ASSERTMESSAGE("Failed to lock non-lockable output resource, buffer copy failed, eStatus:%d.\n", eStatus); |
| 270 | MT_ERR1(MT_ERR_LOCK_SURFACE, MT_SURF_IS_OUTPUT, 1); | |
| 269 | 271 | break; |
| 270 | 272 | } |
| 271 | 273 | // This resource is a series of bytes. Is not 2 dimensional. |
| 278 | 280 | if (eStatus != MOS_STATUS_SUCCESS) |
| 279 | 281 | { |
| 280 | 282 | VPHAL_MEMORY_DECOMP_ASSERTMESSAGE("Failed to copy linear buffer from source to target, eStatus:%d.\n", eStatus); |
| 283 | MT_ERR(MT_MEDIA_COPY_CPU); | |
| 281 | 284 | break; |
| 282 | 285 | } |
| 283 | 286 | } while (false); |
| 293 | 296 | { |
| 294 | 297 | eStatus = MOS_STATUS_INVALID_PARAMETER; |
| 295 | 298 | VPHAL_MEMORY_DECOMP_ASSERTMESSAGE("VEBOX does not support non-64align pitch linear surface, eStatus:%d.\n", eStatus); |
| 299 | MT_ERR2(MT_MEDIA_COPY_VE_LMITATION, MT_SURF_PITCH, sourceSurface.dwPitch, MT_SURF_PITCH, targetSurface.dwPitch); | |
| 296 | 300 | MOS_TraceEventExt(EVENT_MEDIA_COPY, EVENT_TYPE_END, nullptr, 0, nullptr, 0); |
| 297 | 301 | return eStatus; |
| 298 | 302 | } |
| 479 | 483 | sourceSurface.TileType == MOS_TILE_LINEAR) |
| 480 | 484 | { |
| 481 | 485 | VPHAL_MEMORY_DECOMP_NORMALMESSAGE("unsupport linear to linear convert, return unsupport feature"); |
| 486 | MT_ERR2(MT_MEDIA_COPY_VE_LMITATION, MT_SURF_TILE_TYPE, MOS_TILE_LINEAR, MT_SURF_TILE_TYPE, MOS_TILE_LINEAR); | |
| 482 | 487 | return MOS_STATUS_PLATFORM_NOT_SUPPORTED; |
| 483 | 488 | } |
| 484 | 489 | |
| 488 | 493 | if (!IsFormatSupported(&sourceSurface)) |
| 489 | 494 | { |
| 490 | 495 | VPHAL_MEMORY_DECOMP_NORMALMESSAGE("unsupport processing format, return unsupport feature"); |
| 496 | MT_ERR2(MT_MEDIA_COPY_VE_LMITATION, MT_SURF_MOS_FORMAT, sourceSurface.Format, MT_SURF_IS_INPUT, 1); | |
| 491 | 497 | return MOS_STATUS_PLATFORM_NOT_SUPPORTED; |
| 492 | 498 | } |
| 493 | 499 | |
| 499 | 505 | if (!IsFormatSupported(&targetSurface)) |
| 500 | 506 | { |
| 501 | 507 | VPHAL_MEMORY_DECOMP_NORMALMESSAGE("unsupport processing format, return unsupport feature"); |
| 508 | MT_ERR2(MT_MEDIA_COPY_VE_LMITATION, MT_SURF_MOS_FORMAT, targetSurface.Format, MT_SURF_IS_OUTPUT, 1); | |
| 502 | 509 | return MOS_STATUS_PLATFORM_NOT_SUPPORTED; |
| 503 | 510 | } |
| 504 | 511 | |
| 926 | 933 | surface->dwHeight = surface->dwSize / surface->dwPitch; |
| 927 | 934 | } |
| 928 | 935 | |
| 929 | if (IS_RGB64_FLOAT_FORMAT(surface->Format)) | |
| 936 | if (IS_RGB64_FLOAT_FORMAT(surface->Format) || IS_RGB64_FORMAT(surface->Format)) | |
| 930 | 937 | { |
| 931 | 938 | surface->Format = Format_Y416; |
| 932 | 939 | } |
| 993 | 993 | |
| 994 | 994 | if (pRenderPassData->pPrimarySurface && pRenderPassData->pPrimarySurface->bCompressible) |
| 995 | 995 | { |
| 996 | m_reporting->PrimaryCompressible = true; | |
| 997 | m_reporting->PrimaryCompressMode = (uint8_t)(pRenderPassData->pPrimarySurface->CompressionMode); | |
| 996 | m_reporting->GetFeatures().primaryCompressible = true; | |
| 997 | m_reporting->GetFeatures().primaryCompressMode = (uint8_t)(pRenderPassData->pPrimarySurface->CompressionMode); | |
| 998 | 998 | } |
| 999 | 999 | |
| 1000 | 1000 | if (pRenderParams->pTarget[0]->bCompressible) |
| 1002 | 1002 | MOS_ZeroMemory(&Info, sizeof(VPHAL_GET_SURFACE_INFO)); |
| 1003 | 1003 | |
| 1004 | 1004 | VpHal_GetSurfaceInfo(m_pOsInterface, &Info, pRenderParams->pTarget[0]); |
| 1005 | m_reporting->RTCompressible = true; | |
| 1006 | m_reporting->RTCompressMode = (uint8_t)(pRenderParams->pTarget[0]->CompressionMode); | |
| 1005 | m_reporting->GetFeatures().rtCompressible = true; | |
| 1006 | m_reporting->GetFeatures().rtCompressMode = (uint8_t)(pRenderParams->pTarget[0]->CompressionMode); | |
| 1007 | 1007 | } |
| 1008 | 1008 | } |
| 1009 | 1009 | |
| 1524 | 1524 | else |
| 1525 | 1525 | { |
| 1526 | 1526 | VPHAL_RENDER_ASSERTMESSAGE("Not supported color space conversion(from %d to %d)", src, dst); |
| 1527 | MT_ERR2(MT_VP_KERNEL_CSC, MT_VP_COLORSPACE, src, MT_VP_COLORSPACE, dst); | |
| 1527 | 1528 | } |
| 1528 | 1529 | } |
| 1529 | 1530 | |
| 2525 | 2526 | else |
| 2526 | 2527 | { |
| 2527 | 2528 | VPHAL_RENDER_ASSERTMESSAGE("reached maximum number of component kernels."); |
| 2529 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 2528 | 2530 | return false; |
| 2529 | 2531 | } |
| 2530 | 2532 | break; |
| 2583 | 2585 | if (pData == nullptr || iSize == 0) |
| 2584 | 2586 | { |
| 2585 | 2587 | VPHAL_RENDER_ASSERTMESSAGE("invalid patch."); |
| 2588 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 2586 | 2589 | return false; |
| 2587 | 2590 | } |
| 2588 | 2591 | |
| 2596 | 2599 | if (pSearchState->PatchCount >= DL_MAX_PATCHES) |
| 2597 | 2600 | { |
| 2598 | 2601 | VPHAL_RENDER_ASSERTMESSAGE("reached maximum number of patches."); |
| 2602 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 2599 | 2603 | return false; |
| 2600 | 2604 | } |
| 2601 | 2605 | |
| 2617 | 2621 | if (pPatch->iPatchDataSize + iSize > DL_MAX_PATCH_DATA_SIZE) |
| 2618 | 2622 | { |
| 2619 | 2623 | VPHAL_RENDER_ASSERTMESSAGE("exceeded maximum patch size."); |
| 2624 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 2620 | 2625 | return false; |
| 2621 | 2626 | } |
| 2622 | 2627 | |
| 2653 | 2658 | if (nPatches + pPatch->nPatches > DL_MAX_PATCH_BLOCKS) |
| 2654 | 2659 | { |
| 2655 | 2660 | VPHAL_RENDER_ASSERTMESSAGE("exceeded number of patch blocks."); |
| 2661 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 2656 | 2662 | return false; |
| 2657 | 2663 | } |
| 2658 | 2664 | |
| 2895 | 2901 | default: |
| 2896 | 2902 | // Failed to find a matching rule -> kernel search will fail |
| 2897 | 2903 | VPHAL_RENDER_ASSERTMESSAGE("Invalid rule %d @ layer %d, state %d.", pRuleEntry->id, pSearchState->layer_number, pSearchState->state); |
| 2904 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 2898 | 2905 | return false; |
| 2899 | 2906 | } |
| 2900 | 2907 | } |
| 2982 | 2989 | if (pRule->id != RID_IsParserState) |
| 2983 | 2990 | { |
| 2984 | 2991 | VPHAL_RENDER_ASSERTMESSAGE("Rule does not start with State."); |
| 2992 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 2985 | 2993 | return false; |
| 2986 | 2994 | } |
| 2987 | 2995 | |
| 2990 | 2998 | if (state < Parser_Begin) |
| 2991 | 2999 | { |
| 2992 | 3000 | VPHAL_RENDER_ASSERTMESSAGE("Invalid State %d.", state); |
| 3001 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 2993 | 3002 | return false; |
| 2994 | 3003 | } |
| 2995 | 3004 | else if (state >= Parser_Custom) |
| 3020 | 3029 | if (!pState->pSortedRules) |
| 3021 | 3030 | { |
| 3022 | 3031 | VPHAL_RENDER_ASSERTMESSAGE("Failed to allocate rule table."); |
| 3032 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 3023 | 3033 | return false; |
| 3024 | 3034 | } |
| 3025 | 3035 | |
| 3060 | 3070 | if (pRule->id != RID_Op_NewEntry) |
| 3061 | 3071 | { |
| 3062 | 3072 | VPHAL_RENDER_ASSERTMESSAGE("New rule entry expected."); |
| 3073 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 3063 | 3074 | return false; |
| 3064 | 3075 | } |
| 3065 | 3076 | |
| 3136 | 3147 | if (pRuleSet->iSetCount < 1) |
| 3137 | 3148 | { |
| 3138 | 3149 | VPHAL_RENDER_ASSERTMESSAGE("Ruleset must have at least one set rule."); |
| 3150 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 3139 | 3151 | return false; |
| 3140 | 3152 | } |
| 3141 | 3153 | } |
| 3206 | 3218 | if (!pState) |
| 3207 | 3219 | { |
| 3208 | 3220 | VPHAL_RENDER_ASSERTMESSAGE("Failed to allocate kernel dll states."); |
| 3221 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 3209 | 3222 | goto cleanup; |
| 3210 | 3223 | } |
| 3211 | 3224 | pState->iSize = i; |
| 3223 | 3236 | if (!KernelDll_SetupFunctionPointers(pState, ModifyFunctionPointers)) |
| 3224 | 3237 | { |
| 3225 | 3238 | VPHAL_RENDER_ASSERTMESSAGE("Failed to setup function pointers."); |
| 3239 | MT_ERR1(MT_VP_KERNEL_RULE, MT_CODE_LINE, __LINE__); | |
| 3226 | 3240 | goto cleanup; |
| 3227 | 3241 | } |
| 3228 | 3242 | |
| 74 | 74 | #define IDR_VP_ConstSrcBlend_444_16 41 |
| 75 | 75 | #define IDR_VP_CopyKernel_1D_to_2D_NV12_genx 42 |
| 76 | 76 | #define IDR_VP_CopyKernel_1D_to_2D_RGBP_genx 43 |
| 77 | #define IDR_VP_CopyKernel_2D_to_1D_NV12_genx 44 | |
| 78 | #define IDR_VP_CopyKernel_2D_to_1D_RGBP_genx 45 | |
| 79 | #define IDR_VP_CopyKernel_2D_to_2D_NV12_genx 46 | |
| 80 | #define IDR_VP_CopyKernel_2D_to_2D_RGBP_genx 47 | |
| 81 | #define IDR_VP_DP_FC_Setup_Walker_16x16 48 | |
| 82 | #define IDR_VP_DP_FC_Setup_Walker_4x4 49 | |
| 83 | #define IDR_VP_DP_FC_Setup_Walker_8x8 50 | |
| 84 | #define IDR_VP_EOT 51 | |
| 85 | #define IDR_VP_FMD_Summation 52 | |
| 86 | #define IDR_VP_FRC_Clean_Map 53 | |
| 87 | #define IDR_VP_FRC_GMV_Detection 54 | |
| 88 | #define IDR_VP_FRC_GMV_Sanity_Check 55 | |
| 89 | #define IDR_VP_FRC_GradUV 56 | |
| 90 | #define IDR_VP_FRC_GradY 57 | |
| 91 | #define IDR_VP_FRC_MC 58 | |
| 92 | #define IDR_VP_FRC_ME_Level1 59 | |
| 93 | #define IDR_VP_FRC_ME_Level2 60 | |
| 94 | #define IDR_VP_FRC_ME_Level3 61 | |
| 95 | #define IDR_VP_FRC_MV_Level1 62 | |
| 96 | #define IDR_VP_FRC_MV_Level2 63 | |
| 97 | #define IDR_VP_FRC_MV_Level3 64 | |
| 98 | #define IDR_VP_FRC_PS 65 | |
| 99 | #define IDR_VP_FRC_SPD_Map 66 | |
| 100 | #define IDR_VP_FRC_TempDiff 67 | |
| 101 | #define IDR_VP_FRC_TempDiff_HD 68 | |
| 102 | #define IDR_VP_FRC_WSD 69 | |
| 103 | #define IDR_VP_GammaC 70 | |
| 104 | #define IDR_VP_GeoCorrection 71 | |
| 105 | #define IDR_VP_HDR_mandatory 72 | |
| 106 | #define IDR_VP_HDR_per_frame_stat 73 | |
| 107 | #define IDR_VP_HDR_preprocess 74 | |
| 108 | #define IDR_VP_IS_DS 75 | |
| 109 | #define IDR_VP_IS_FW 76 | |
| 110 | #define IDR_VP_IS_GMC 77 | |
| 111 | #define IDR_VP_IS_ME 78 | |
| 112 | #define IDR_VP_Interlace_420_16_Buf_0 79 | |
| 113 | #define IDR_VP_Interlace_420_16_Buf_1 80 | |
| 114 | #define IDR_VP_Interlace_420_16_Buf_2 81 | |
| 115 | #define IDR_VP_Interlace_420_16_Buf_3 82 | |
| 116 | #define IDR_VP_Interlace_444AVS16_Buf_0 83 | |
| 117 | #define IDR_VP_Interlace_444AVS16_Buf_1 84 | |
| 118 | #define IDR_VP_Interlace_444AVS16_Buf_2 85 | |
| 119 | #define IDR_VP_Interlace_444AVS16_Buf_3 86 | |
| 120 | #define IDR_VP_Interlace_444_16_Buf_0 87 | |
| 121 | #define IDR_VP_Interlace_444_16_Buf_1 88 | |
| 122 | #define IDR_VP_Interlace_444_16_Buf_2 89 | |
| 123 | #define IDR_VP_Interlace_444_16_Buf_3 90 | |
| 124 | #define IDR_VP_LACE_HIST_SUM 91 | |
| 125 | #define IDR_VP_LACE_LUT 92 | |
| 126 | #define IDR_VP_LACE_PWLF 93 | |
| 127 | #define IDR_VP_LACE_STD 94 | |
| 128 | #define IDR_VP_LinkFile 95 | |
| 129 | #define IDR_VP_Mirror_AVS_H_L0 96 | |
| 130 | #define IDR_VP_Mirror_AVS_V_L0 97 | |
| 131 | #define IDR_VP_Mirror_H_YUV 98 | |
| 132 | #define IDR_VP_Mirror_H_YUVA 99 | |
| 133 | #define IDR_VP_Mirror_scale_H_L0 100 | |
| 134 | #define IDR_VP_Mirror_scale_V_L0 101 | |
| 135 | #define IDR_VP_NV12_DP_DownScaling_4x4 102 | |
| 136 | #define IDR_VP_NV12_DP_DownScaling_4x4_mirror_h 103 | |
| 137 | #define IDR_VP_NV12_DP_DownScaling_4x4_mirror_v 104 | |
| 138 | #define IDR_VP_NV12_DP_DownScaling_4x4_rot_180 105 | |
| 139 | #define IDR_VP_NV12_DP_DownScaling_4x4_rot_270 106 | |
| 140 | #define IDR_VP_NV12_DP_DownScaling_4x4_rot_90 107 | |
| 141 | #define IDR_VP_NV12_DP_DownScaling_4x4_rot_90_mirror_h 108 | |
| 142 | #define IDR_VP_NV12_DP_DownScaling_4x4_rot_90_mirror_v 109 | |
| 143 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th 110 | |
| 144 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_mirror_h 111 | |
| 145 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_mirror_v 112 | |
| 146 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_rot_180 113 | |
| 147 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_rot_270 114 | |
| 148 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_rot_90 115 | |
| 149 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_rot_90_mirror_h 116 | |
| 150 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_rot_90_mirror_v 117 | |
| 151 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio 118 | |
| 152 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_mirror_h 119 | |
| 153 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_mirror_v 120 | |
| 154 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_rot_180 121 | |
| 155 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_rot_270 122 | |
| 156 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_rot_90 123 | |
| 157 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_rot_90_mirror_h 124 | |
| 158 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_rot_90_mirror_v 125 | |
| 159 | #define IDR_VP_NV12_DP_DownScaling_8x8 126 | |
| 160 | #define IDR_VP_NV12_DP_DownScaling_8x8_mirror_h 127 | |
| 161 | #define IDR_VP_NV12_DP_DownScaling_8x8_mirror_v 128 | |
| 162 | #define IDR_VP_NV12_DP_DownScaling_8x8_rot_180 129 | |
| 163 | #define IDR_VP_NV12_DP_DownScaling_8x8_rot_270 130 | |
| 164 | #define IDR_VP_NV12_DP_DownScaling_8x8_rot_90 131 | |
| 165 | #define IDR_VP_NV12_DP_DownScaling_8x8_rot_90_mirror_h 132 | |
| 166 | #define IDR_VP_NV12_DP_DownScaling_8x8_rot_90_mirror_v 133 | |
| 167 | #define IDR_VP_NV12_DP_UpScaling_16x16 134 | |
| 168 | #define IDR_VP_NV12_DP_UpScaling_16x16_mirror_h 135 | |
| 169 | #define IDR_VP_NV12_DP_UpScaling_16x16_mirror_v 136 | |
| 170 | #define IDR_VP_NV12_DP_UpScaling_16x16_rot_180 137 | |
| 171 | #define IDR_VP_NV12_DP_UpScaling_16x16_rot_270 138 | |
| 172 | #define IDR_VP_NV12_DP_UpScaling_16x16_rot_90 139 | |
| 173 | #define IDR_VP_NV12_DP_UpScaling_16x16_rot_90_mirror_h 140 | |
| 174 | #define IDR_VP_NV12_DP_UpScaling_16x16_rot_90_mirror_v 141 | |
| 175 | #define IDR_VP_NV12_DP_rotation_avg 142 | |
| 176 | #define IDR_VP_NV12_DP_rotation_nv12 143 | |
| 177 | #define IDR_VP_NV12_DP_rotation_rep 144 | |
| 178 | #define IDR_VP_P010_444Dscale16_Buf_0 145 | |
| 179 | #define IDR_VP_P010_444Dscale16_Buf_0_Rot_180 146 | |
| 180 | #define IDR_VP_P010_444Dscale16_Buf_0_Rot_270 147 | |
| 181 | #define IDR_VP_P010_444Dscale16_Buf_0_Rot_90 148 | |
| 182 | #define IDR_VP_P010_444Dscale16_Buf_1 149 | |
| 183 | #define IDR_VP_P010_444Dscale16_Buf_1_Rot_180 150 | |
| 184 | #define IDR_VP_P010_444Dscale16_Buf_1_Rot_270 151 | |
| 185 | #define IDR_VP_P010_444Dscale16_Buf_1_Rot_90 152 | |
| 186 | #define IDR_VP_P010_444Dscale16_Buf_2 153 | |
| 187 | #define IDR_VP_P010_444Dscale16_Buf_2_Rot_180 154 | |
| 188 | #define IDR_VP_P010_444Dscale16_Buf_2_Rot_270 155 | |
| 189 | #define IDR_VP_P010_444Dscale16_Buf_2_Rot_90 156 | |
| 190 | #define IDR_VP_P010_444Dscale16_Buf_3 157 | |
| 191 | #define IDR_VP_P010_444Dscale16_Buf_3_Rot_180 158 | |
| 192 | #define IDR_VP_P010_444Dscale16_Buf_3_Rot_270 159 | |
| 193 | #define IDR_VP_P010_444Dscale16_Buf_3_Rot_90 160 | |
| 194 | #define IDR_VP_PA_444AVS16_Buf_0 161 | |
| 195 | #define IDR_VP_PA_444AVS16_Buf_0_Rot_180 162 | |
| 196 | #define IDR_VP_PA_444AVS16_Buf_0_Rot_270 163 | |
| 197 | #define IDR_VP_PA_444AVS16_Buf_0_Rot_90 164 | |
| 198 | #define IDR_VP_PA_444AVS16_Buf_1 165 | |
| 199 | #define IDR_VP_PA_444AVS16_Buf_1_Rot_180 166 | |
| 200 | #define IDR_VP_PA_444AVS16_Buf_1_Rot_270 167 | |
| 201 | #define IDR_VP_PA_444AVS16_Buf_1_Rot_90 168 | |
| 202 | #define IDR_VP_PA_444AVS16_Buf_2 169 | |
| 203 | #define IDR_VP_PA_444AVS16_Buf_2_Rot_180 170 | |
| 204 | #define IDR_VP_PA_444AVS16_Buf_2_Rot_270 171 | |
| 205 | #define IDR_VP_PA_444AVS16_Buf_2_Rot_90 172 | |
| 206 | #define IDR_VP_PA_444AVS16_Buf_3 173 | |
| 207 | #define IDR_VP_PA_444AVS16_Buf_3_Rot_180 174 | |
| 208 | #define IDR_VP_PA_444AVS16_Buf_3_Rot_270 175 | |
| 209 | #define IDR_VP_PA_444AVS16_Buf_3_Rot_90 176 | |
| 210 | #define IDR_VP_PA_444AVS16_Buf_4 177 | |
| 211 | #define IDR_VP_PA_444AVS16_Buf_4_Rot_180 178 | |
| 212 | #define IDR_VP_PA_444AVS16_Buf_4_Rot_270 179 | |
| 213 | #define IDR_VP_PA_444AVS16_Buf_4_Rot_90 180 | |
| 214 | #define IDR_VP_PA_444AVS16_Buf_5 181 | |
| 215 | #define IDR_VP_PA_444AVS16_Buf_5_Rot_180 182 | |
| 216 | #define IDR_VP_PA_444AVS16_Buf_5_Rot_270 183 | |
| 217 | #define IDR_VP_PA_444AVS16_Buf_5_Rot_90 184 | |
| 218 | #define IDR_VP_PA_444AVS16_HDC_DW_PLANAR_420_8_Buf_0 185 | |
| 219 | #define IDR_VP_PA_444AVS16_HDC_DW_PLANAR_420_8_Buf_1 186 | |
| 220 | #define IDR_VP_PA_444AVS16_HDC_DW_PLANAR_420_8_Buf_2 187 | |
| 221 | #define IDR_VP_PA_444AVS16_HDC_DW_PLANAR_420_8_Buf_3 188 | |
| 222 | #define IDR_VP_PA_444AVS16_HDC_DW_Y8_UNORM_Buf_0 189 | |
| 223 | #define IDR_VP_PA_444AVS16_HDC_DW_Y8_UNORM_Buf_1 190 | |
| 224 | #define IDR_VP_PA_444AVS16_HDC_DW_Y8_UNORM_Buf_2 191 | |
| 225 | #define IDR_VP_PA_444AVS16_HDC_DW_Y8_UNORM_Buf_3 192 | |
| 226 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_NORMAL_Buf_0 193 | |
| 227 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_NORMAL_Buf_1 194 | |
| 228 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_NORMAL_Buf_2 195 | |
| 229 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_NORMAL_Buf_3 196 | |
| 230 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUVY_Buf_0 197 | |
| 231 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUVY_Buf_1 198 | |
| 232 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUVY_Buf_2 199 | |
| 233 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUVY_Buf_3 200 | |
| 234 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUV_Buf_0 201 | |
| 235 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUV_Buf_1 202 | |
| 236 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUV_Buf_2 203 | |
| 237 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUV_Buf_3 204 | |
| 238 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPY_Buf_0 205 | |
| 239 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPY_Buf_1 206 | |
| 240 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPY_Buf_2 207 | |
| 241 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPY_Buf_3 208 | |
| 242 | #define IDR_VP_PA_444DScale16_Buf_0 209 | |
| 243 | #define IDR_VP_PA_444DScale16_Buf_0_Rot_180 210 | |
| 244 | #define IDR_VP_PA_444DScale16_Buf_0_Rot_270 211 | |
| 245 | #define IDR_VP_PA_444DScale16_Buf_0_Rot_90 212 | |
| 246 | #define IDR_VP_PA_444DScale16_Buf_1 213 | |
| 247 | #define IDR_VP_PA_444DScale16_Buf_1_Rot_180 214 | |
| 248 | #define IDR_VP_PA_444DScale16_Buf_1_Rot_270 215 | |
| 249 | #define IDR_VP_PA_444DScale16_Buf_1_Rot_90 216 | |
| 250 | #define IDR_VP_PA_444DScale16_Buf_2 217 | |
| 251 | #define IDR_VP_PA_444DScale16_Buf_2_Rot_180 218 | |
| 252 | #define IDR_VP_PA_444DScale16_Buf_2_Rot_270 219 | |
| 253 | #define IDR_VP_PA_444DScale16_Buf_2_Rot_90 220 | |
| 254 | #define IDR_VP_PA_444DScale16_Buf_3 221 | |
| 255 | #define IDR_VP_PA_444DScale16_Buf_3_Rot_180 222 | |
| 256 | #define IDR_VP_PA_444DScale16_Buf_3_Rot_270 223 | |
| 257 | #define IDR_VP_PA_444DScale16_Buf_3_Rot_90 224 | |
| 258 | #define IDR_VP_PA_444DScale16_Buf_4 225 | |
| 259 | #define IDR_VP_PA_444DScale16_Buf_4_Rot_180 226 | |
| 260 | #define IDR_VP_PA_444DScale16_Buf_4_Rot_270 227 | |
| 261 | #define IDR_VP_PA_444DScale16_Buf_4_Rot_90 228 | |
| 262 | #define IDR_VP_PA_444DScale16_Buf_5 229 | |
| 263 | #define IDR_VP_PA_444DScale16_Buf_5_Rot_180 230 | |
| 264 | #define IDR_VP_PA_444DScale16_Buf_5_Rot_270 231 | |
| 265 | #define IDR_VP_PA_444DScale16_Buf_5_Rot_90 232 | |
| 266 | #define IDR_VP_PA_444Scale16_Buf_0 233 | |
| 267 | #define IDR_VP_PA_444Scale16_Buf_0_Rot_180 234 | |
| 268 | #define IDR_VP_PA_444Scale16_Buf_0_Rot_270 235 | |
| 269 | #define IDR_VP_PA_444Scale16_Buf_0_Rot_90 236 | |
| 270 | #define IDR_VP_PA_444Scale16_Buf_1 237 | |
| 271 | #define IDR_VP_PA_444Scale16_Buf_1_Rot_180 238 | |
| 272 | #define IDR_VP_PA_444Scale16_Buf_1_Rot_270 239 | |
| 273 | #define IDR_VP_PA_444Scale16_Buf_1_Rot_90 240 | |
| 274 | #define IDR_VP_PA_444Scale16_Buf_2 241 | |
| 275 | #define IDR_VP_PA_444Scale16_Buf_2_Rot_180 242 | |
| 276 | #define IDR_VP_PA_444Scale16_Buf_2_Rot_270 243 | |
| 277 | #define IDR_VP_PA_444Scale16_Buf_2_Rot_90 244 | |
| 278 | #define IDR_VP_PA_444Scale16_Buf_3 245 | |
| 279 | #define IDR_VP_PA_444Scale16_Buf_3_Rot_180 246 | |
| 280 | #define IDR_VP_PA_444Scale16_Buf_3_Rot_270 247 | |
| 281 | #define IDR_VP_PA_444Scale16_Buf_3_Rot_90 248 | |
| 282 | #define IDR_VP_PA_444Scale16_Buf_4 249 | |
| 283 | #define IDR_VP_PA_444Scale16_Buf_4_Rot_180 250 | |
| 284 | #define IDR_VP_PA_444Scale16_Buf_4_Rot_270 251 | |
| 285 | #define IDR_VP_PA_444Scale16_Buf_4_Rot_90 252 | |
| 286 | #define IDR_VP_PA_444Scale16_Buf_5 253 | |
| 287 | #define IDR_VP_PA_444Scale16_Buf_5_Rot_180 254 | |
| 288 | #define IDR_VP_PA_444Scale16_Buf_5_Rot_270 255 | |
| 289 | #define IDR_VP_PA_444Scale16_Buf_5_Rot_90 256 | |
| 290 | #define IDR_VP_PA_444iAVS16_Buf_0 257 | |
| 291 | #define IDR_VP_PA_444iAVS16_Buf_1 258 | |
| 292 | #define IDR_VP_PA_444iAVS16_Buf_2 259 | |
| 293 | #define IDR_VP_PA_444iAVS16_Buf_3 260 | |
| 294 | #define IDR_VP_PA_444iDScale16_Buf_0 261 | |
| 295 | #define IDR_VP_PA_444iDScale16_Buf_1 262 | |
| 296 | #define IDR_VP_PA_444iDScale16_Buf_2 263 | |
| 297 | #define IDR_VP_PA_444iDScale16_Buf_3 264 | |
| 298 | #define IDR_VP_PA_444iScale16_Buf_0 265 | |
| 299 | #define IDR_VP_PA_444iScale16_Buf_0_Rot_180 266 | |
| 300 | #define IDR_VP_PA_444iScale16_Buf_0_Rot_270 267 | |
| 301 | #define IDR_VP_PA_444iScale16_Buf_0_Rot_90 268 | |
| 302 | #define IDR_VP_PA_444iScale16_Buf_1 269 | |
| 303 | #define IDR_VP_PA_444iScale16_Buf_1_Rot_180 270 | |
| 304 | #define IDR_VP_PA_444iScale16_Buf_1_Rot_270 271 | |
| 305 | #define IDR_VP_PA_444iScale16_Buf_1_Rot_90 272 | |
| 306 | #define IDR_VP_PA_444iScale16_Buf_2 273 | |
| 307 | #define IDR_VP_PA_444iScale16_Buf_2_Rot_180 274 | |
| 308 | #define IDR_VP_PA_444iScale16_Buf_2_Rot_270 275 | |
| 309 | #define IDR_VP_PA_444iScale16_Buf_2_Rot_90 276 | |
| 310 | #define IDR_VP_PA_444iScale16_Buf_3 277 | |
| 311 | #define IDR_VP_PA_444iScale16_Buf_3_Rot_180 278 | |
| 312 | #define IDR_VP_PA_444iScale16_Buf_3_Rot_270 279 | |
| 313 | #define IDR_VP_PA_444iScale16_Buf_3_Rot_90 280 | |
| 314 | #define IDR_VP_PA_AVS_Mirror_H_L0 281 | |
| 315 | #define IDR_VP_PA_AVS_Mirror_V_L0 282 | |
| 316 | #define IDR_VP_PA_AVS_Rotate_90_Mirror_H_L0 283 | |
| 317 | #define IDR_VP_PA_AVS_Rotate_90_Mirror_V_L0 284 | |
| 318 | #define IDR_VP_PA_AVS_Rotate_L0_180 285 | |
| 319 | #define IDR_VP_PA_AVS_Rotate_L0_270 286 | |
| 320 | #define IDR_VP_PA_AVS_Rotate_L0_90 287 | |
| 321 | #define IDR_VP_PA_Copy 288 | |
| 322 | #define IDR_VP_PA_Scale_Mirror_H_L0 289 | |
| 323 | #define IDR_VP_PA_Scale_Mirror_V_L0 290 | |
| 324 | #define IDR_VP_PA_Scale_Rotate90_Mirror_H_L0 291 | |
| 325 | #define IDR_VP_PA_Scale_Rotate90_Mirror_V_L0 292 | |
| 326 | #define IDR_VP_PA_Scale_Rotate_L0_180 293 | |
| 327 | #define IDR_VP_PA_Scale_Rotate_L0_270 294 | |
| 328 | #define IDR_VP_PA_Scale_Rotate_L0_90 295 | |
| 329 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_0 296 | |
| 330 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_1 297 | |
| 331 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_2 298 | |
| 332 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_3 299 | |
| 333 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_4 300 | |
| 334 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_5 301 | |
| 335 | #define IDR_VP_PL2_444AVS16_Buf_0 302 | |
| 336 | #define IDR_VP_PL2_444AVS16_Buf_0_Rot_180 303 | |
| 337 | #define IDR_VP_PL2_444AVS16_Buf_0_Rot_270 304 | |
| 338 | #define IDR_VP_PL2_444AVS16_Buf_0_Rot_90 305 | |
| 339 | #define IDR_VP_PL2_444AVS16_Buf_1 306 | |
| 340 | #define IDR_VP_PL2_444AVS16_Buf_1_Rot_180 307 | |
| 341 | #define IDR_VP_PL2_444AVS16_Buf_1_Rot_270 308 | |
| 342 | #define IDR_VP_PL2_444AVS16_Buf_1_Rot_90 309 | |
| 343 | #define IDR_VP_PL2_444AVS16_Buf_2 310 | |
| 344 | #define IDR_VP_PL2_444AVS16_Buf_2_Rot_180 311 | |
| 345 | #define IDR_VP_PL2_444AVS16_Buf_2_Rot_270 312 | |
| 346 | #define IDR_VP_PL2_444AVS16_Buf_2_Rot_90 313 | |
| 347 | #define IDR_VP_PL2_444AVS16_Buf_3 314 | |
| 348 | #define IDR_VP_PL2_444AVS16_Buf_3_Rot_180 315 | |
| 349 | #define IDR_VP_PL2_444AVS16_Buf_3_Rot_270 316 | |
| 350 | #define IDR_VP_PL2_444AVS16_Buf_3_Rot_90 317 | |
| 351 | #define IDR_VP_PL2_444AVS16_Buf_4 318 | |
| 352 | #define IDR_VP_PL2_444AVS16_Buf_4_Rot_180 319 | |
| 353 | #define IDR_VP_PL2_444AVS16_Buf_4_Rot_270 320 | |
| 354 | #define IDR_VP_PL2_444AVS16_Buf_4_Rot_90 321 | |
| 355 | #define IDR_VP_PL2_444AVS16_Buf_5 322 | |
| 356 | #define IDR_VP_PL2_444AVS16_Buf_5_Rot_180 323 | |
| 357 | #define IDR_VP_PL2_444AVS16_Buf_5_Rot_270 324 | |
| 358 | #define IDR_VP_PL2_444AVS16_Buf_5_Rot_90 325 | |
| 359 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_4 326 | |
| 360 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_4_Rot_180 327 | |
| 361 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_4_Rot_270 328 | |
| 362 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_4_Rot_90 329 | |
| 363 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_5 330 | |
| 364 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_5_Rot_180 331 | |
| 365 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_5_Rot_270 332 | |
| 366 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_5_Rot_90 333 | |
| 367 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_0 334 | |
| 368 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_1 335 | |
| 369 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_2 336 | |
| 370 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_3 337 | |
| 371 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_4 338 | |
| 372 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_5 339 | |
| 373 | #define IDR_VP_PL2_444DScale16_Buf_0 340 | |
| 374 | #define IDR_VP_PL2_444DScale16_Buf_0_Rot_180 341 | |
| 375 | #define IDR_VP_PL2_444DScale16_Buf_0_Rot_270 342 | |
| 376 | #define IDR_VP_PL2_444DScale16_Buf_0_Rot_90 343 | |
| 377 | #define IDR_VP_PL2_444DScale16_Buf_1 344 | |
| 378 | #define IDR_VP_PL2_444DScale16_Buf_1_Rot_180 345 | |
| 379 | #define IDR_VP_PL2_444DScale16_Buf_1_Rot_270 346 | |
| 380 | #define IDR_VP_PL2_444DScale16_Buf_1_Rot_90 347 | |
| 381 | #define IDR_VP_PL2_444DScale16_Buf_2 348 | |
| 382 | #define IDR_VP_PL2_444DScale16_Buf_2_Rot_180 349 | |
| 383 | #define IDR_VP_PL2_444DScale16_Buf_2_Rot_270 350 | |
| 384 | #define IDR_VP_PL2_444DScale16_Buf_2_Rot_90 351 | |
| 385 | #define IDR_VP_PL2_444DScale16_Buf_3 352 | |
| 386 | #define IDR_VP_PL2_444DScale16_Buf_3_Rot_180 353 | |
| 387 | #define IDR_VP_PL2_444DScale16_Buf_3_Rot_270 354 | |
| 388 | #define IDR_VP_PL2_444DScale16_Buf_3_Rot_90 355 | |
| 389 | #define IDR_VP_PL2_444DScale16_Buf_4 356 | |
| 390 | #define IDR_VP_PL2_444DScale16_Buf_4_Rot_180 357 | |
| 391 | #define IDR_VP_PL2_444DScale16_Buf_4_Rot_270 358 | |
| 392 | #define IDR_VP_PL2_444DScale16_Buf_4_Rot_90 359 | |
| 393 | #define IDR_VP_PL2_444DScale16_Buf_5 360 | |
| 394 | #define IDR_VP_PL2_444DScale16_Buf_5_Rot_180 361 | |
| 395 | #define IDR_VP_PL2_444DScale16_Buf_5_Rot_270 362 | |
| 396 | #define IDR_VP_PL2_444DScale16_Buf_5_Rot_90 363 | |
| 397 | #define IDR_VP_PL2_444DScale16_Buf_Sep_Alpha_4 364 | |
| 398 | #define IDR_VP_PL2_444DScale16_Buf_Sep_Alpha_5 365 | |
| 399 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_0 366 | |
| 400 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_0_Rot_180 367 | |
| 401 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_0_Rot_270 368 | |
| 402 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_0_Rot_90 369 | |
| 403 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_1 370 | |
| 404 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_1_Rot_180 371 | |
| 405 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_1_Rot_270 372 | |
| 406 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_1_Rot_90 373 | |
| 407 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_2 374 | |
| 408 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_2_Rot_180 375 | |
| 409 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_2_Rot_270 376 | |
| 410 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_2_Rot_90 377 | |
| 411 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_3 378 | |
| 412 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_3_Rot_180 379 | |
| 413 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_3_Rot_270 380 | |
| 414 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_3_Rot_90 381 | |
| 415 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_4 382 | |
| 416 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_4_Rot_180 383 | |
| 417 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_4_Rot_270 384 | |
| 418 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_4_Rot_90 385 | |
| 419 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_5 386 | |
| 420 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_5_Rot_180 387 | |
| 421 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_5_Rot_270 388 | |
| 422 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_5_Rot_90 389 | |
| 423 | #define IDR_VP_PL2_444Scale16_Buf_0 390 | |
| 424 | #define IDR_VP_PL2_444Scale16_Buf_0_Rot_180 391 | |
| 425 | #define IDR_VP_PL2_444Scale16_Buf_0_Rot_270 392 | |
| 426 | #define IDR_VP_PL2_444Scale16_Buf_0_Rot_90 393 | |
| 427 | #define IDR_VP_PL2_444Scale16_Buf_1 394 | |
| 428 | #define IDR_VP_PL2_444Scale16_Buf_1_Rot_180 395 | |
| 429 | #define IDR_VP_PL2_444Scale16_Buf_1_Rot_270 396 | |
| 430 | #define IDR_VP_PL2_444Scale16_Buf_1_Rot_90 397 | |
| 431 | #define IDR_VP_PL2_444Scale16_Buf_2 398 | |
| 432 | #define IDR_VP_PL2_444Scale16_Buf_2_Rot_180 399 | |
| 433 | #define IDR_VP_PL2_444Scale16_Buf_2_Rot_270 400 | |
| 434 | #define IDR_VP_PL2_444Scale16_Buf_2_Rot_90 401 | |
| 435 | #define IDR_VP_PL2_444Scale16_Buf_3 402 | |
| 436 | #define IDR_VP_PL2_444Scale16_Buf_3_Rot_180 403 | |
| 437 | #define IDR_VP_PL2_444Scale16_Buf_3_Rot_270 404 | |
| 438 | #define IDR_VP_PL2_444Scale16_Buf_3_Rot_90 405 | |
| 439 | #define IDR_VP_PL2_444Scale16_Buf_4 406 | |
| 440 | #define IDR_VP_PL2_444Scale16_Buf_4_Rot_180 407 | |
| 441 | #define IDR_VP_PL2_444Scale16_Buf_4_Rot_270 408 | |
| 442 | #define IDR_VP_PL2_444Scale16_Buf_4_Rot_90 409 | |
| 443 | #define IDR_VP_PL2_444Scale16_Buf_5 410 | |
| 444 | #define IDR_VP_PL2_444Scale16_Buf_5_Rot_180 411 | |
| 445 | #define IDR_VP_PL2_444Scale16_Buf_5_Rot_270 412 | |
| 446 | #define IDR_VP_PL2_444Scale16_Buf_5_Rot_90 413 | |
| 447 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_4 414 | |
| 448 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_4_Rot_180 415 | |
| 449 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_4_Rot_270 416 | |
| 450 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_4_Rot_90 417 | |
| 451 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_5 418 | |
| 452 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_5_Rot_180 419 | |
| 453 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_5_Rot_270 420 | |
| 454 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_5_Rot_90 421 | |
| 455 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_0 422 | |
| 456 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_0_Rot_180 423 | |
| 457 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_0_Rot_270 424 | |
| 458 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_0_Rot_90 425 | |
| 459 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_1 426 | |
| 460 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_1_Rot_180 427 | |
| 461 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_1_Rot_270 428 | |
| 462 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_1_Rot_90 429 | |
| 463 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_2 430 | |
| 464 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_2_Rot_180 431 | |
| 465 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_2_Rot_270 432 | |
| 466 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_2_Rot_90 433 | |
| 467 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_3 434 | |
| 468 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_3_Rot_180 435 | |
| 469 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_3_Rot_270 436 | |
| 470 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_3_Rot_90 437 | |
| 471 | #define IDR_VP_PL2_444iDScale16_Buf_0 438 | |
| 472 | #define IDR_VP_PL2_444iDScale16_Buf_1 439 | |
| 473 | #define IDR_VP_PL2_444iDScale16_Buf_2 440 | |
| 474 | #define IDR_VP_PL2_444iDScale16_Buf_3 441 | |
| 475 | #define IDR_VP_PL2_444iScale16_Buf_0 442 | |
| 476 | #define IDR_VP_PL2_444iScale16_Buf_0_Rot_180 443 | |
| 477 | #define IDR_VP_PL2_444iScale16_Buf_0_Rot_270 444 | |
| 478 | #define IDR_VP_PL2_444iScale16_Buf_0_Rot_90 445 | |
| 479 | #define IDR_VP_PL2_444iScale16_Buf_1 446 | |
| 480 | #define IDR_VP_PL2_444iScale16_Buf_1_Rot_180 447 | |
| 481 | #define IDR_VP_PL2_444iScale16_Buf_1_Rot_270 448 | |
| 482 | #define IDR_VP_PL2_444iScale16_Buf_1_Rot_90 449 | |
| 483 | #define IDR_VP_PL2_444iScale16_Buf_2 450 | |
| 484 | #define IDR_VP_PL2_444iScale16_Buf_2_Rot_180 451 | |
| 485 | #define IDR_VP_PL2_444iScale16_Buf_2_Rot_270 452 | |
| 486 | #define IDR_VP_PL2_444iScale16_Buf_2_Rot_90 453 | |
| 487 | #define IDR_VP_PL2_444iScale16_Buf_3 454 | |
| 488 | #define IDR_VP_PL2_444iScale16_Buf_3_Rot_180 455 | |
| 489 | #define IDR_VP_PL2_444iScale16_Buf_3_Rot_270 456 | |
| 490 | #define IDR_VP_PL2_444iScale16_Buf_3_Rot_90 457 | |
| 491 | #define IDR_VP_PL2_AVS_Mirror_H_L0 458 | |
| 492 | #define IDR_VP_PL2_AVS_Mirror_H_L0_DualOutput 459 | |
| 493 | #define IDR_VP_PL2_AVS_Mirror_V_L0 460 | |
| 494 | #define IDR_VP_PL2_AVS_Rotate90_Mirror_H_L0 461 | |
| 495 | #define IDR_VP_PL2_AVS_Rotate90_Mirror_V_L0 462 | |
| 496 | #define IDR_VP_PL2_AVS_Rotate_L0_180 463 | |
| 497 | #define IDR_VP_PL2_AVS_Rotate_L0_270 464 | |
| 498 | #define IDR_VP_PL2_AVS_Rotate_L0_90 465 | |
| 499 | #define IDR_VP_PL2_Copy 466 | |
| 500 | #define IDR_VP_PL2_Scale_Mirror_H_L0 467 | |
| 501 | #define IDR_VP_PL2_Scale_Mirror_H_L0_DualOutput 468 | |
| 502 | #define IDR_VP_PL2_Scale_Mirror_V_L0 469 | |
| 503 | #define IDR_VP_PL2_Scale_Rotate90_Mirror_H_L0 470 | |
| 504 | #define IDR_VP_PL2_Scale_Rotate90_Mirror_V_L0 471 | |
| 505 | #define IDR_VP_PL2_Scale_Rotate_L0_180 472 | |
| 506 | #define IDR_VP_PL2_Scale_Rotate_L0_270 473 | |
| 507 | #define IDR_VP_PL2_Scale_Rotate_L0_90 474 | |
| 508 | #define IDR_VP_PL3_444AVS16_Buf_0 475 | |
| 509 | #define IDR_VP_PL3_444AVS16_Buf_0_Rot_180 476 | |
| 510 | #define IDR_VP_PL3_444AVS16_Buf_0_Rot_270 477 | |
| 511 | #define IDR_VP_PL3_444AVS16_Buf_0_Rot_90 478 | |
| 512 | #define IDR_VP_PL3_444AVS16_Buf_1 479 | |
| 513 | #define IDR_VP_PL3_444AVS16_Buf_1_Rot_180 480 | |
| 514 | #define IDR_VP_PL3_444AVS16_Buf_1_Rot_270 481 | |
| 515 | #define IDR_VP_PL3_444AVS16_Buf_1_Rot_90 482 | |
| 516 | #define IDR_VP_PL3_444AVS16_Buf_2 483 | |
| 517 | #define IDR_VP_PL3_444AVS16_Buf_2_Rot_180 484 | |
| 518 | #define IDR_VP_PL3_444AVS16_Buf_2_Rot_270 485 | |
| 519 | #define IDR_VP_PL3_444AVS16_Buf_2_Rot_90 486 | |
| 520 | #define IDR_VP_PL3_444AVS16_Buf_3 487 | |
| 521 | #define IDR_VP_PL3_444AVS16_Buf_3_Rot_180 488 | |
| 522 | #define IDR_VP_PL3_444AVS16_Buf_3_Rot_270 489 | |
| 523 | #define IDR_VP_PL3_444AVS16_Buf_3_Rot_90 490 | |
| 524 | #define IDR_VP_PL3_444AVS16_Buf_4 491 | |
| 525 | #define IDR_VP_PL3_444AVS16_Buf_4_Rot_180 492 | |
| 526 | #define IDR_VP_PL3_444AVS16_Buf_4_Rot_270 493 | |
| 527 | #define IDR_VP_PL3_444AVS16_Buf_4_Rot_90 494 | |
| 528 | #define IDR_VP_PL3_444AVS16_Buf_5 495 | |
| 529 | #define IDR_VP_PL3_444AVS16_Buf_5_Rot_180 496 | |
| 530 | #define IDR_VP_PL3_444AVS16_Buf_5_Rot_270 497 | |
| 531 | #define IDR_VP_PL3_444AVS16_Buf_5_Rot_90 498 | |
| 532 | #define IDR_VP_PL3_444DScale16_Buf_0 499 | |
| 533 | #define IDR_VP_PL3_444DScale16_Buf_0_Rot_180 500 | |
| 534 | #define IDR_VP_PL3_444DScale16_Buf_0_Rot_270 501 | |
| 535 | #define IDR_VP_PL3_444DScale16_Buf_0_Rot_90 502 | |
| 536 | #define IDR_VP_PL3_444DScale16_Buf_1 503 | |
| 537 | #define IDR_VP_PL3_444DScale16_Buf_1_Rot_180 504 | |
| 538 | #define IDR_VP_PL3_444DScale16_Buf_1_Rot_270 505 | |
| 539 | #define IDR_VP_PL3_444DScale16_Buf_1_Rot_90 506 | |
| 540 | #define IDR_VP_PL3_444DScale16_Buf_2 507 | |
| 541 | #define IDR_VP_PL3_444DScale16_Buf_2_Rot_180 508 | |
| 542 | #define IDR_VP_PL3_444DScale16_Buf_2_Rot_270 509 | |
| 543 | #define IDR_VP_PL3_444DScale16_Buf_2_Rot_90 510 | |
| 544 | #define IDR_VP_PL3_444DScale16_Buf_3 511 | |
| 545 | #define IDR_VP_PL3_444DScale16_Buf_3_Rot_180 512 | |
| 546 | #define IDR_VP_PL3_444DScale16_Buf_3_Rot_270 513 | |
| 547 | #define IDR_VP_PL3_444DScale16_Buf_3_Rot_90 514 | |
| 548 | #define IDR_VP_PL3_444DScale16_Buf_4 515 | |
| 549 | #define IDR_VP_PL3_444DScale16_Buf_4_Rot_180 516 | |
| 550 | #define IDR_VP_PL3_444DScale16_Buf_4_Rot_270 517 | |
| 551 | #define IDR_VP_PL3_444DScale16_Buf_4_Rot_90 518 | |
| 552 | #define IDR_VP_PL3_444DScale16_Buf_5 519 | |
| 553 | #define IDR_VP_PL3_444DScale16_Buf_5_Rot_180 520 | |
| 554 | #define IDR_VP_PL3_444DScale16_Buf_5_Rot_270 521 | |
| 555 | #define IDR_VP_PL3_444DScale16_Buf_5_Rot_90 522 | |
| 556 | #define IDR_VP_PL3_444Scale16_Buf_0 523 | |
| 557 | #define IDR_VP_PL3_444Scale16_Buf_0_Rot_180 524 | |
| 558 | #define IDR_VP_PL3_444Scale16_Buf_0_Rot_270 525 | |
| 559 | #define IDR_VP_PL3_444Scale16_Buf_0_Rot_90 526 | |
| 560 | #define IDR_VP_PL3_444Scale16_Buf_1 527 | |
| 561 | #define IDR_VP_PL3_444Scale16_Buf_1_Rot_180 528 | |
| 562 | #define IDR_VP_PL3_444Scale16_Buf_1_Rot_270 529 | |
| 563 | #define IDR_VP_PL3_444Scale16_Buf_1_Rot_90 530 | |
| 564 | #define IDR_VP_PL3_444Scale16_Buf_2 531 | |
| 565 | #define IDR_VP_PL3_444Scale16_Buf_2_Rot_180 532 | |
| 566 | #define IDR_VP_PL3_444Scale16_Buf_2_Rot_270 533 | |
| 567 | #define IDR_VP_PL3_444Scale16_Buf_2_Rot_90 534 | |
| 568 | #define IDR_VP_PL3_444Scale16_Buf_3 535 | |
| 569 | #define IDR_VP_PL3_444Scale16_Buf_3_Rot_180 536 | |
| 570 | #define IDR_VP_PL3_444Scale16_Buf_3_Rot_270 537 | |
| 571 | #define IDR_VP_PL3_444Scale16_Buf_3_Rot_90 538 | |
| 572 | #define IDR_VP_PL3_444Scale16_Buf_4 539 | |
| 573 | #define IDR_VP_PL3_444Scale16_Buf_4_Rot_180 540 | |
| 574 | #define IDR_VP_PL3_444Scale16_Buf_4_Rot_270 541 | |
| 575 | #define IDR_VP_PL3_444Scale16_Buf_4_Rot_90 542 | |
| 576 | #define IDR_VP_PL3_444Scale16_Buf_5 543 | |
| 577 | #define IDR_VP_PL3_444Scale16_Buf_5_Rot_180 544 | |
| 578 | #define IDR_VP_PL3_444Scale16_Buf_5_Rot_270 545 | |
| 579 | #define IDR_VP_PL3_444Scale16_Buf_5_Rot_90 546 | |
| 580 | #define IDR_VP_PL3_444iDScale16_Buf_0 547 | |
| 581 | #define IDR_VP_PL3_444iDScale16_Buf_1 548 | |
| 582 | #define IDR_VP_PL3_444iDScale16_Buf_2 549 | |
| 583 | #define IDR_VP_PL3_444iDScale16_Buf_3 550 | |
| 584 | #define IDR_VP_PL3_444iScale16_Buf_0 551 | |
| 585 | #define IDR_VP_PL3_444iScale16_Buf_0_Rot_180 552 | |
| 586 | #define IDR_VP_PL3_444iScale16_Buf_0_Rot_270 553 | |
| 587 | #define IDR_VP_PL3_444iScale16_Buf_0_Rot_90 554 | |
| 588 | #define IDR_VP_PL3_444iScale16_Buf_1 555 | |
| 589 | #define IDR_VP_PL3_444iScale16_Buf_1_Rot_180 556 | |
| 590 | #define IDR_VP_PL3_444iScale16_Buf_1_Rot_270 557 | |
| 591 | #define IDR_VP_PL3_444iScale16_Buf_1_Rot_90 558 | |
| 592 | #define IDR_VP_PL3_444iScale16_Buf_2 559 | |
| 593 | #define IDR_VP_PL3_444iScale16_Buf_2_Rot_180 560 | |
| 594 | #define IDR_VP_PL3_444iScale16_Buf_2_Rot_270 561 | |
| 595 | #define IDR_VP_PL3_444iScale16_Buf_2_Rot_90 562 | |
| 596 | #define IDR_VP_PL3_444iScale16_Buf_3 563 | |
| 597 | #define IDR_VP_PL3_444iScale16_Buf_3_Rot_180 564 | |
| 598 | #define IDR_VP_PL3_444iScale16_Buf_3_Rot_270 565 | |
| 599 | #define IDR_VP_PL3_444iScale16_Buf_3_Rot_90 566 | |
| 600 | #define IDR_VP_PL3_AVS_Rotate_L0_180 567 | |
| 601 | #define IDR_VP_PL3_AVS_Rotate_L0_270 568 | |
| 602 | #define IDR_VP_PL3_AVS_Rotate_L0_90 569 | |
| 603 | #define IDR_VP_PL3_Scale_Rotate_L0_180 570 | |
| 604 | #define IDR_VP_PL3_Scale_Rotate_L0_270 571 | |
| 605 | #define IDR_VP_PL3_Scale_Rotate_L0_90 572 | |
| 606 | #define IDR_VP_PLY_444DScale16_2f_Buf_0 573 | |
| 607 | #define IDR_VP_PLY_444DScale16_2f_Buf_1 574 | |
| 608 | #define IDR_VP_PLY_444DScale16_2f_Buf_2 575 | |
| 609 | #define IDR_VP_PLY_444DScale16_2f_Buf_3 576 | |
| 610 | #define IDR_VP_PLY_444DScale16_Buf_0 577 | |
| 611 | #define IDR_VP_PLY_444DScale16_Buf_0_Rot_180 578 | |
| 612 | #define IDR_VP_PLY_444DScale16_Buf_0_Rot_270 579 | |
| 613 | #define IDR_VP_PLY_444DScale16_Buf_0_Rot_90 580 | |
| 614 | #define IDR_VP_PLY_444DScale16_Buf_1 581 | |
| 615 | #define IDR_VP_PLY_444DScale16_Buf_1_Rot_180 582 | |
| 616 | #define IDR_VP_PLY_444DScale16_Buf_1_Rot_270 583 | |
| 617 | #define IDR_VP_PLY_444DScale16_Buf_1_Rot_90 584 | |
| 618 | #define IDR_VP_PLY_444DScale16_Buf_2 585 | |
| 619 | #define IDR_VP_PLY_444DScale16_Buf_2_Rot_180 586 | |
| 620 | #define IDR_VP_PLY_444DScale16_Buf_2_Rot_270 587 | |
| 621 | #define IDR_VP_PLY_444DScale16_Buf_2_Rot_90 588 | |
| 622 | #define IDR_VP_PLY_444DScale16_Buf_3 589 | |
| 623 | #define IDR_VP_PLY_444DScale16_Buf_3_Rot_180 590 | |
| 624 | #define IDR_VP_PLY_444DScale16_Buf_3_Rot_270 591 | |
| 625 | #define IDR_VP_PLY_444DScale16_Buf_3_Rot_90 592 | |
| 626 | #define IDR_VP_PartBlend_444_16 593 | |
| 627 | #define IDR_VP_Prepare_LumaKey_SampleUnorm 594 | |
| 628 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4 595 | |
| 629 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_mirror_h 596 | |
| 630 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_mirror_v 597 | |
| 631 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_rot_180 598 | |
| 632 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_rot_270 599 | |
| 633 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_rot_90 600 | |
| 634 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_rot_90_mirror_h 601 | |
| 635 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_rot_90_mirror_v 602 | |
| 636 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th 603 | |
| 637 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_mirror_h 604 | |
| 638 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_mirror_v 605 | |
| 639 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_rot_180 606 | |
| 640 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_rot_270 607 | |
| 641 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_rot_90 608 | |
| 642 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_rot_90_mirror_h 609 | |
| 643 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_rot_90_mirror_v 610 | |
| 644 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio 611 | |
| 645 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_mirror_h 612 | |
| 646 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_mirror_v 613 | |
| 647 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_rot_180 614 | |
| 648 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_rot_270 615 | |
| 649 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_rot_90 616 | |
| 650 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_rot_90_mirror_h 617 | |
| 651 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_rot_90_mirror_v 618 | |
| 652 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8 619 | |
| 653 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_mirror_h 620 | |
| 654 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_mirror_v 621 | |
| 655 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_rot_180 622 | |
| 656 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_rot_270 623 | |
| 657 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_rot_90 624 | |
| 658 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_rot_90_mirror_h 625 | |
| 659 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_rot_90_mirror_v 626 | |
| 660 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16 627 | |
| 661 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_mirror_h 628 | |
| 662 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_mirror_v 629 | |
| 663 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_rot_180 630 | |
| 664 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_rot_270 631 | |
| 665 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_rot_90 632 | |
| 666 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_rot_90_mirror_h 633 | |
| 667 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_rot_90_mirror_v 634 | |
| 668 | #define IDR_VP_RGB2sRGB 635 | |
| 669 | #define IDR_VP_RGBP_DP_DownScaling_8x8 636 | |
| 670 | #define IDR_VP_RGBP_DP_UpScaling_16x16 637 | |
| 671 | #define IDR_VP_Rotate_90_Mirror_AVS_H_L0 638 | |
| 672 | #define IDR_VP_Rotate_90_Mirror_AVS_V_L0 639 | |
| 673 | #define IDR_VP_Rotate_90_Mirror_H_scale_L0 640 | |
| 674 | #define IDR_VP_Rotate_90_Mirror_V_scale_L0 641 | |
| 675 | #define IDR_VP_Rotate_AVS_L0_180 642 | |
| 676 | #define IDR_VP_Rotate_AVS_L0_270 643 | |
| 677 | #define IDR_VP_Rotate_AVS_L0_90 644 | |
| 678 | #define IDR_VP_Rotate_Scale_L0_180 645 | |
| 679 | #define IDR_VP_Rotate_Scale_L0_270 646 | |
| 680 | #define IDR_VP_Rotate_Scale_L0_90 647 | |
| 681 | #define IDR_VP_SIP_Debug 648 | |
| 682 | #define IDR_VP_Save_444AVS16_ARGB 649 | |
| 683 | #define IDR_VP_Save_444AVS16_ARGB_64Byte 650 | |
| 684 | #define IDR_VP_Save_444AVS16_NV12 651 | |
| 685 | #define IDR_VP_Save_444AVS16_NV21 652 | |
| 686 | #define IDR_VP_Save_444AVS16_PA 653 | |
| 687 | #define IDR_VP_Save_444AVS16_PL3 654 | |
| 688 | #define IDR_VP_Save_444AVS16_R10G10B10 655 | |
| 689 | #define IDR_VP_Save_444AVS16_R10G10B10A2 656 | |
| 690 | #define IDR_VP_Save_444AVS16_R10G10B10X2 657 | |
| 691 | #define IDR_VP_Save_444AVS16_RGB 658 | |
| 692 | #define IDR_VP_Save_444AVS16_RGB16 659 | |
| 693 | #define IDR_VP_Save_444AVS16_RGB_64Byte 660 | |
| 694 | #define IDR_VP_Save_444AVS16_SrcAYUV 661 | |
| 695 | #define IDR_VP_Save_444AVS16_XRGB 662 | |
| 696 | #define IDR_VP_Save_444AVS16_XRGB_64Byte 663 | |
| 697 | #define IDR_VP_Save_444Scale16_ARGB 664 | |
| 698 | #define IDR_VP_Save_444Scale16_ARGB_64Byte 665 | |
| 699 | #define IDR_VP_Save_444Scale16_Dither_NV12 666 | |
| 700 | #define IDR_VP_Save_444Scale16_Dither_NV21 667 | |
| 701 | #define IDR_VP_Save_444Scale16_Dither_PA 668 | |
| 702 | #define IDR_VP_Save_444Scale16_Dither_PA_32X16 669 | |
| 703 | #define IDR_VP_Save_444Scale16_Dither_PL3 670 | |
| 704 | #define IDR_VP_Save_444Scale16_Dither_RGB 671 | |
| 705 | #define IDR_VP_Save_444Scale16_Dither_RGB16 672 | |
| 706 | #define IDR_VP_Save_444Scale16_Dither_RGB_64Byte 673 | |
| 707 | #define IDR_VP_Save_444Scale16_Dither_VUYA 674 | |
| 708 | #define IDR_VP_Save_444Scale16_Dither_XRGB 675 | |
| 709 | #define IDR_VP_Save_444Scale16_Dither_XRGB_64Byte 676 | |
| 710 | #define IDR_VP_Save_444Scale16_NV12 677 | |
| 711 | #define IDR_VP_Save_444Scale16_NV21 678 | |
| 712 | #define IDR_VP_Save_444Scale16_P010 679 | |
| 713 | #define IDR_VP_Save_444Scale16_P016 680 | |
| 714 | #define IDR_VP_Save_444Scale16_PA 681 | |
| 715 | #define IDR_VP_Save_444Scale16_PA_32X16 682 | |
| 716 | #define IDR_VP_Save_444Scale16_PL3 683 | |
| 717 | #define IDR_VP_Save_444Scale16_PLY 684 | |
| 718 | #define IDR_VP_Save_444Scale16_R10G10B10 685 | |
| 719 | #define IDR_VP_Save_444Scale16_R10G10B10A2 686 | |
| 720 | #define IDR_VP_Save_444Scale16_R10G10B10X2 687 | |
| 721 | #define IDR_VP_Save_444Scale16_R10G10B10XR 688 | |
| 722 | #define IDR_VP_Save_444Scale16_R10G10B10XRA2 689 | |
| 723 | #define IDR_VP_Save_444Scale16_R10G10B10XRX2 690 | |
| 724 | #define IDR_VP_Save_444Scale16_RGB 691 | |
| 725 | #define IDR_VP_Save_444Scale16_RGB16 692 | |
| 726 | #define IDR_VP_Save_444Scale16_RGBP 693 | |
| 727 | #define IDR_VP_Save_444Scale16_RGB_64Byte 694 | |
| 728 | #define IDR_VP_Save_444Scale16_SrcVUYA 695 | |
| 729 | #define IDR_VP_Save_444Scale16_SrcY416 696 | |
| 730 | #define IDR_VP_Save_444Scale16_VUYA 697 | |
| 731 | #define IDR_VP_Save_444Scale16_XRGB 698 | |
| 732 | #define IDR_VP_Save_444Scale16_XRGB_64Byte 699 | |
| 733 | #define IDR_VP_Save_444Scale16_Y210 700 | |
| 734 | #define IDR_VP_Save_444Scale16_Y216 701 | |
| 735 | #define IDR_VP_Save_444Scale16_Y410 702 | |
| 736 | #define IDR_VP_Save_444Scale16_Y416 703 | |
| 737 | #define IDR_VP_Save_ARGB_16x16 704 | |
| 738 | #define IDR_VP_Save_ARGB_4x4 705 | |
| 739 | #define IDR_VP_Save_ARGB_8x8 706 | |
| 740 | #define IDR_VP_Save_NV12_16x16 707 | |
| 741 | #define IDR_VP_Save_NV12_4x4 708 | |
| 742 | #define IDR_VP_Save_NV12_8x8 709 | |
| 743 | #define IDR_VP_Save_RGBP_16x16 710 | |
| 744 | #define IDR_VP_Save_RGBP_4x4 711 | |
| 745 | #define IDR_VP_Save_RGBP_8x8 712 | |
| 746 | #define IDR_VP_Secure_Block_Copy 713 | |
| 747 | #define IDR_VP_Set_Buf0_Buf4 714 | |
| 748 | #define IDR_VP_Set_Buf1_Buf5 715 | |
| 749 | #define IDR_VP_Set_Buf2_Buf4 716 | |
| 750 | #define IDR_VP_Set_Buf3_Buf5 717 | |
| 751 | #define IDR_VP_Set_CSC_Src_Buf0 718 | |
| 752 | #define IDR_VP_Set_CSC_Src_Buf1 719 | |
| 753 | #define IDR_VP_Set_CSC_Src_Buf2 720 | |
| 754 | #define IDR_VP_Set_CSC_Src_Buf3 721 | |
| 755 | #define IDR_VP_Set_CSC_Src_Buf4 722 | |
| 756 | #define IDR_VP_Set_CSC_Src_Buf5 723 | |
| 757 | #define IDR_VP_Set_CURBE_CSC_Coeff 724 | |
| 758 | #define IDR_VP_Set_ColorE_Src_Buf0 725 | |
| 759 | #define IDR_VP_Set_ColorE_Src_Buf1 726 | |
| 760 | #define IDR_VP_Set_ColorE_Src_Buf2 727 | |
| 761 | #define IDR_VP_Set_ColorE_Src_Buf3 728 | |
| 762 | #define IDR_VP_Set_Dest_Surf_Indexes_Primary 729 | |
| 763 | #define IDR_VP_Set_Dest_Surf_Indexes_Secondary 730 | |
| 764 | #define IDR_VP_Set_GammaC_Src_Buf0 731 | |
| 765 | #define IDR_VP_Set_GammaC_Src_Buf1 732 | |
| 766 | #define IDR_VP_Set_GammaC_Src_Buf2 733 | |
| 767 | #define IDR_VP_Set_GammaC_Src_Buf3 734 | |
| 768 | #define IDR_VP_Set_Layer_0 735 | |
| 769 | #define IDR_VP_Set_Layer_1 736 | |
| 770 | #define IDR_VP_Set_Layer_1_AVS 737 | |
| 771 | #define IDR_VP_Set_Layer_2 738 | |
| 772 | #define IDR_VP_Set_Layer_3 739 | |
| 773 | #define IDR_VP_Set_Layer_4 740 | |
| 774 | #define IDR_VP_Set_Layer_5 741 | |
| 775 | #define IDR_VP_Set_Layer_6 742 | |
| 776 | #define IDR_VP_Set_Layer_7 743 | |
| 777 | #define IDR_VP_Set_Patched_CSC_Coeff 744 | |
| 778 | #define IDR_VP_Set_Scale_Buf_0123_Colorfill 745 | |
| 779 | #define IDR_VP_Set_Sec_Half_Buf45 746 | |
| 780 | #define IDR_VP_Shuffle_444AVS16_Buf_0 747 | |
| 781 | #define IDR_VP_Shuffle_444AVS16_Buf_1 748 | |
| 782 | #define IDR_VP_Shuffle_444AVS16_Buf_2 749 | |
| 783 | #define IDR_VP_Shuffle_444AVS16_Buf_3 750 | |
| 784 | #define IDR_VP_Shuffle_444AVS16_Buf_4 751 | |
| 785 | #define IDR_VP_Shuffle_444AVS16_Buf_5 752 | |
| 786 | #define IDR_VP_SrcBlend_444_16 753 | |
| 787 | #define IDR_VP_SrcBlend_4bits_444_16 754 | |
| 788 | #define IDR_VP_UpdateDNState 755 | |
| 789 | #define IDR_VP_VP_Setup 756 | |
| 790 | #define IDR_VP_VP_Setup_MediaWalker 757 | |
| 791 | #define IDR_VP_VP_Setup_MediaWalker_32X16_Design 758 | |
| 792 | #define IDR_VP_VP_Setup_MediaWalker_32x32_Color 759 | |
| 793 | #define IDR_VP_XOR_Composite_444_16 760 | |
| 794 | #define IDR_VP_XOR_Mono_Composite_444_16 761 | |
| 795 | #define IDR_VP_Y210_444DScale16_Buf_0 762 | |
| 796 | #define IDR_VP_Y210_444DScale16_Buf_0_Rot_180 763 | |
| 797 | #define IDR_VP_Y210_444DScale16_Buf_0_Rot_270 764 | |
| 798 | #define IDR_VP_Y210_444DScale16_Buf_0_Rot_90 765 | |
| 799 | #define IDR_VP_Y210_444DScale16_Buf_1 766 | |
| 800 | #define IDR_VP_Y210_444DScale16_Buf_1_Rot_180 767 | |
| 801 | #define IDR_VP_Y210_444DScale16_Buf_1_Rot_270 768 | |
| 802 | #define IDR_VP_Y210_444DScale16_Buf_1_Rot_90 769 | |
| 803 | #define IDR_VP_Y210_444DScale16_Buf_2 770 | |
| 804 | #define IDR_VP_Y210_444DScale16_Buf_2_Rot_180 771 | |
| 805 | #define IDR_VP_Y210_444DScale16_Buf_2_Rot_270 772 | |
| 806 | #define IDR_VP_Y210_444DScale16_Buf_2_Rot_90 773 | |
| 807 | #define IDR_VP_Y210_444DScale16_Buf_3 774 | |
| 808 | #define IDR_VP_Y210_444DScale16_Buf_3_Rot_180 775 | |
| 809 | #define IDR_VP_Y210_444DScale16_Buf_3_Rot_270 776 | |
| 810 | #define IDR_VP_Y210_444DScale16_Buf_3_Rot_90 777 | |
| 811 | #define IDR_VP_Y210_444DScale16_Buf_4 778 | |
| 812 | #define IDR_VP_Y210_444DScale16_Buf_4_Rot_180 779 | |
| 813 | #define IDR_VP_Y210_444DScale16_Buf_4_Rot_270 780 | |
| 814 | #define IDR_VP_Y210_444DScale16_Buf_4_Rot_90 781 | |
| 815 | #define IDR_VP_Y210_444DScale16_Buf_5 782 | |
| 816 | #define IDR_VP_Y210_444DScale16_Buf_5_Rot_180 783 | |
| 817 | #define IDR_VP_Y210_444DScale16_Buf_5_Rot_270 784 | |
| 818 | #define IDR_VP_Y210_444DScale16_Buf_5_Rot_90 785 | |
| 819 | #define IDR_VP_Y210_444Scale16_Buf_0 786 | |
| 820 | #define IDR_VP_Y210_444Scale16_Buf_0_Rot_180 787 | |
| 821 | #define IDR_VP_Y210_444Scale16_Buf_0_Rot_270 788 | |
| 822 | #define IDR_VP_Y210_444Scale16_Buf_0_Rot_90 789 | |
| 823 | #define IDR_VP_Y210_444Scale16_Buf_1 790 | |
| 824 | #define IDR_VP_Y210_444Scale16_Buf_1_Rot_180 791 | |
| 825 | #define IDR_VP_Y210_444Scale16_Buf_1_Rot_270 792 | |
| 826 | #define IDR_VP_Y210_444Scale16_Buf_1_Rot_90 793 | |
| 827 | #define IDR_VP_Y210_444Scale16_Buf_2 794 | |
| 828 | #define IDR_VP_Y210_444Scale16_Buf_2_Rot_180 795 | |
| 829 | #define IDR_VP_Y210_444Scale16_Buf_2_Rot_270 796 | |
| 830 | #define IDR_VP_Y210_444Scale16_Buf_2_Rot_90 797 | |
| 831 | #define IDR_VP_Y210_444Scale16_Buf_3 798 | |
| 832 | #define IDR_VP_Y210_444Scale16_Buf_3_Rot_180 799 | |
| 833 | #define IDR_VP_Y210_444Scale16_Buf_3_Rot_270 800 | |
| 834 | #define IDR_VP_Y210_444Scale16_Buf_3_Rot_90 801 | |
| 835 | #define IDR_VP_Y210_444Scale16_Buf_4 802 | |
| 836 | #define IDR_VP_Y210_444Scale16_Buf_4_Rot_180 803 | |
| 837 | #define IDR_VP_Y210_444Scale16_Buf_4_Rot_270 804 | |
| 838 | #define IDR_VP_Y210_444Scale16_Buf_4_Rot_90 805 | |
| 839 | #define IDR_VP_Y210_444Scale16_Buf_5 806 | |
| 840 | #define IDR_VP_Y210_444Scale16_Buf_5_Rot_180 807 | |
| 841 | #define IDR_VP_Y210_444Scale16_Buf_5_Rot_270 808 | |
| 842 | #define IDR_VP_Y210_444Scale16_Buf_5_Rot_90 809 | |
| 843 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_0 810 | |
| 844 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_0_Rot_180 811 | |
| 845 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_0_Rot_270 812 | |
| 846 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_0_Rot_90 813 | |
| 847 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_1 814 | |
| 848 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_1_Rot_180 815 | |
| 849 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_1_Rot_270 816 | |
| 850 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_1_Rot_90 817 | |
| 851 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_2 818 | |
| 852 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_2_Rot_180 819 | |
| 853 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_2_Rot_270 820 | |
| 854 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_2_Rot_90 821 | |
| 855 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_3 822 | |
| 856 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_3_Rot_180 823 | |
| 857 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_3_Rot_270 824 | |
| 858 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_3_Rot_90 825 | |
| 859 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_4 826 | |
| 860 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_4_Rot_180 827 | |
| 861 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_4_Rot_270 828 | |
| 862 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_4_Rot_90 829 | |
| 863 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_5 830 | |
| 864 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_5_Rot_180 831 | |
| 865 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_5_Rot_270 832 | |
| 866 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_5_Rot_90 833 | |
| 867 | #define IDR_VP_Y410_444AVS16_Buf_0 834 | |
| 868 | #define IDR_VP_Y410_444AVS16_Buf_0_Rot_180 835 | |
| 869 | #define IDR_VP_Y410_444AVS16_Buf_0_Rot_270 836 | |
| 870 | #define IDR_VP_Y410_444AVS16_Buf_0_Rot_90 837 | |
| 871 | #define IDR_VP_Y410_444AVS16_Buf_1 838 | |
| 872 | #define IDR_VP_Y410_444AVS16_Buf_1_Rot_180 839 | |
| 873 | #define IDR_VP_Y410_444AVS16_Buf_1_Rot_270 840 | |
| 874 | #define IDR_VP_Y410_444AVS16_Buf_1_Rot_90 841 | |
| 875 | #define IDR_VP_Y410_444AVS16_Buf_2 842 | |
| 876 | #define IDR_VP_Y410_444AVS16_Buf_2_Rot_180 843 | |
| 877 | #define IDR_VP_Y410_444AVS16_Buf_2_Rot_270 844 | |
| 878 | #define IDR_VP_Y410_444AVS16_Buf_2_Rot_90 845 | |
| 879 | #define IDR_VP_Y410_444AVS16_Buf_3 846 | |
| 880 | #define IDR_VP_Y410_444AVS16_Buf_3_Rot_180 847 | |
| 881 | #define IDR_VP_Y410_444AVS16_Buf_3_Rot_270 848 | |
| 882 | #define IDR_VP_Y410_444AVS16_Buf_3_Rot_90 849 | |
| 883 | #define IDR_VP_Y410_444AVS16_Buf_4 850 | |
| 884 | #define IDR_VP_Y410_444AVS16_Buf_4_Rot_180 851 | |
| 885 | #define IDR_VP_Y410_444AVS16_Buf_4_Rot_270 852 | |
| 886 | #define IDR_VP_Y410_444AVS16_Buf_4_Rot_90 853 | |
| 887 | #define IDR_VP_Y410_444AVS16_Buf_5 854 | |
| 888 | #define IDR_VP_Y410_444AVS16_Buf_5_Rot_180 855 | |
| 889 | #define IDR_VP_Y410_444AVS16_Buf_5_Rot_270 856 | |
| 890 | #define IDR_VP_Y410_444AVS16_Buf_5_Rot_90 857 | |
| 891 | #define IDR_VP_Y410_444DScale16_Buf_0 858 | |
| 892 | #define IDR_VP_Y410_444DScale16_Buf_0_Rot_180 859 | |
| 893 | #define IDR_VP_Y410_444DScale16_Buf_0_Rot_270 860 | |
| 894 | #define IDR_VP_Y410_444DScale16_Buf_0_Rot_90 861 | |
| 895 | #define IDR_VP_Y410_444DScale16_Buf_1 862 | |
| 896 | #define IDR_VP_Y410_444DScale16_Buf_1_Rot_180 863 | |
| 897 | #define IDR_VP_Y410_444DScale16_Buf_1_Rot_270 864 | |
| 898 | #define IDR_VP_Y410_444DScale16_Buf_1_Rot_90 865 | |
| 899 | #define IDR_VP_Y410_444DScale16_Buf_2 866 | |
| 900 | #define IDR_VP_Y410_444DScale16_Buf_2_Rot_180 867 | |
| 901 | #define IDR_VP_Y410_444DScale16_Buf_2_Rot_270 868 | |
| 902 | #define IDR_VP_Y410_444DScale16_Buf_2_Rot_90 869 | |
| 903 | #define IDR_VP_Y410_444DScale16_Buf_3 870 | |
| 904 | #define IDR_VP_Y410_444DScale16_Buf_3_Rot_180 871 | |
| 905 | #define IDR_VP_Y410_444DScale16_Buf_3_Rot_270 872 | |
| 906 | #define IDR_VP_Y410_444DScale16_Buf_3_Rot_90 873 | |
| 907 | #define IDR_VP_Y410_444DScale16_Buf_4 874 | |
| 908 | #define IDR_VP_Y410_444DScale16_Buf_4_Rot_180 875 | |
| 909 | #define IDR_VP_Y410_444DScale16_Buf_4_Rot_270 876 | |
| 910 | #define IDR_VP_Y410_444DScale16_Buf_4_Rot_90 877 | |
| 911 | #define IDR_VP_Y410_444DScale16_Buf_5 878 | |
| 912 | #define IDR_VP_Y410_444DScale16_Buf_5_Rot_180 879 | |
| 913 | #define IDR_VP_Y410_444DScale16_Buf_5_Rot_270 880 | |
| 914 | #define IDR_VP_Y410_444DScale16_Buf_5_Rot_90 881 | |
| 915 | #define IDR_VP_Y410_444Scale16_Buf_0 882 | |
| 916 | #define IDR_VP_Y410_444Scale16_Buf_0_Rot_180 883 | |
| 917 | #define IDR_VP_Y410_444Scale16_Buf_0_Rot_270 884 | |
| 918 | #define IDR_VP_Y410_444Scale16_Buf_0_Rot_90 885 | |
| 919 | #define IDR_VP_Y410_444Scale16_Buf_1 886 | |
| 920 | #define IDR_VP_Y410_444Scale16_Buf_1_Rot_180 887 | |
| 921 | #define IDR_VP_Y410_444Scale16_Buf_1_Rot_270 888 | |
| 922 | #define IDR_VP_Y410_444Scale16_Buf_1_Rot_90 889 | |
| 923 | #define IDR_VP_Y410_444Scale16_Buf_2 890 | |
| 924 | #define IDR_VP_Y410_444Scale16_Buf_2_Rot_180 891 | |
| 925 | #define IDR_VP_Y410_444Scale16_Buf_2_Rot_270 892 | |
| 926 | #define IDR_VP_Y410_444Scale16_Buf_2_Rot_90 893 | |
| 927 | #define IDR_VP_Y410_444Scale16_Buf_3 894 | |
| 928 | #define IDR_VP_Y410_444Scale16_Buf_3_Rot_180 895 | |
| 929 | #define IDR_VP_Y410_444Scale16_Buf_3_Rot_270 896 | |
| 930 | #define IDR_VP_Y410_444Scale16_Buf_3_Rot_90 897 | |
| 931 | #define IDR_VP_Y410_444Scale16_Buf_4 898 | |
| 932 | #define IDR_VP_Y410_444Scale16_Buf_4_Rot_180 899 | |
| 933 | #define IDR_VP_Y410_444Scale16_Buf_4_Rot_270 900 | |
| 934 | #define IDR_VP_Y410_444Scale16_Buf_4_Rot_90 901 | |
| 935 | #define IDR_VP_Y410_444Scale16_Buf_5 902 | |
| 936 | #define IDR_VP_Y410_444Scale16_Buf_5_Rot_180 903 | |
| 937 | #define IDR_VP_Y410_444Scale16_Buf_5_Rot_270 904 | |
| 938 | #define IDR_VP_Y410_444Scale16_Buf_5_Rot_90 905 | |
| 939 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_0 906 | |
| 940 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_0_Rot_180 907 | |
| 941 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_0_Rot_270 908 | |
| 942 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_0_Rot_90 909 | |
| 943 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_1 910 | |
| 944 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_1_Rot_180 911 | |
| 945 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_1_Rot_270 912 | |
| 946 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_1_Rot_90 913 | |
| 947 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_2 914 | |
| 948 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_2_Rot_180 915 | |
| 949 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_2_Rot_270 916 | |
| 950 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_2_Rot_90 917 | |
| 951 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_3 918 | |
| 952 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_3_Rot_180 919 | |
| 953 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_3_Rot_270 920 | |
| 954 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_3_Rot_90 921 | |
| 955 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_4 922 | |
| 956 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_4_Rot_180 923 | |
| 957 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_4_Rot_270 924 | |
| 958 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_4_Rot_90 925 | |
| 959 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_5 926 | |
| 960 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_5_Rot_180 927 | |
| 961 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_5_Rot_270 928 | |
| 962 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_5_Rot_90 929 | |
| 963 | #define IDR_VP_camera_pipe_CalcParams 930 | |
| 964 | #define IDR_VP_fast_avs_1_to_n 931 | |
| 965 | #define IDR_VP_return 932 | |
| 966 | #define IDR_VP_sampler_scaling 933 | |
| 967 | #define IDR_VP_zzz_preproduction 934 | |
| 968 | #define IDR_VP_zzz_preproduction_ALLPL2Copy_Gen 935 | |
| 969 | #define IDR_VP_zzz_preproduction_HDR_mandatory_Gen 936 | |
| 970 | #define IDR_VP_zzz_preproduction_HDR_per_frame_stat_Gen 937 | |
| 971 | #define IDR_VP_zzz_preproduction_gcBltPS_32_To_128_Mirror_Gen 938 | |
| 972 | #define IDR_VP_zzz_preproduction_gcBltPS_64_To_128_Mirror_Gen 939 | |
| 973 | #define IDR_VP_zzz_preproduction_gcBltPS_Gen 940 | |
| 974 | #define IDR_VP_zzz_preproduction_gcBlt_D11 941 | |
| 975 | #define IDR_VP_zzz_preproduction_gcClearNoReplicatePS_Gen 942 | |
| 976 | #define IDR_VP_zzz_preproduction_gcClearReplicatePS_Gen 943 | |
| 977 | #define IDR_VP_zzz_preproduction_gcClear_NoReplicate_D11 944 | |
| 978 | #define IDR_VP_zzz_preproduction_gcClear_Replicate_D11 945 | |
| 979 | #define IDR_VP_zzz_preproduction_gcColorFillNoReplicatePS_Gen 946 | |
| 980 | #define IDR_VP_zzz_preproduction_gcColorFillReplicatePS_Gen 947 | |
| 981 | #define IDR_VP_zzz_preproduction_gcFastClearReplicatePS_Gen 948 | |
| 982 | #define IDR_VP_zzz_preproduction_gcFastClear_Replicate_D11 949 | |
| 983 | #define IDR_VP_zzz_preproduction_gcResourceCopy_D11 950 | |
| 984 | #define IDR_VP_zzz_production 951 | |
| 985 | #define IDR_VP_zzz_production_ALLPL2Copy_Gen 952 | |
| 986 | #define IDR_VP_zzz_production_HDR_mandatory_Gen 953 | |
| 987 | #define IDR_VP_zzz_production_HDR_per_frame_stat_Gen 954 | |
| 988 | #define IDR_VP_zzz_production_gcBltPS_32_To_128_Mirror_Gen 955 | |
| 989 | #define IDR_VP_zzz_production_gcBltPS_64_To_128_Mirror_Gen 956 | |
| 990 | #define IDR_VP_zzz_production_gcBltPS_Gen 957 | |
| 991 | #define IDR_VP_zzz_production_gcBlt_D11 958 | |
| 992 | #define IDR_VP_zzz_production_gcClearNoReplicatePS_Gen 959 | |
| 993 | #define IDR_VP_zzz_production_gcClearReplicatePS_Gen 960 | |
| 994 | #define IDR_VP_zzz_production_gcClear_NoReplicate_D11 961 | |
| 995 | #define IDR_VP_zzz_production_gcClear_Replicate_D11 962 | |
| 996 | #define IDR_VP_zzz_production_gcColorFillNoReplicatePS_Gen 963 | |
| 997 | #define IDR_VP_zzz_production_gcColorFillReplicatePS_Gen 964 | |
| 998 | #define IDR_VP_zzz_production_gcFastClearReplicatePS_Gen 965 | |
| 999 | #define IDR_VP_zzz_production_gcFastClear_Replicate_D11 966 | |
| 1000 | #define IDR_VP_zzz_production_gcResourceCopy_D11 967 | |
| 1001 | #define IDR_VP_TOTAL_NUM_KERNELS 968 | |
| 77 | #define IDR_VP_CopyKernel_1D_to_2D_genx 44 | |
| 78 | #define IDR_VP_CopyKernel_2D_to_1D_NV12_genx 45 | |
| 79 | #define IDR_VP_CopyKernel_2D_to_1D_RGBP_genx 46 | |
| 80 | #define IDR_VP_CopyKernel_2D_to_1D_genx 47 | |
| 81 | #define IDR_VP_CopyKernel_2D_to_2D_NV12_genx 48 | |
| 82 | #define IDR_VP_CopyKernel_2D_to_2D_RGBP_genx 49 | |
| 83 | #define IDR_VP_CopyKernel_2D_to_2D_genx 50 | |
| 84 | #define IDR_VP_DP_FC_Setup_Walker_16x16 51 | |
| 85 | #define IDR_VP_DP_FC_Setup_Walker_4x4 52 | |
| 86 | #define IDR_VP_DP_FC_Setup_Walker_8x8 53 | |
| 87 | #define IDR_VP_EOT 54 | |
| 88 | #define IDR_VP_FMD_Summation 55 | |
| 89 | #define IDR_VP_FRC_Clean_Map 56 | |
| 90 | #define IDR_VP_FRC_GMV_Detection 57 | |
| 91 | #define IDR_VP_FRC_GMV_Sanity_Check 58 | |
| 92 | #define IDR_VP_FRC_GradUV 59 | |
| 93 | #define IDR_VP_FRC_GradY 60 | |
| 94 | #define IDR_VP_FRC_MC 61 | |
| 95 | #define IDR_VP_FRC_ME_Level1 62 | |
| 96 | #define IDR_VP_FRC_ME_Level2 63 | |
| 97 | #define IDR_VP_FRC_ME_Level3 64 | |
| 98 | #define IDR_VP_FRC_MV_Level1 65 | |
| 99 | #define IDR_VP_FRC_MV_Level2 66 | |
| 100 | #define IDR_VP_FRC_MV_Level3 67 | |
| 101 | #define IDR_VP_FRC_PS 68 | |
| 102 | #define IDR_VP_FRC_SPD_Map 69 | |
| 103 | #define IDR_VP_FRC_TempDiff 70 | |
| 104 | #define IDR_VP_FRC_TempDiff_HD 71 | |
| 105 | #define IDR_VP_FRC_WSD 72 | |
| 106 | #define IDR_VP_GammaC 73 | |
| 107 | #define IDR_VP_GeoCorrection 74 | |
| 108 | #define IDR_VP_HDR_mandatory 75 | |
| 109 | #define IDR_VP_HDR_per_frame_stat 76 | |
| 110 | #define IDR_VP_HDR_preprocess 77 | |
| 111 | #define IDR_VP_IS_DS 78 | |
| 112 | #define IDR_VP_IS_FW 79 | |
| 113 | #define IDR_VP_IS_GMC 80 | |
| 114 | #define IDR_VP_IS_ME 81 | |
| 115 | #define IDR_VP_Interlace_420_16_Buf_0 82 | |
| 116 | #define IDR_VP_Interlace_420_16_Buf_1 83 | |
| 117 | #define IDR_VP_Interlace_420_16_Buf_2 84 | |
| 118 | #define IDR_VP_Interlace_420_16_Buf_3 85 | |
| 119 | #define IDR_VP_Interlace_444AVS16_Buf_0 86 | |
| 120 | #define IDR_VP_Interlace_444AVS16_Buf_1 87 | |
| 121 | #define IDR_VP_Interlace_444AVS16_Buf_2 88 | |
| 122 | #define IDR_VP_Interlace_444AVS16_Buf_3 89 | |
| 123 | #define IDR_VP_Interlace_444_16_Buf_0 90 | |
| 124 | #define IDR_VP_Interlace_444_16_Buf_1 91 | |
| 125 | #define IDR_VP_Interlace_444_16_Buf_2 92 | |
| 126 | #define IDR_VP_Interlace_444_16_Buf_3 93 | |
| 127 | #define IDR_VP_LACE_HIST_SUM 94 | |
| 128 | #define IDR_VP_LACE_LUT 95 | |
| 129 | #define IDR_VP_LACE_PWLF 96 | |
| 130 | #define IDR_VP_LACE_STD 97 | |
| 131 | #define IDR_VP_LinkFile 98 | |
| 132 | #define IDR_VP_Mirror_AVS_H_L0 99 | |
| 133 | #define IDR_VP_Mirror_AVS_V_L0 100 | |
| 134 | #define IDR_VP_Mirror_H_YUV 101 | |
| 135 | #define IDR_VP_Mirror_H_YUVA 102 | |
| 136 | #define IDR_VP_Mirror_scale_H_L0 103 | |
| 137 | #define IDR_VP_Mirror_scale_V_L0 104 | |
| 138 | #define IDR_VP_NV12_DP_DownScaling_4x4 105 | |
| 139 | #define IDR_VP_NV12_DP_DownScaling_4x4_mirror_h 106 | |
| 140 | #define IDR_VP_NV12_DP_DownScaling_4x4_mirror_v 107 | |
| 141 | #define IDR_VP_NV12_DP_DownScaling_4x4_rot_180 108 | |
| 142 | #define IDR_VP_NV12_DP_DownScaling_4x4_rot_270 109 | |
| 143 | #define IDR_VP_NV12_DP_DownScaling_4x4_rot_90 110 | |
| 144 | #define IDR_VP_NV12_DP_DownScaling_4x4_rot_90_mirror_h 111 | |
| 145 | #define IDR_VP_NV12_DP_DownScaling_4x4_rot_90_mirror_v 112 | |
| 146 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th 113 | |
| 147 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_mirror_h 114 | |
| 148 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_mirror_v 115 | |
| 149 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_rot_180 116 | |
| 150 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_rot_270 117 | |
| 151 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_rot_90 118 | |
| 152 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_rot_90_mirror_h 119 | |
| 153 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_1_8th_rot_90_mirror_v 120 | |
| 154 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio 121 | |
| 155 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_mirror_h 122 | |
| 156 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_mirror_v 123 | |
| 157 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_rot_180 124 | |
| 158 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_rot_270 125 | |
| 159 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_rot_90 126 | |
| 160 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_rot_90_mirror_h 127 | |
| 161 | #define IDR_VP_NV12_DP_DownScaling_4x4_scale_to_any_ratio_rot_90_mirror_v 128 | |
| 162 | #define IDR_VP_NV12_DP_DownScaling_8x8 129 | |
| 163 | #define IDR_VP_NV12_DP_DownScaling_8x8_mirror_h 130 | |
| 164 | #define IDR_VP_NV12_DP_DownScaling_8x8_mirror_v 131 | |
| 165 | #define IDR_VP_NV12_DP_DownScaling_8x8_rot_180 132 | |
| 166 | #define IDR_VP_NV12_DP_DownScaling_8x8_rot_270 133 | |
| 167 | #define IDR_VP_NV12_DP_DownScaling_8x8_rot_90 134 | |
| 168 | #define IDR_VP_NV12_DP_DownScaling_8x8_rot_90_mirror_h 135 | |
| 169 | #define IDR_VP_NV12_DP_DownScaling_8x8_rot_90_mirror_v 136 | |
| 170 | #define IDR_VP_NV12_DP_UpScaling_16x16 137 | |
| 171 | #define IDR_VP_NV12_DP_UpScaling_16x16_mirror_h 138 | |
| 172 | #define IDR_VP_NV12_DP_UpScaling_16x16_mirror_v 139 | |
| 173 | #define IDR_VP_NV12_DP_UpScaling_16x16_rot_180 140 | |
| 174 | #define IDR_VP_NV12_DP_UpScaling_16x16_rot_270 141 | |
| 175 | #define IDR_VP_NV12_DP_UpScaling_16x16_rot_90 142 | |
| 176 | #define IDR_VP_NV12_DP_UpScaling_16x16_rot_90_mirror_h 143 | |
| 177 | #define IDR_VP_NV12_DP_UpScaling_16x16_rot_90_mirror_v 144 | |
| 178 | #define IDR_VP_NV12_DP_rotation_avg 145 | |
| 179 | #define IDR_VP_NV12_DP_rotation_nv12 146 | |
| 180 | #define IDR_VP_NV12_DP_rotation_rep 147 | |
| 181 | #define IDR_VP_P010_444Dscale16_Buf_0 148 | |
| 182 | #define IDR_VP_P010_444Dscale16_Buf_0_Rot_180 149 | |
| 183 | #define IDR_VP_P010_444Dscale16_Buf_0_Rot_270 150 | |
| 184 | #define IDR_VP_P010_444Dscale16_Buf_0_Rot_90 151 | |
| 185 | #define IDR_VP_P010_444Dscale16_Buf_1 152 | |
| 186 | #define IDR_VP_P010_444Dscale16_Buf_1_Rot_180 153 | |
| 187 | #define IDR_VP_P010_444Dscale16_Buf_1_Rot_270 154 | |
| 188 | #define IDR_VP_P010_444Dscale16_Buf_1_Rot_90 155 | |
| 189 | #define IDR_VP_P010_444Dscale16_Buf_2 156 | |
| 190 | #define IDR_VP_P010_444Dscale16_Buf_2_Rot_180 157 | |
| 191 | #define IDR_VP_P010_444Dscale16_Buf_2_Rot_270 158 | |
| 192 | #define IDR_VP_P010_444Dscale16_Buf_2_Rot_90 159 | |
| 193 | #define IDR_VP_P010_444Dscale16_Buf_3 160 | |
| 194 | #define IDR_VP_P010_444Dscale16_Buf_3_Rot_180 161 | |
| 195 | #define IDR_VP_P010_444Dscale16_Buf_3_Rot_270 162 | |
| 196 | #define IDR_VP_P010_444Dscale16_Buf_3_Rot_90 163 | |
| 197 | #define IDR_VP_PA_444AVS16_Buf_0 164 | |
| 198 | #define IDR_VP_PA_444AVS16_Buf_0_Rot_180 165 | |
| 199 | #define IDR_VP_PA_444AVS16_Buf_0_Rot_270 166 | |
| 200 | #define IDR_VP_PA_444AVS16_Buf_0_Rot_90 167 | |
| 201 | #define IDR_VP_PA_444AVS16_Buf_1 168 | |
| 202 | #define IDR_VP_PA_444AVS16_Buf_1_Rot_180 169 | |
| 203 | #define IDR_VP_PA_444AVS16_Buf_1_Rot_270 170 | |
| 204 | #define IDR_VP_PA_444AVS16_Buf_1_Rot_90 171 | |
| 205 | #define IDR_VP_PA_444AVS16_Buf_2 172 | |
| 206 | #define IDR_VP_PA_444AVS16_Buf_2_Rot_180 173 | |
| 207 | #define IDR_VP_PA_444AVS16_Buf_2_Rot_270 174 | |
| 208 | #define IDR_VP_PA_444AVS16_Buf_2_Rot_90 175 | |
| 209 | #define IDR_VP_PA_444AVS16_Buf_3 176 | |
| 210 | #define IDR_VP_PA_444AVS16_Buf_3_Rot_180 177 | |
| 211 | #define IDR_VP_PA_444AVS16_Buf_3_Rot_270 178 | |
| 212 | #define IDR_VP_PA_444AVS16_Buf_3_Rot_90 179 | |
| 213 | #define IDR_VP_PA_444AVS16_Buf_4 180 | |
| 214 | #define IDR_VP_PA_444AVS16_Buf_4_Rot_180 181 | |
| 215 | #define IDR_VP_PA_444AVS16_Buf_4_Rot_270 182 | |
| 216 | #define IDR_VP_PA_444AVS16_Buf_4_Rot_90 183 | |
| 217 | #define IDR_VP_PA_444AVS16_Buf_5 184 | |
| 218 | #define IDR_VP_PA_444AVS16_Buf_5_Rot_180 185 | |
| 219 | #define IDR_VP_PA_444AVS16_Buf_5_Rot_270 186 | |
| 220 | #define IDR_VP_PA_444AVS16_Buf_5_Rot_90 187 | |
| 221 | #define IDR_VP_PA_444AVS16_HDC_DW_PLANAR_420_8_Buf_0 188 | |
| 222 | #define IDR_VP_PA_444AVS16_HDC_DW_PLANAR_420_8_Buf_1 189 | |
| 223 | #define IDR_VP_PA_444AVS16_HDC_DW_PLANAR_420_8_Buf_2 190 | |
| 224 | #define IDR_VP_PA_444AVS16_HDC_DW_PLANAR_420_8_Buf_3 191 | |
| 225 | #define IDR_VP_PA_444AVS16_HDC_DW_Y8_UNORM_Buf_0 192 | |
| 226 | #define IDR_VP_PA_444AVS16_HDC_DW_Y8_UNORM_Buf_1 193 | |
| 227 | #define IDR_VP_PA_444AVS16_HDC_DW_Y8_UNORM_Buf_2 194 | |
| 228 | #define IDR_VP_PA_444AVS16_HDC_DW_Y8_UNORM_Buf_3 195 | |
| 229 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_NORMAL_Buf_0 196 | |
| 230 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_NORMAL_Buf_1 197 | |
| 231 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_NORMAL_Buf_2 198 | |
| 232 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_NORMAL_Buf_3 199 | |
| 233 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUVY_Buf_0 200 | |
| 234 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUVY_Buf_1 201 | |
| 235 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUVY_Buf_2 202 | |
| 236 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUVY_Buf_3 203 | |
| 237 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUV_Buf_0 204 | |
| 238 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUV_Buf_1 205 | |
| 239 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUV_Buf_2 206 | |
| 240 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPUV_Buf_3 207 | |
| 241 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPY_Buf_0 208 | |
| 242 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPY_Buf_1 209 | |
| 243 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPY_Buf_2 210 | |
| 244 | #define IDR_VP_PA_444AVS16_HDC_DW_YCRCB_SWAPY_Buf_3 211 | |
| 245 | #define IDR_VP_PA_444DScale16_Buf_0 212 | |
| 246 | #define IDR_VP_PA_444DScale16_Buf_0_Rot_180 213 | |
| 247 | #define IDR_VP_PA_444DScale16_Buf_0_Rot_270 214 | |
| 248 | #define IDR_VP_PA_444DScale16_Buf_0_Rot_90 215 | |
| 249 | #define IDR_VP_PA_444DScale16_Buf_1 216 | |
| 250 | #define IDR_VP_PA_444DScale16_Buf_1_Rot_180 217 | |
| 251 | #define IDR_VP_PA_444DScale16_Buf_1_Rot_270 218 | |
| 252 | #define IDR_VP_PA_444DScale16_Buf_1_Rot_90 219 | |
| 253 | #define IDR_VP_PA_444DScale16_Buf_2 220 | |
| 254 | #define IDR_VP_PA_444DScale16_Buf_2_Rot_180 221 | |
| 255 | #define IDR_VP_PA_444DScale16_Buf_2_Rot_270 222 | |
| 256 | #define IDR_VP_PA_444DScale16_Buf_2_Rot_90 223 | |
| 257 | #define IDR_VP_PA_444DScale16_Buf_3 224 | |
| 258 | #define IDR_VP_PA_444DScale16_Buf_3_Rot_180 225 | |
| 259 | #define IDR_VP_PA_444DScale16_Buf_3_Rot_270 226 | |
| 260 | #define IDR_VP_PA_444DScale16_Buf_3_Rot_90 227 | |
| 261 | #define IDR_VP_PA_444DScale16_Buf_4 228 | |
| 262 | #define IDR_VP_PA_444DScale16_Buf_4_Rot_180 229 | |
| 263 | #define IDR_VP_PA_444DScale16_Buf_4_Rot_270 230 | |
| 264 | #define IDR_VP_PA_444DScale16_Buf_4_Rot_90 231 | |
| 265 | #define IDR_VP_PA_444DScale16_Buf_5 232 | |
| 266 | #define IDR_VP_PA_444DScale16_Buf_5_Rot_180 233 | |
| 267 | #define IDR_VP_PA_444DScale16_Buf_5_Rot_270 234 | |
| 268 | #define IDR_VP_PA_444DScale16_Buf_5_Rot_90 235 | |
| 269 | #define IDR_VP_PA_444Scale16_Buf_0 236 | |
| 270 | #define IDR_VP_PA_444Scale16_Buf_0_Rot_180 237 | |
| 271 | #define IDR_VP_PA_444Scale16_Buf_0_Rot_270 238 | |
| 272 | #define IDR_VP_PA_444Scale16_Buf_0_Rot_90 239 | |
| 273 | #define IDR_VP_PA_444Scale16_Buf_1 240 | |
| 274 | #define IDR_VP_PA_444Scale16_Buf_1_Rot_180 241 | |
| 275 | #define IDR_VP_PA_444Scale16_Buf_1_Rot_270 242 | |
| 276 | #define IDR_VP_PA_444Scale16_Buf_1_Rot_90 243 | |
| 277 | #define IDR_VP_PA_444Scale16_Buf_2 244 | |
| 278 | #define IDR_VP_PA_444Scale16_Buf_2_Rot_180 245 | |
| 279 | #define IDR_VP_PA_444Scale16_Buf_2_Rot_270 246 | |
| 280 | #define IDR_VP_PA_444Scale16_Buf_2_Rot_90 247 | |
| 281 | #define IDR_VP_PA_444Scale16_Buf_3 248 | |
| 282 | #define IDR_VP_PA_444Scale16_Buf_3_Rot_180 249 | |
| 283 | #define IDR_VP_PA_444Scale16_Buf_3_Rot_270 250 | |
| 284 | #define IDR_VP_PA_444Scale16_Buf_3_Rot_90 251 | |
| 285 | #define IDR_VP_PA_444Scale16_Buf_4 252 | |
| 286 | #define IDR_VP_PA_444Scale16_Buf_4_Rot_180 253 | |
| 287 | #define IDR_VP_PA_444Scale16_Buf_4_Rot_270 254 | |
| 288 | #define IDR_VP_PA_444Scale16_Buf_4_Rot_90 255 | |
| 289 | #define IDR_VP_PA_444Scale16_Buf_5 256 | |
| 290 | #define IDR_VP_PA_444Scale16_Buf_5_Rot_180 257 | |
| 291 | #define IDR_VP_PA_444Scale16_Buf_5_Rot_270 258 | |
| 292 | #define IDR_VP_PA_444Scale16_Buf_5_Rot_90 259 | |
| 293 | #define IDR_VP_PA_444iAVS16_Buf_0 260 | |
| 294 | #define IDR_VP_PA_444iAVS16_Buf_1 261 | |
| 295 | #define IDR_VP_PA_444iAVS16_Buf_2 262 | |
| 296 | #define IDR_VP_PA_444iAVS16_Buf_3 263 | |
| 297 | #define IDR_VP_PA_444iDScale16_Buf_0 264 | |
| 298 | #define IDR_VP_PA_444iDScale16_Buf_1 265 | |
| 299 | #define IDR_VP_PA_444iDScale16_Buf_2 266 | |
| 300 | #define IDR_VP_PA_444iDScale16_Buf_3 267 | |
| 301 | #define IDR_VP_PA_444iScale16_Buf_0 268 | |
| 302 | #define IDR_VP_PA_444iScale16_Buf_0_Rot_180 269 | |
| 303 | #define IDR_VP_PA_444iScale16_Buf_0_Rot_270 270 | |
| 304 | #define IDR_VP_PA_444iScale16_Buf_0_Rot_90 271 | |
| 305 | #define IDR_VP_PA_444iScale16_Buf_1 272 | |
| 306 | #define IDR_VP_PA_444iScale16_Buf_1_Rot_180 273 | |
| 307 | #define IDR_VP_PA_444iScale16_Buf_1_Rot_270 274 | |
| 308 | #define IDR_VP_PA_444iScale16_Buf_1_Rot_90 275 | |
| 309 | #define IDR_VP_PA_444iScale16_Buf_2 276 | |
| 310 | #define IDR_VP_PA_444iScale16_Buf_2_Rot_180 277 | |
| 311 | #define IDR_VP_PA_444iScale16_Buf_2_Rot_270 278 | |
| 312 | #define IDR_VP_PA_444iScale16_Buf_2_Rot_90 279 | |
| 313 | #define IDR_VP_PA_444iScale16_Buf_3 280 | |
| 314 | #define IDR_VP_PA_444iScale16_Buf_3_Rot_180 281 | |
| 315 | #define IDR_VP_PA_444iScale16_Buf_3_Rot_270 282 | |
| 316 | #define IDR_VP_PA_444iScale16_Buf_3_Rot_90 283 | |
| 317 | #define IDR_VP_PA_AVS_Mirror_H_L0 284 | |
| 318 | #define IDR_VP_PA_AVS_Mirror_V_L0 285 | |
| 319 | #define IDR_VP_PA_AVS_Rotate_90_Mirror_H_L0 286 | |
| 320 | #define IDR_VP_PA_AVS_Rotate_90_Mirror_V_L0 287 | |
| 321 | #define IDR_VP_PA_AVS_Rotate_L0_180 288 | |
| 322 | #define IDR_VP_PA_AVS_Rotate_L0_270 289 | |
| 323 | #define IDR_VP_PA_AVS_Rotate_L0_90 290 | |
| 324 | #define IDR_VP_PA_Copy 291 | |
| 325 | #define IDR_VP_PA_Scale_Mirror_H_L0 292 | |
| 326 | #define IDR_VP_PA_Scale_Mirror_V_L0 293 | |
| 327 | #define IDR_VP_PA_Scale_Rotate90_Mirror_H_L0 294 | |
| 328 | #define IDR_VP_PA_Scale_Rotate90_Mirror_V_L0 295 | |
| 329 | #define IDR_VP_PA_Scale_Rotate_L0_180 296 | |
| 330 | #define IDR_VP_PA_Scale_Rotate_L0_270 297 | |
| 331 | #define IDR_VP_PA_Scale_Rotate_L0_90 298 | |
| 332 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_0 299 | |
| 333 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_1 300 | |
| 334 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_2 301 | |
| 335 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_3 302 | |
| 336 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_4 303 | |
| 337 | #define IDR_VP_PL2_422AVS16_ChromaSiting_Buf_5 304 | |
| 338 | #define IDR_VP_PL2_444AVS16_Buf_0 305 | |
| 339 | #define IDR_VP_PL2_444AVS16_Buf_0_Rot_180 306 | |
| 340 | #define IDR_VP_PL2_444AVS16_Buf_0_Rot_270 307 | |
| 341 | #define IDR_VP_PL2_444AVS16_Buf_0_Rot_90 308 | |
| 342 | #define IDR_VP_PL2_444AVS16_Buf_1 309 | |
| 343 | #define IDR_VP_PL2_444AVS16_Buf_1_Rot_180 310 | |
| 344 | #define IDR_VP_PL2_444AVS16_Buf_1_Rot_270 311 | |
| 345 | #define IDR_VP_PL2_444AVS16_Buf_1_Rot_90 312 | |
| 346 | #define IDR_VP_PL2_444AVS16_Buf_2 313 | |
| 347 | #define IDR_VP_PL2_444AVS16_Buf_2_Rot_180 314 | |
| 348 | #define IDR_VP_PL2_444AVS16_Buf_2_Rot_270 315 | |
| 349 | #define IDR_VP_PL2_444AVS16_Buf_2_Rot_90 316 | |
| 350 | #define IDR_VP_PL2_444AVS16_Buf_3 317 | |
| 351 | #define IDR_VP_PL2_444AVS16_Buf_3_Rot_180 318 | |
| 352 | #define IDR_VP_PL2_444AVS16_Buf_3_Rot_270 319 | |
| 353 | #define IDR_VP_PL2_444AVS16_Buf_3_Rot_90 320 | |
| 354 | #define IDR_VP_PL2_444AVS16_Buf_4 321 | |
| 355 | #define IDR_VP_PL2_444AVS16_Buf_4_Rot_180 322 | |
| 356 | #define IDR_VP_PL2_444AVS16_Buf_4_Rot_270 323 | |
| 357 | #define IDR_VP_PL2_444AVS16_Buf_4_Rot_90 324 | |
| 358 | #define IDR_VP_PL2_444AVS16_Buf_5 325 | |
| 359 | #define IDR_VP_PL2_444AVS16_Buf_5_Rot_180 326 | |
| 360 | #define IDR_VP_PL2_444AVS16_Buf_5_Rot_270 327 | |
| 361 | #define IDR_VP_PL2_444AVS16_Buf_5_Rot_90 328 | |
| 362 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_4 329 | |
| 363 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_4_Rot_180 330 | |
| 364 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_4_Rot_270 331 | |
| 365 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_4_Rot_90 332 | |
| 366 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_5 333 | |
| 367 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_5_Rot_180 334 | |
| 368 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_5_Rot_270 335 | |
| 369 | #define IDR_VP_PL2_444AVS16_Buf_Sep_Alpha_5_Rot_90 336 | |
| 370 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_0 337 | |
| 371 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_1 338 | |
| 372 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_2 339 | |
| 373 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_3 340 | |
| 374 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_4 341 | |
| 375 | #define IDR_VP_PL2_444AVS16_ChromaSiting_Buf_5 342 | |
| 376 | #define IDR_VP_PL2_444DScale16_Buf_0 343 | |
| 377 | #define IDR_VP_PL2_444DScale16_Buf_0_Rot_180 344 | |
| 378 | #define IDR_VP_PL2_444DScale16_Buf_0_Rot_270 345 | |
| 379 | #define IDR_VP_PL2_444DScale16_Buf_0_Rot_90 346 | |
| 380 | #define IDR_VP_PL2_444DScale16_Buf_1 347 | |
| 381 | #define IDR_VP_PL2_444DScale16_Buf_1_Rot_180 348 | |
| 382 | #define IDR_VP_PL2_444DScale16_Buf_1_Rot_270 349 | |
| 383 | #define IDR_VP_PL2_444DScale16_Buf_1_Rot_90 350 | |
| 384 | #define IDR_VP_PL2_444DScale16_Buf_2 351 | |
| 385 | #define IDR_VP_PL2_444DScale16_Buf_2_Rot_180 352 | |
| 386 | #define IDR_VP_PL2_444DScale16_Buf_2_Rot_270 353 | |
| 387 | #define IDR_VP_PL2_444DScale16_Buf_2_Rot_90 354 | |
| 388 | #define IDR_VP_PL2_444DScale16_Buf_3 355 | |
| 389 | #define IDR_VP_PL2_444DScale16_Buf_3_Rot_180 356 | |
| 390 | #define IDR_VP_PL2_444DScale16_Buf_3_Rot_270 357 | |
| 391 | #define IDR_VP_PL2_444DScale16_Buf_3_Rot_90 358 | |
| 392 | #define IDR_VP_PL2_444DScale16_Buf_4 359 | |
| 393 | #define IDR_VP_PL2_444DScale16_Buf_4_Rot_180 360 | |
| 394 | #define IDR_VP_PL2_444DScale16_Buf_4_Rot_270 361 | |
| 395 | #define IDR_VP_PL2_444DScale16_Buf_4_Rot_90 362 | |
| 396 | #define IDR_VP_PL2_444DScale16_Buf_5 363 | |
| 397 | #define IDR_VP_PL2_444DScale16_Buf_5_Rot_180 364 | |
| 398 | #define IDR_VP_PL2_444DScale16_Buf_5_Rot_270 365 | |
| 399 | #define IDR_VP_PL2_444DScale16_Buf_5_Rot_90 366 | |
| 400 | #define IDR_VP_PL2_444DScale16_Buf_Sep_Alpha_4 367 | |
| 401 | #define IDR_VP_PL2_444DScale16_Buf_Sep_Alpha_5 368 | |
| 402 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_0 369 | |
| 403 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_0_Rot_180 370 | |
| 404 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_0_Rot_270 371 | |
| 405 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_0_Rot_90 372 | |
| 406 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_1 373 | |
| 407 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_1_Rot_180 374 | |
| 408 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_1_Rot_270 375 | |
| 409 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_1_Rot_90 376 | |
| 410 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_2 377 | |
| 411 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_2_Rot_180 378 | |
| 412 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_2_Rot_270 379 | |
| 413 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_2_Rot_90 380 | |
| 414 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_3 381 | |
| 415 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_3_Rot_180 382 | |
| 416 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_3_Rot_270 383 | |
| 417 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_3_Rot_90 384 | |
| 418 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_4 385 | |
| 419 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_4_Rot_180 386 | |
| 420 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_4_Rot_270 387 | |
| 421 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_4_Rot_90 388 | |
| 422 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_5 389 | |
| 423 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_5_Rot_180 390 | |
| 424 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_5_Rot_270 391 | |
| 425 | #define IDR_VP_PL2_444DScale16_ChromaSiting_Buf_5_Rot_90 392 | |
| 426 | #define IDR_VP_PL2_444Scale16_Buf_0 393 | |
| 427 | #define IDR_VP_PL2_444Scale16_Buf_0_Rot_180 394 | |
| 428 | #define IDR_VP_PL2_444Scale16_Buf_0_Rot_270 395 | |
| 429 | #define IDR_VP_PL2_444Scale16_Buf_0_Rot_90 396 | |
| 430 | #define IDR_VP_PL2_444Scale16_Buf_1 397 | |
| 431 | #define IDR_VP_PL2_444Scale16_Buf_1_Rot_180 398 | |
| 432 | #define IDR_VP_PL2_444Scale16_Buf_1_Rot_270 399 | |
| 433 | #define IDR_VP_PL2_444Scale16_Buf_1_Rot_90 400 | |
| 434 | #define IDR_VP_PL2_444Scale16_Buf_2 401 | |
| 435 | #define IDR_VP_PL2_444Scale16_Buf_2_Rot_180 402 | |
| 436 | #define IDR_VP_PL2_444Scale16_Buf_2_Rot_270 403 | |
| 437 | #define IDR_VP_PL2_444Scale16_Buf_2_Rot_90 404 | |
| 438 | #define IDR_VP_PL2_444Scale16_Buf_3 405 | |
| 439 | #define IDR_VP_PL2_444Scale16_Buf_3_Rot_180 406 | |
| 440 | #define IDR_VP_PL2_444Scale16_Buf_3_Rot_270 407 | |
| 441 | #define IDR_VP_PL2_444Scale16_Buf_3_Rot_90 408 | |
| 442 | #define IDR_VP_PL2_444Scale16_Buf_4 409 | |
| 443 | #define IDR_VP_PL2_444Scale16_Buf_4_Rot_180 410 | |
| 444 | #define IDR_VP_PL2_444Scale16_Buf_4_Rot_270 411 | |
| 445 | #define IDR_VP_PL2_444Scale16_Buf_4_Rot_90 412 | |
| 446 | #define IDR_VP_PL2_444Scale16_Buf_5 413 | |
| 447 | #define IDR_VP_PL2_444Scale16_Buf_5_Rot_180 414 | |
| 448 | #define IDR_VP_PL2_444Scale16_Buf_5_Rot_270 415 | |
| 449 | #define IDR_VP_PL2_444Scale16_Buf_5_Rot_90 416 | |
| 450 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_4 417 | |
| 451 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_4_Rot_180 418 | |
| 452 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_4_Rot_270 419 | |
| 453 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_4_Rot_90 420 | |
| 454 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_5 421 | |
| 455 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_5_Rot_180 422 | |
| 456 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_5_Rot_270 423 | |
| 457 | #define IDR_VP_PL2_444Scale16_Buf_Sep_Alpha_5_Rot_90 424 | |
| 458 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_0 425 | |
| 459 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_0_Rot_180 426 | |
| 460 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_0_Rot_270 427 | |
| 461 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_0_Rot_90 428 | |
| 462 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_1 429 | |
| 463 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_1_Rot_180 430 | |
| 464 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_1_Rot_270 431 | |
| 465 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_1_Rot_90 432 | |
| 466 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_2 433 | |
| 467 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_2_Rot_180 434 | |
| 468 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_2_Rot_270 435 | |
| 469 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_2_Rot_90 436 | |
| 470 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_3 437 | |
| 471 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_3_Rot_180 438 | |
| 472 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_3_Rot_270 439 | |
| 473 | #define IDR_VP_PL2_444Scale16_Chromasiting_Buf_3_Rot_90 440 | |
| 474 | #define IDR_VP_PL2_444iDScale16_Buf_0 441 | |
| 475 | #define IDR_VP_PL2_444iDScale16_Buf_1 442 | |
| 476 | #define IDR_VP_PL2_444iDScale16_Buf_2 443 | |
| 477 | #define IDR_VP_PL2_444iDScale16_Buf_3 444 | |
| 478 | #define IDR_VP_PL2_444iScale16_Buf_0 445 | |
| 479 | #define IDR_VP_PL2_444iScale16_Buf_0_Rot_180 446 | |
| 480 | #define IDR_VP_PL2_444iScale16_Buf_0_Rot_270 447 | |
| 481 | #define IDR_VP_PL2_444iScale16_Buf_0_Rot_90 448 | |
| 482 | #define IDR_VP_PL2_444iScale16_Buf_1 449 | |
| 483 | #define IDR_VP_PL2_444iScale16_Buf_1_Rot_180 450 | |
| 484 | #define IDR_VP_PL2_444iScale16_Buf_1_Rot_270 451 | |
| 485 | #define IDR_VP_PL2_444iScale16_Buf_1_Rot_90 452 | |
| 486 | #define IDR_VP_PL2_444iScale16_Buf_2 453 | |
| 487 | #define IDR_VP_PL2_444iScale16_Buf_2_Rot_180 454 | |
| 488 | #define IDR_VP_PL2_444iScale16_Buf_2_Rot_270 455 | |
| 489 | #define IDR_VP_PL2_444iScale16_Buf_2_Rot_90 456 | |
| 490 | #define IDR_VP_PL2_444iScale16_Buf_3 457 | |
| 491 | #define IDR_VP_PL2_444iScale16_Buf_3_Rot_180 458 | |
| 492 | #define IDR_VP_PL2_444iScale16_Buf_3_Rot_270 459 | |
| 493 | #define IDR_VP_PL2_444iScale16_Buf_3_Rot_90 460 | |
| 494 | #define IDR_VP_PL2_AVS_Mirror_H_L0 461 | |
| 495 | #define IDR_VP_PL2_AVS_Mirror_H_L0_DualOutput 462 | |
| 496 | #define IDR_VP_PL2_AVS_Mirror_V_L0 463 | |
| 497 | #define IDR_VP_PL2_AVS_Rotate90_Mirror_H_L0 464 | |
| 498 | #define IDR_VP_PL2_AVS_Rotate90_Mirror_V_L0 465 | |
| 499 | #define IDR_VP_PL2_AVS_Rotate_L0_180 466 | |
| 500 | #define IDR_VP_PL2_AVS_Rotate_L0_270 467 | |
| 501 | #define IDR_VP_PL2_AVS_Rotate_L0_90 468 | |
| 502 | #define IDR_VP_PL2_Copy 469 | |
| 503 | #define IDR_VP_PL2_Scale_Mirror_H_L0 470 | |
| 504 | #define IDR_VP_PL2_Scale_Mirror_H_L0_DualOutput 471 | |
| 505 | #define IDR_VP_PL2_Scale_Mirror_V_L0 472 | |
| 506 | #define IDR_VP_PL2_Scale_Rotate90_Mirror_H_L0 473 | |
| 507 | #define IDR_VP_PL2_Scale_Rotate90_Mirror_V_L0 474 | |
| 508 | #define IDR_VP_PL2_Scale_Rotate_L0_180 475 | |
| 509 | #define IDR_VP_PL2_Scale_Rotate_L0_270 476 | |
| 510 | #define IDR_VP_PL2_Scale_Rotate_L0_90 477 | |
| 511 | #define IDR_VP_PL3_444AVS16_Buf_0 478 | |
| 512 | #define IDR_VP_PL3_444AVS16_Buf_0_Rot_180 479 | |
| 513 | #define IDR_VP_PL3_444AVS16_Buf_0_Rot_270 480 | |
| 514 | #define IDR_VP_PL3_444AVS16_Buf_0_Rot_90 481 | |
| 515 | #define IDR_VP_PL3_444AVS16_Buf_1 482 | |
| 516 | #define IDR_VP_PL3_444AVS16_Buf_1_Rot_180 483 | |
| 517 | #define IDR_VP_PL3_444AVS16_Buf_1_Rot_270 484 | |
| 518 | #define IDR_VP_PL3_444AVS16_Buf_1_Rot_90 485 | |
| 519 | #define IDR_VP_PL3_444AVS16_Buf_2 486 | |
| 520 | #define IDR_VP_PL3_444AVS16_Buf_2_Rot_180 487 | |
| 521 | #define IDR_VP_PL3_444AVS16_Buf_2_Rot_270 488 | |
| 522 | #define IDR_VP_PL3_444AVS16_Buf_2_Rot_90 489 | |
| 523 | #define IDR_VP_PL3_444AVS16_Buf_3 490 | |
| 524 | #define IDR_VP_PL3_444AVS16_Buf_3_Rot_180 491 | |
| 525 | #define IDR_VP_PL3_444AVS16_Buf_3_Rot_270 492 | |
| 526 | #define IDR_VP_PL3_444AVS16_Buf_3_Rot_90 493 | |
| 527 | #define IDR_VP_PL3_444AVS16_Buf_4 494 | |
| 528 | #define IDR_VP_PL3_444AVS16_Buf_4_Rot_180 495 | |
| 529 | #define IDR_VP_PL3_444AVS16_Buf_4_Rot_270 496 | |
| 530 | #define IDR_VP_PL3_444AVS16_Buf_4_Rot_90 497 | |
| 531 | #define IDR_VP_PL3_444AVS16_Buf_5 498 | |
| 532 | #define IDR_VP_PL3_444AVS16_Buf_5_Rot_180 499 | |
| 533 | #define IDR_VP_PL3_444AVS16_Buf_5_Rot_270 500 | |
| 534 | #define IDR_VP_PL3_444AVS16_Buf_5_Rot_90 501 | |
| 535 | #define IDR_VP_PL3_444DScale16_Buf_0 502 | |
| 536 | #define IDR_VP_PL3_444DScale16_Buf_0_Rot_180 503 | |
| 537 | #define IDR_VP_PL3_444DScale16_Buf_0_Rot_270 504 | |
| 538 | #define IDR_VP_PL3_444DScale16_Buf_0_Rot_90 505 | |
| 539 | #define IDR_VP_PL3_444DScale16_Buf_1 506 | |
| 540 | #define IDR_VP_PL3_444DScale16_Buf_1_Rot_180 507 | |
| 541 | #define IDR_VP_PL3_444DScale16_Buf_1_Rot_270 508 | |
| 542 | #define IDR_VP_PL3_444DScale16_Buf_1_Rot_90 509 | |
| 543 | #define IDR_VP_PL3_444DScale16_Buf_2 510 | |
| 544 | #define IDR_VP_PL3_444DScale16_Buf_2_Rot_180 511 | |
| 545 | #define IDR_VP_PL3_444DScale16_Buf_2_Rot_270 512 | |
| 546 | #define IDR_VP_PL3_444DScale16_Buf_2_Rot_90 513 | |
| 547 | #define IDR_VP_PL3_444DScale16_Buf_3 514 | |
| 548 | #define IDR_VP_PL3_444DScale16_Buf_3_Rot_180 515 | |
| 549 | #define IDR_VP_PL3_444DScale16_Buf_3_Rot_270 516 | |
| 550 | #define IDR_VP_PL3_444DScale16_Buf_3_Rot_90 517 | |
| 551 | #define IDR_VP_PL3_444DScale16_Buf_4 518 | |
| 552 | #define IDR_VP_PL3_444DScale16_Buf_4_Rot_180 519 | |
| 553 | #define IDR_VP_PL3_444DScale16_Buf_4_Rot_270 520 | |
| 554 | #define IDR_VP_PL3_444DScale16_Buf_4_Rot_90 521 | |
| 555 | #define IDR_VP_PL3_444DScale16_Buf_5 522 | |
| 556 | #define IDR_VP_PL3_444DScale16_Buf_5_Rot_180 523 | |
| 557 | #define IDR_VP_PL3_444DScale16_Buf_5_Rot_270 524 | |
| 558 | #define IDR_VP_PL3_444DScale16_Buf_5_Rot_90 525 | |
| 559 | #define IDR_VP_PL3_444Scale16_Buf_0 526 | |
| 560 | #define IDR_VP_PL3_444Scale16_Buf_0_Rot_180 527 | |
| 561 | #define IDR_VP_PL3_444Scale16_Buf_0_Rot_270 528 | |
| 562 | #define IDR_VP_PL3_444Scale16_Buf_0_Rot_90 529 | |
| 563 | #define IDR_VP_PL3_444Scale16_Buf_1 530 | |
| 564 | #define IDR_VP_PL3_444Scale16_Buf_1_Rot_180 531 | |
| 565 | #define IDR_VP_PL3_444Scale16_Buf_1_Rot_270 532 | |
| 566 | #define IDR_VP_PL3_444Scale16_Buf_1_Rot_90 533 | |
| 567 | #define IDR_VP_PL3_444Scale16_Buf_2 534 | |
| 568 | #define IDR_VP_PL3_444Scale16_Buf_2_Rot_180 535 | |
| 569 | #define IDR_VP_PL3_444Scale16_Buf_2_Rot_270 536 | |
| 570 | #define IDR_VP_PL3_444Scale16_Buf_2_Rot_90 537 | |
| 571 | #define IDR_VP_PL3_444Scale16_Buf_3 538 | |
| 572 | #define IDR_VP_PL3_444Scale16_Buf_3_Rot_180 539 | |
| 573 | #define IDR_VP_PL3_444Scale16_Buf_3_Rot_270 540 | |
| 574 | #define IDR_VP_PL3_444Scale16_Buf_3_Rot_90 541 | |
| 575 | #define IDR_VP_PL3_444Scale16_Buf_4 542 | |
| 576 | #define IDR_VP_PL3_444Scale16_Buf_4_Rot_180 543 | |
| 577 | #define IDR_VP_PL3_444Scale16_Buf_4_Rot_270 544 | |
| 578 | #define IDR_VP_PL3_444Scale16_Buf_4_Rot_90 545 | |
| 579 | #define IDR_VP_PL3_444Scale16_Buf_5 546 | |
| 580 | #define IDR_VP_PL3_444Scale16_Buf_5_Rot_180 547 | |
| 581 | #define IDR_VP_PL3_444Scale16_Buf_5_Rot_270 548 | |
| 582 | #define IDR_VP_PL3_444Scale16_Buf_5_Rot_90 549 | |
| 583 | #define IDR_VP_PL3_444iDScale16_Buf_0 550 | |
| 584 | #define IDR_VP_PL3_444iDScale16_Buf_1 551 | |
| 585 | #define IDR_VP_PL3_444iDScale16_Buf_2 552 | |
| 586 | #define IDR_VP_PL3_444iDScale16_Buf_3 553 | |
| 587 | #define IDR_VP_PL3_444iScale16_Buf_0 554 | |
| 588 | #define IDR_VP_PL3_444iScale16_Buf_0_Rot_180 555 | |
| 589 | #define IDR_VP_PL3_444iScale16_Buf_0_Rot_270 556 | |
| 590 | #define IDR_VP_PL3_444iScale16_Buf_0_Rot_90 557 | |
| 591 | #define IDR_VP_PL3_444iScale16_Buf_1 558 | |
| 592 | #define IDR_VP_PL3_444iScale16_Buf_1_Rot_180 559 | |
| 593 | #define IDR_VP_PL3_444iScale16_Buf_1_Rot_270 560 | |
| 594 | #define IDR_VP_PL3_444iScale16_Buf_1_Rot_90 561 | |
| 595 | #define IDR_VP_PL3_444iScale16_Buf_2 562 | |
| 596 | #define IDR_VP_PL3_444iScale16_Buf_2_Rot_180 563 | |
| 597 | #define IDR_VP_PL3_444iScale16_Buf_2_Rot_270 564 | |
| 598 | #define IDR_VP_PL3_444iScale16_Buf_2_Rot_90 565 | |
| 599 | #define IDR_VP_PL3_444iScale16_Buf_3 566 | |
| 600 | #define IDR_VP_PL3_444iScale16_Buf_3_Rot_180 567 | |
| 601 | #define IDR_VP_PL3_444iScale16_Buf_3_Rot_270 568 | |
| 602 | #define IDR_VP_PL3_444iScale16_Buf_3_Rot_90 569 | |
| 603 | #define IDR_VP_PL3_AVS_Rotate_L0_180 570 | |
| 604 | #define IDR_VP_PL3_AVS_Rotate_L0_270 571 | |
| 605 | #define IDR_VP_PL3_AVS_Rotate_L0_90 572 | |
| 606 | #define IDR_VP_PL3_Scale_Rotate_L0_180 573 | |
| 607 | #define IDR_VP_PL3_Scale_Rotate_L0_270 574 | |
| 608 | #define IDR_VP_PL3_Scale_Rotate_L0_90 575 | |
| 609 | #define IDR_VP_PLY_444DScale16_2f_Buf_0 576 | |
| 610 | #define IDR_VP_PLY_444DScale16_2f_Buf_1 577 | |
| 611 | #define IDR_VP_PLY_444DScale16_2f_Buf_2 578 | |
| 612 | #define IDR_VP_PLY_444DScale16_2f_Buf_3 579 | |
| 613 | #define IDR_VP_PLY_444DScale16_Buf_0 580 | |
| 614 | #define IDR_VP_PLY_444DScale16_Buf_0_Rot_180 581 | |
| 615 | #define IDR_VP_PLY_444DScale16_Buf_0_Rot_270 582 | |
| 616 | #define IDR_VP_PLY_444DScale16_Buf_0_Rot_90 583 | |
| 617 | #define IDR_VP_PLY_444DScale16_Buf_1 584 | |
| 618 | #define IDR_VP_PLY_444DScale16_Buf_1_Rot_180 585 | |
| 619 | #define IDR_VP_PLY_444DScale16_Buf_1_Rot_270 586 | |
| 620 | #define IDR_VP_PLY_444DScale16_Buf_1_Rot_90 587 | |
| 621 | #define IDR_VP_PLY_444DScale16_Buf_2 588 | |
| 622 | #define IDR_VP_PLY_444DScale16_Buf_2_Rot_180 589 | |
| 623 | #define IDR_VP_PLY_444DScale16_Buf_2_Rot_270 590 | |
| 624 | #define IDR_VP_PLY_444DScale16_Buf_2_Rot_90 591 | |
| 625 | #define IDR_VP_PLY_444DScale16_Buf_3 592 | |
| 626 | #define IDR_VP_PLY_444DScale16_Buf_3_Rot_180 593 | |
| 627 | #define IDR_VP_PLY_444DScale16_Buf_3_Rot_270 594 | |
| 628 | #define IDR_VP_PLY_444DScale16_Buf_3_Rot_90 595 | |
| 629 | #define IDR_VP_PartBlend_444_16 596 | |
| 630 | #define IDR_VP_Prepare_LumaKey_SampleUnorm 597 | |
| 631 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4 598 | |
| 632 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_mirror_h 599 | |
| 633 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_mirror_v 600 | |
| 634 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_rot_180 601 | |
| 635 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_rot_270 602 | |
| 636 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_rot_90 603 | |
| 637 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_rot_90_mirror_h 604 | |
| 638 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_rot_90_mirror_v 605 | |
| 639 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th 606 | |
| 640 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_mirror_h 607 | |
| 641 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_mirror_v 608 | |
| 642 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_rot_180 609 | |
| 643 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_rot_270 610 | |
| 644 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_rot_90 611 | |
| 645 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_rot_90_mirror_h 612 | |
| 646 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_1_8th_rot_90_mirror_v 613 | |
| 647 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio 614 | |
| 648 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_mirror_h 615 | |
| 649 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_mirror_v 616 | |
| 650 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_rot_180 617 | |
| 651 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_rot_270 618 | |
| 652 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_rot_90 619 | |
| 653 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_rot_90_mirror_h 620 | |
| 654 | #define IDR_VP_R8G8B8A8_DP_DownScaling_4x4_scale_to_any_ratio_rot_90_mirror_v 621 | |
| 655 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8 622 | |
| 656 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_mirror_h 623 | |
| 657 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_mirror_v 624 | |
| 658 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_rot_180 625 | |
| 659 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_rot_270 626 | |
| 660 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_rot_90 627 | |
| 661 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_rot_90_mirror_h 628 | |
| 662 | #define IDR_VP_R8G8B8A8_DP_DownScaling_8x8_rot_90_mirror_v 629 | |
| 663 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16 630 | |
| 664 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_mirror_h 631 | |
| 665 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_mirror_v 632 | |
| 666 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_rot_180 633 | |
| 667 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_rot_270 634 | |
| 668 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_rot_90 635 | |
| 669 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_rot_90_mirror_h 636 | |
| 670 | #define IDR_VP_R8G8B8A8_DP_UpScaling_16x16_rot_90_mirror_v 637 | |
| 671 | #define IDR_VP_RGB2sRGB 638 | |
| 672 | #define IDR_VP_RGBP_DP_DownScaling_8x8 639 | |
| 673 | #define IDR_VP_RGBP_DP_UpScaling_16x16 640 | |
| 674 | #define IDR_VP_Rotate_90_Mirror_AVS_H_L0 641 | |
| 675 | #define IDR_VP_Rotate_90_Mirror_AVS_V_L0 642 | |
| 676 | #define IDR_VP_Rotate_90_Mirror_H_scale_L0 643 | |
| 677 | #define IDR_VP_Rotate_90_Mirror_V_scale_L0 644 | |
| 678 | #define IDR_VP_Rotate_AVS_L0_180 645 | |
| 679 | #define IDR_VP_Rotate_AVS_L0_270 646 | |
| 680 | #define IDR_VP_Rotate_AVS_L0_90 647 | |
| 681 | #define IDR_VP_Rotate_Scale_L0_180 648 | |
| 682 | #define IDR_VP_Rotate_Scale_L0_270 649 | |
| 683 | #define IDR_VP_Rotate_Scale_L0_90 650 | |
| 684 | #define IDR_VP_SIP_Debug 651 | |
| 685 | #define IDR_VP_Save_444AVS16_ARGB 652 | |
| 686 | #define IDR_VP_Save_444AVS16_ARGB_64Byte 653 | |
| 687 | #define IDR_VP_Save_444AVS16_NV12 654 | |
| 688 | #define IDR_VP_Save_444AVS16_NV21 655 | |
| 689 | #define IDR_VP_Save_444AVS16_PA 656 | |
| 690 | #define IDR_VP_Save_444AVS16_PL3 657 | |
| 691 | #define IDR_VP_Save_444AVS16_R10G10B10 658 | |
| 692 | #define IDR_VP_Save_444AVS16_R10G10B10A2 659 | |
| 693 | #define IDR_VP_Save_444AVS16_R10G10B10X2 660 | |
| 694 | #define IDR_VP_Save_444AVS16_RGB 661 | |
| 695 | #define IDR_VP_Save_444AVS16_RGB16 662 | |
| 696 | #define IDR_VP_Save_444AVS16_RGB_64Byte 663 | |
| 697 | #define IDR_VP_Save_444AVS16_SrcAYUV 664 | |
| 698 | #define IDR_VP_Save_444AVS16_XRGB 665 | |
| 699 | #define IDR_VP_Save_444AVS16_XRGB_64Byte 666 | |
| 700 | #define IDR_VP_Save_444Scale16_ARGB 667 | |
| 701 | #define IDR_VP_Save_444Scale16_ARGB_64Byte 668 | |
| 702 | #define IDR_VP_Save_444Scale16_Dither_NV12 669 | |
| 703 | #define IDR_VP_Save_444Scale16_Dither_NV21 670 | |
| 704 | #define IDR_VP_Save_444Scale16_Dither_PA 671 | |
| 705 | #define IDR_VP_Save_444Scale16_Dither_PA_32X16 672 | |
| 706 | #define IDR_VP_Save_444Scale16_Dither_PL3 673 | |
| 707 | #define IDR_VP_Save_444Scale16_Dither_RGB 674 | |
| 708 | #define IDR_VP_Save_444Scale16_Dither_RGB16 675 | |
| 709 | #define IDR_VP_Save_444Scale16_Dither_RGB_64Byte 676 | |
| 710 | #define IDR_VP_Save_444Scale16_Dither_VUYA 677 | |
| 711 | #define IDR_VP_Save_444Scale16_Dither_XRGB 678 | |
| 712 | #define IDR_VP_Save_444Scale16_Dither_XRGB_64Byte 679 | |
| 713 | #define IDR_VP_Save_444Scale16_NV12 680 | |
| 714 | #define IDR_VP_Save_444Scale16_NV21 681 | |
| 715 | #define IDR_VP_Save_444Scale16_P010 682 | |
| 716 | #define IDR_VP_Save_444Scale16_P016 683 | |
| 717 | #define IDR_VP_Save_444Scale16_PA 684 | |
| 718 | #define IDR_VP_Save_444Scale16_PA_32X16 685 | |
| 719 | #define IDR_VP_Save_444Scale16_PL3 686 | |
| 720 | #define IDR_VP_Save_444Scale16_PLY 687 | |
| 721 | #define IDR_VP_Save_444Scale16_R10G10B10 688 | |
| 722 | #define IDR_VP_Save_444Scale16_R10G10B10A2 689 | |
| 723 | #define IDR_VP_Save_444Scale16_R10G10B10X2 690 | |
| 724 | #define IDR_VP_Save_444Scale16_R10G10B10XR 691 | |
| 725 | #define IDR_VP_Save_444Scale16_R10G10B10XRA2 692 | |
| 726 | #define IDR_VP_Save_444Scale16_R10G10B10XRX2 693 | |
| 727 | #define IDR_VP_Save_444Scale16_RGB 694 | |
| 728 | #define IDR_VP_Save_444Scale16_RGB16 695 | |
| 729 | #define IDR_VP_Save_444Scale16_RGBP 696 | |
| 730 | #define IDR_VP_Save_444Scale16_RGB_64Byte 697 | |
| 731 | #define IDR_VP_Save_444Scale16_SrcVUYA 698 | |
| 732 | #define IDR_VP_Save_444Scale16_SrcY416 699 | |
| 733 | #define IDR_VP_Save_444Scale16_VUYA 700 | |
| 734 | #define IDR_VP_Save_444Scale16_XRGB 701 | |
| 735 | #define IDR_VP_Save_444Scale16_XRGB_64Byte 702 | |
| 736 | #define IDR_VP_Save_444Scale16_Y210 703 | |
| 737 | #define IDR_VP_Save_444Scale16_Y216 704 | |
| 738 | #define IDR_VP_Save_444Scale16_Y410 705 | |
| 739 | #define IDR_VP_Save_444Scale16_Y416 706 | |
| 740 | #define IDR_VP_Save_ARGB_16x16 707 | |
| 741 | #define IDR_VP_Save_ARGB_4x4 708 | |
| 742 | #define IDR_VP_Save_ARGB_8x8 709 | |
| 743 | #define IDR_VP_Save_NV12_16x16 710 | |
| 744 | #define IDR_VP_Save_NV12_4x4 711 | |
| 745 | #define IDR_VP_Save_NV12_8x8 712 | |
| 746 | #define IDR_VP_Save_RGBP_16x16 713 | |
| 747 | #define IDR_VP_Save_RGBP_4x4 714 | |
| 748 | #define IDR_VP_Save_RGBP_8x8 715 | |
| 749 | #define IDR_VP_Secure_Block_Copy 716 | |
| 750 | #define IDR_VP_Set_Buf0_Buf4 717 | |
| 751 | #define IDR_VP_Set_Buf1_Buf5 718 | |
| 752 | #define IDR_VP_Set_Buf2_Buf4 719 | |
| 753 | #define IDR_VP_Set_Buf3_Buf5 720 | |
| 754 | #define IDR_VP_Set_CSC_Src_Buf0 721 | |
| 755 | #define IDR_VP_Set_CSC_Src_Buf1 722 | |
| 756 | #define IDR_VP_Set_CSC_Src_Buf2 723 | |
| 757 | #define IDR_VP_Set_CSC_Src_Buf3 724 | |
| 758 | #define IDR_VP_Set_CSC_Src_Buf4 725 | |
| 759 | #define IDR_VP_Set_CSC_Src_Buf5 726 | |
| 760 | #define IDR_VP_Set_CURBE_CSC_Coeff 727 | |
| 761 | #define IDR_VP_Set_ColorE_Src_Buf0 728 | |
| 762 | #define IDR_VP_Set_ColorE_Src_Buf1 729 | |
| 763 | #define IDR_VP_Set_ColorE_Src_Buf2 730 | |
| 764 | #define IDR_VP_Set_ColorE_Src_Buf3 731 | |
| 765 | #define IDR_VP_Set_Dest_Surf_Indexes_Primary 732 | |
| 766 | #define IDR_VP_Set_Dest_Surf_Indexes_Secondary 733 | |
| 767 | #define IDR_VP_Set_GammaC_Src_Buf0 734 | |
| 768 | #define IDR_VP_Set_GammaC_Src_Buf1 735 | |
| 769 | #define IDR_VP_Set_GammaC_Src_Buf2 736 | |
| 770 | #define IDR_VP_Set_GammaC_Src_Buf3 737 | |
| 771 | #define IDR_VP_Set_Layer_0 738 | |
| 772 | #define IDR_VP_Set_Layer_1 739 | |
| 773 | #define IDR_VP_Set_Layer_1_AVS 740 | |
| 774 | #define IDR_VP_Set_Layer_2 741 | |
| 775 | #define IDR_VP_Set_Layer_3 742 | |
| 776 | #define IDR_VP_Set_Layer_4 743 | |
| 777 | #define IDR_VP_Set_Layer_5 744 | |
| 778 | #define IDR_VP_Set_Layer_6 745 | |
| 779 | #define IDR_VP_Set_Layer_7 746 | |
| 780 | #define IDR_VP_Set_Patched_CSC_Coeff 747 | |
| 781 | #define IDR_VP_Set_Scale_Buf_0123_Colorfill 748 | |
| 782 | #define IDR_VP_Set_Sec_Half_Buf45 749 | |
| 783 | #define IDR_VP_Shuffle_444AVS16_Buf_0 750 | |
| 784 | #define IDR_VP_Shuffle_444AVS16_Buf_1 751 | |
| 785 | #define IDR_VP_Shuffle_444AVS16_Buf_2 752 | |
| 786 | #define IDR_VP_Shuffle_444AVS16_Buf_3 753 | |
| 787 | #define IDR_VP_Shuffle_444AVS16_Buf_4 754 | |
| 788 | #define IDR_VP_Shuffle_444AVS16_Buf_5 755 | |
| 789 | #define IDR_VP_SrcBlend_444_16 756 | |
| 790 | #define IDR_VP_SrcBlend_4bits_444_16 757 | |
| 791 | #define IDR_VP_UpdateDNState 758 | |
| 792 | #define IDR_VP_VP_Setup 759 | |
| 793 | #define IDR_VP_VP_Setup_MediaWalker 760 | |
| 794 | #define IDR_VP_VP_Setup_MediaWalker_32X16_Design 761 | |
| 795 | #define IDR_VP_VP_Setup_MediaWalker_32x32_Color 762 | |
| 796 | #define IDR_VP_XOR_Composite_444_16 763 | |
| 797 | #define IDR_VP_XOR_Mono_Composite_444_16 764 | |
| 798 | #define IDR_VP_Y210_444DScale16_Buf_0 765 | |
| 799 | #define IDR_VP_Y210_444DScale16_Buf_0_Rot_180 766 | |
| 800 | #define IDR_VP_Y210_444DScale16_Buf_0_Rot_270 767 | |
| 801 | #define IDR_VP_Y210_444DScale16_Buf_0_Rot_90 768 | |
| 802 | #define IDR_VP_Y210_444DScale16_Buf_1 769 | |
| 803 | #define IDR_VP_Y210_444DScale16_Buf_1_Rot_180 770 | |
| 804 | #define IDR_VP_Y210_444DScale16_Buf_1_Rot_270 771 | |
| 805 | #define IDR_VP_Y210_444DScale16_Buf_1_Rot_90 772 | |
| 806 | #define IDR_VP_Y210_444DScale16_Buf_2 773 | |
| 807 | #define IDR_VP_Y210_444DScale16_Buf_2_Rot_180 774 | |
| 808 | #define IDR_VP_Y210_444DScale16_Buf_2_Rot_270 775 | |
| 809 | #define IDR_VP_Y210_444DScale16_Buf_2_Rot_90 776 | |
| 810 | #define IDR_VP_Y210_444DScale16_Buf_3 777 | |
| 811 | #define IDR_VP_Y210_444DScale16_Buf_3_Rot_180 778 | |
| 812 | #define IDR_VP_Y210_444DScale16_Buf_3_Rot_270 779 | |
| 813 | #define IDR_VP_Y210_444DScale16_Buf_3_Rot_90 780 | |
| 814 | #define IDR_VP_Y210_444DScale16_Buf_4 781 | |
| 815 | #define IDR_VP_Y210_444DScale16_Buf_4_Rot_180 782 | |
| 816 | #define IDR_VP_Y210_444DScale16_Buf_4_Rot_270 783 | |
| 817 | #define IDR_VP_Y210_444DScale16_Buf_4_Rot_90 784 | |
| 818 | #define IDR_VP_Y210_444DScale16_Buf_5 785 | |
| 819 | #define IDR_VP_Y210_444DScale16_Buf_5_Rot_180 786 | |
| 820 | #define IDR_VP_Y210_444DScale16_Buf_5_Rot_270 787 | |
| 821 | #define IDR_VP_Y210_444DScale16_Buf_5_Rot_90 788 | |
| 822 | #define IDR_VP_Y210_444Scale16_Buf_0 789 | |
| 823 | #define IDR_VP_Y210_444Scale16_Buf_0_Rot_180 790 | |
| 824 | #define IDR_VP_Y210_444Scale16_Buf_0_Rot_270 791 | |
| 825 | #define IDR_VP_Y210_444Scale16_Buf_0_Rot_90 792 | |
| 826 | #define IDR_VP_Y210_444Scale16_Buf_1 793 | |
| 827 | #define IDR_VP_Y210_444Scale16_Buf_1_Rot_180 794 | |
| 828 | #define IDR_VP_Y210_444Scale16_Buf_1_Rot_270 795 | |
| 829 | #define IDR_VP_Y210_444Scale16_Buf_1_Rot_90 796 | |
| 830 | #define IDR_VP_Y210_444Scale16_Buf_2 797 | |
| 831 | #define IDR_VP_Y210_444Scale16_Buf_2_Rot_180 798 | |
| 832 | #define IDR_VP_Y210_444Scale16_Buf_2_Rot_270 799 | |
| 833 | #define IDR_VP_Y210_444Scale16_Buf_2_Rot_90 800 | |
| 834 | #define IDR_VP_Y210_444Scale16_Buf_3 801 | |
| 835 | #define IDR_VP_Y210_444Scale16_Buf_3_Rot_180 802 | |
| 836 | #define IDR_VP_Y210_444Scale16_Buf_3_Rot_270 803 | |
| 837 | #define IDR_VP_Y210_444Scale16_Buf_3_Rot_90 804 | |
| 838 | #define IDR_VP_Y210_444Scale16_Buf_4 805 | |
| 839 | #define IDR_VP_Y210_444Scale16_Buf_4_Rot_180 806 | |
| 840 | #define IDR_VP_Y210_444Scale16_Buf_4_Rot_270 807 | |
| 841 | #define IDR_VP_Y210_444Scale16_Buf_4_Rot_90 808 | |
| 842 | #define IDR_VP_Y210_444Scale16_Buf_5 809 | |
| 843 | #define IDR_VP_Y210_444Scale16_Buf_5_Rot_180 810 | |
| 844 | #define IDR_VP_Y210_444Scale16_Buf_5_Rot_270 811 | |
| 845 | #define IDR_VP_Y210_444Scale16_Buf_5_Rot_90 812 | |
| 846 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_0 813 | |
| 847 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_0_Rot_180 814 | |
| 848 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_0_Rot_270 815 | |
| 849 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_0_Rot_90 816 | |
| 850 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_1 817 | |
| 851 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_1_Rot_180 818 | |
| 852 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_1_Rot_270 819 | |
| 853 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_1_Rot_90 820 | |
| 854 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_2 821 | |
| 855 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_2_Rot_180 822 | |
| 856 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_2_Rot_270 823 | |
| 857 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_2_Rot_90 824 | |
| 858 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_3 825 | |
| 859 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_3_Rot_180 826 | |
| 860 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_3_Rot_270 827 | |
| 861 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_3_Rot_90 828 | |
| 862 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_4 829 | |
| 863 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_4_Rot_180 830 | |
| 864 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_4_Rot_270 831 | |
| 865 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_4_Rot_90 832 | |
| 866 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_5 833 | |
| 867 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_5_Rot_180 834 | |
| 868 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_5_Rot_270 835 | |
| 869 | #define IDR_VP_Y210_444_AVS16_Y_Scale16_UV_Buf_5_Rot_90 836 | |
| 870 | #define IDR_VP_Y410_444AVS16_Buf_0 837 | |
| 871 | #define IDR_VP_Y410_444AVS16_Buf_0_Rot_180 838 | |
| 872 | #define IDR_VP_Y410_444AVS16_Buf_0_Rot_270 839 | |
| 873 | #define IDR_VP_Y410_444AVS16_Buf_0_Rot_90 840 | |
| 874 | #define IDR_VP_Y410_444AVS16_Buf_1 841 | |
| 875 | #define IDR_VP_Y410_444AVS16_Buf_1_Rot_180 842 | |
| 876 | #define IDR_VP_Y410_444AVS16_Buf_1_Rot_270 843 | |
| 877 | #define IDR_VP_Y410_444AVS16_Buf_1_Rot_90 844 | |
| 878 | #define IDR_VP_Y410_444AVS16_Buf_2 845 | |
| 879 | #define IDR_VP_Y410_444AVS16_Buf_2_Rot_180 846 | |
| 880 | #define IDR_VP_Y410_444AVS16_Buf_2_Rot_270 847 | |
| 881 | #define IDR_VP_Y410_444AVS16_Buf_2_Rot_90 848 | |
| 882 | #define IDR_VP_Y410_444AVS16_Buf_3 849 | |
| 883 | #define IDR_VP_Y410_444AVS16_Buf_3_Rot_180 850 | |
| 884 | #define IDR_VP_Y410_444AVS16_Buf_3_Rot_270 851 | |
| 885 | #define IDR_VP_Y410_444AVS16_Buf_3_Rot_90 852 | |
| 886 | #define IDR_VP_Y410_444AVS16_Buf_4 853 | |
| 887 | #define IDR_VP_Y410_444AVS16_Buf_4_Rot_180 854 | |
| 888 | #define IDR_VP_Y410_444AVS16_Buf_4_Rot_270 855 | |
| 889 | #define IDR_VP_Y410_444AVS16_Buf_4_Rot_90 856 | |
| 890 | #define IDR_VP_Y410_444AVS16_Buf_5 857 | |
| 891 | #define IDR_VP_Y410_444AVS16_Buf_5_Rot_180 858 | |
| 892 | #define IDR_VP_Y410_444AVS16_Buf_5_Rot_270 859 | |
| 893 | #define IDR_VP_Y410_444AVS16_Buf_5_Rot_90 860 | |
| 894 | #define IDR_VP_Y410_444DScale16_Buf_0 861 | |
| 895 | #define IDR_VP_Y410_444DScale16_Buf_0_Rot_180 862 | |
| 896 | #define IDR_VP_Y410_444DScale16_Buf_0_Rot_270 863 | |
| 897 | #define IDR_VP_Y410_444DScale16_Buf_0_Rot_90 864 | |
| 898 | #define IDR_VP_Y410_444DScale16_Buf_1 865 | |
| 899 | #define IDR_VP_Y410_444DScale16_Buf_1_Rot_180 866 | |
| 900 | #define IDR_VP_Y410_444DScale16_Buf_1_Rot_270 867 | |
| 901 | #define IDR_VP_Y410_444DScale16_Buf_1_Rot_90 868 | |
| 902 | #define IDR_VP_Y410_444DScale16_Buf_2 869 | |
| 903 | #define IDR_VP_Y410_444DScale16_Buf_2_Rot_180 870 | |
| 904 | #define IDR_VP_Y410_444DScale16_Buf_2_Rot_270 871 | |
| 905 | #define IDR_VP_Y410_444DScale16_Buf_2_Rot_90 872 | |
| 906 | #define IDR_VP_Y410_444DScale16_Buf_3 873 | |
| 907 | #define IDR_VP_Y410_444DScale16_Buf_3_Rot_180 874 | |
| 908 | #define IDR_VP_Y410_444DScale16_Buf_3_Rot_270 875 | |
| 909 | #define IDR_VP_Y410_444DScale16_Buf_3_Rot_90 876 | |
| 910 | #define IDR_VP_Y410_444DScale16_Buf_4 877 | |
| 911 | #define IDR_VP_Y410_444DScale16_Buf_4_Rot_180 878 | |
| 912 | #define IDR_VP_Y410_444DScale16_Buf_4_Rot_270 879 | |
| 913 | #define IDR_VP_Y410_444DScale16_Buf_4_Rot_90 880 | |
| 914 | #define IDR_VP_Y410_444DScale16_Buf_5 881 | |
| 915 | #define IDR_VP_Y410_444DScale16_Buf_5_Rot_180 882 | |
| 916 | #define IDR_VP_Y410_444DScale16_Buf_5_Rot_270 883 | |
| 917 | #define IDR_VP_Y410_444DScale16_Buf_5_Rot_90 884 | |
| 918 | #define IDR_VP_Y410_444Scale16_Buf_0 885 | |
| 919 | #define IDR_VP_Y410_444Scale16_Buf_0_Rot_180 886 | |
| 920 | #define IDR_VP_Y410_444Scale16_Buf_0_Rot_270 887 | |
| 921 | #define IDR_VP_Y410_444Scale16_Buf_0_Rot_90 888 | |
| 922 | #define IDR_VP_Y410_444Scale16_Buf_1 889 | |
| 923 | #define IDR_VP_Y410_444Scale16_Buf_1_Rot_180 890 | |
| 924 | #define IDR_VP_Y410_444Scale16_Buf_1_Rot_270 891 | |
| 925 | #define IDR_VP_Y410_444Scale16_Buf_1_Rot_90 892 | |
| 926 | #define IDR_VP_Y410_444Scale16_Buf_2 893 | |
| 927 | #define IDR_VP_Y410_444Scale16_Buf_2_Rot_180 894 | |
| 928 | #define IDR_VP_Y410_444Scale16_Buf_2_Rot_270 895 | |
| 929 | #define IDR_VP_Y410_444Scale16_Buf_2_Rot_90 896 | |
| 930 | #define IDR_VP_Y410_444Scale16_Buf_3 897 | |
| 931 | #define IDR_VP_Y410_444Scale16_Buf_3_Rot_180 898 | |
| 932 | #define IDR_VP_Y410_444Scale16_Buf_3_Rot_270 899 | |
| 933 | #define IDR_VP_Y410_444Scale16_Buf_3_Rot_90 900 | |
| 934 | #define IDR_VP_Y410_444Scale16_Buf_4 901 | |
| 935 | #define IDR_VP_Y410_444Scale16_Buf_4_Rot_180 902 | |
| 936 | #define IDR_VP_Y410_444Scale16_Buf_4_Rot_270 903 | |
| 937 | #define IDR_VP_Y410_444Scale16_Buf_4_Rot_90 904 | |
| 938 | #define IDR_VP_Y410_444Scale16_Buf_5 905 | |
| 939 | #define IDR_VP_Y410_444Scale16_Buf_5_Rot_180 906 | |
| 940 | #define IDR_VP_Y410_444Scale16_Buf_5_Rot_270 907 | |
| 941 | #define IDR_VP_Y410_444Scale16_Buf_5_Rot_90 908 | |
| 942 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_0 909 | |
| 943 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_0_Rot_180 910 | |
| 944 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_0_Rot_270 911 | |
| 945 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_0_Rot_90 912 | |
| 946 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_1 913 | |
| 947 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_1_Rot_180 914 | |
| 948 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_1_Rot_270 915 | |
| 949 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_1_Rot_90 916 | |
| 950 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_2 917 | |
| 951 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_2_Rot_180 918 | |
| 952 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_2_Rot_270 919 | |
| 953 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_2_Rot_90 920 | |
| 954 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_3 921 | |
| 955 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_3_Rot_180 922 | |
| 956 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_3_Rot_270 923 | |
| 957 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_3_Rot_90 924 | |
| 958 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_4 925 | |
| 959 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_4_Rot_180 926 | |
| 960 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_4_Rot_270 927 | |
| 961 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_4_Rot_90 928 | |
| 962 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_5 929 | |
| 963 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_5_Rot_180 930 | |
| 964 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_5_Rot_270 931 | |
| 965 | #define IDR_VP_YUY2_444Scale16_Chromasiting_Buf_5_Rot_90 932 | |
| 966 | #define IDR_VP_camera_pipe_CalcParams 933 | |
| 967 | #define IDR_VP_fast_avs_1_to_n 934 | |
| 968 | #define IDR_VP_return 935 | |
| 969 | #define IDR_VP_sampler_scaling 936 | |
| 970 | #define IDR_VP_zzz_preproduction 937 | |
| 971 | #define IDR_VP_zzz_preproduction_ALLPL2Copy_Gen 938 | |
| 972 | #define IDR_VP_zzz_preproduction_HDR_mandatory_Gen 939 | |
| 973 | #define IDR_VP_zzz_preproduction_HDR_per_frame_stat_Gen 940 | |
| 974 | #define IDR_VP_zzz_preproduction_gcBltPS_32_To_128_Mirror_Gen 941 | |
| 975 | #define IDR_VP_zzz_preproduction_gcBltPS_64_To_128_Mirror_Gen 942 | |
| 976 | #define IDR_VP_zzz_preproduction_gcBltPS_Gen 943 | |
| 977 | #define IDR_VP_zzz_preproduction_gcBlt_D11 944 | |
| 978 | #define IDR_VP_zzz_preproduction_gcClearNoReplicatePS_Gen 945 | |
| 979 | #define IDR_VP_zzz_preproduction_gcClearReplicatePS_Gen 946 | |
| 980 | #define IDR_VP_zzz_preproduction_gcClear_NoReplicate_D11 947 | |
| 981 | #define IDR_VP_zzz_preproduction_gcClear_Replicate_D11 948 | |
| 982 | #define IDR_VP_zzz_preproduction_gcColorFillNoReplicatePS_Gen 949 | |
| 983 | #define IDR_VP_zzz_preproduction_gcColorFillReplicatePS_Gen 950 | |
| 984 | #define IDR_VP_zzz_preproduction_gcFastClearReplicatePS_Gen 951 | |
| 985 | #define IDR_VP_zzz_preproduction_gcFastClear_Replicate_D11 952 | |
| 986 | #define IDR_VP_zzz_preproduction_gcResourceCopy_D11 953 | |
| 987 | #define IDR_VP_zzz_production 954 | |
| 988 | #define IDR_VP_zzz_production_ALLPL2Copy_Gen 955 | |
| 989 | #define IDR_VP_zzz_production_HDR_mandatory_Gen 956 | |
| 990 | #define IDR_VP_zzz_production_HDR_per_frame_stat_Gen 957 | |
| 991 | #define IDR_VP_zzz_production_gcBltPS_32_To_128_Mirror_Gen 958 | |
| 992 | #define IDR_VP_zzz_production_gcBltPS_64_To_128_Mirror_Gen 959 | |
| 993 | #define IDR_VP_zzz_production_gcBltPS_Gen 960 | |
| 994 | #define IDR_VP_zzz_production_gcBlt_D11 961 | |
| 995 | #define IDR_VP_zzz_production_gcClearNoReplicatePS_Gen 962 | |
| 996 | #define IDR_VP_zzz_production_gcClearReplicatePS_Gen 963 | |
| 997 | #define IDR_VP_zzz_production_gcClear_NoReplicate_D11 964 | |
| 998 | #define IDR_VP_zzz_production_gcClear_Replicate_D11 965 | |
| 999 | #define IDR_VP_zzz_production_gcColorFillNoReplicatePS_Gen 966 | |
| 1000 | #define IDR_VP_zzz_production_gcColorFillReplicatePS_Gen 967 | |
| 1001 | #define IDR_VP_zzz_production_gcFastClearReplicatePS_Gen 968 | |
| 1002 | #define IDR_VP_zzz_production_gcFastClear_Replicate_D11 969 | |
| 1003 | #define IDR_VP_zzz_production_gcResourceCopy_D11 970 | |
| 1004 | #define IDR_VP_TOTAL_NUM_KERNELS 971 | |
| 1002 | 1005 | |
| 1003 | 1006 | #if _DEBUG || _RELEASE_INTERNAL |
| 1004 | 1007 | #define IDR_VP_KERNEL_NAMES \ |
| 1046 | 1049 | _T("ConstSrcBlend_444_16"),\ |
| 1047 | 1050 | _T("CopyKernel_1D_to_2D_NV12_genx"),\ |
| 1048 | 1051 | _T("CopyKernel_1D_to_2D_RGBP_genx"),\ |
| 1052 | _T("CopyKernel_1D_to_2D_genx"),\ | |
| 1049 | 1053 | _T("CopyKernel_2D_to_1D_NV12_genx"),\ |
| 1050 | 1054 | _T("CopyKernel_2D_to_1D_RGBP_genx"),\ |
| 1055 | _T("CopyKernel_2D_to_1D_genx"),\ | |
| 1051 | 1056 | _T("CopyKernel_2D_to_2D_NV12_genx"),\ |
| 1052 | 1057 | _T("CopyKernel_2D_to_2D_RGBP_genx"),\ |
| 1058 | _T("CopyKernel_2D_to_2D_genx"),\ | |
| 1053 | 1059 | _T("DP_FC_Setup_Walker_16x16"),\ |
| 1054 | 1060 | _T("DP_FC_Setup_Walker_4x4"),\ |
| 1055 | 1061 | _T("DP_FC_Setup_Walker_8x8"),\ |
| 2941 | 2947 | _T("965"),\ |
| 2942 | 2948 | _T("966"),\ |
| 2943 | 2949 | _T("967"),\ |
| 2950 | _T("968"),\ | |
| 2951 | _T("969"),\ | |
| 2952 | _T("970"),\ | |
| 2944 | 2953 | _T("") |
| 2945 | 2954 | #endif // _DEBUG |
| 2946 | 2955 | |
| 0 | 0 | /* |
| 1 | * Copyright (c) 2009-2018, Intel Corporation | |
| 1 | * Copyright (c) 2009-2021, Intel Corporation | |
| 2 | 2 | * |
| 3 | 3 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 4 | 4 | * copy of this software and associated documentation files (the "Software"), |
| 30 | 30 | #ifndef __RENDERHAL_G10_H__ |
| 31 | 31 | #define __RENDERHAL_G10_H__ |
| 32 | 32 | |
| 33 | #include "renderhal_platform_interface.h" | |
| 33 | #include "renderhal_platform_interface_legacy.h" | |
| 34 | 34 | #include "mhw_render_hwcmd_g10_X.h" |
| 35 | 35 | #include "mhw_state_heap_hwcmd_g10_X.h" |
| 36 | 36 | |
| 43 | 43 | |
| 44 | 44 | extern const RENDERHAL_STATE_HEAP_SETTINGS g_cRenderHal_State_Heap_Settings_g10; |
| 45 | 45 | |
| 46 | class XRenderHal_Interface_g10 : public XRenderHal_Platform_Interface | |
| 46 | class XRenderHal_Interface_g10 : public XRenderHal_Platform_Interface_Legacy | |
| 47 | 47 | { |
| 48 | 48 | public: |
| 49 | 49 | XRenderHal_Interface_g10() {} |
| 477 | 477 | if (bAllocated) |
| 478 | 478 | { |
| 479 | 479 | // Report Compress Status |
| 480 | m_reporting->FFDICompressible = bSurfCompressible; | |
| 481 | m_reporting->FFDICompressMode = (uint8_t)(SurfCompressionMode); | |
| 480 | m_reporting->GetFeatures().ffdiCompressible = bSurfCompressible; | |
| 481 | m_reporting->GetFeatures().ffdiCompressMode = (uint8_t)(SurfCompressionMode); | |
| 482 | 482 | } |
| 483 | 483 | } |
| 484 | 484 | } |
| 571 | 571 | if (bAllocated) |
| 572 | 572 | { |
| 573 | 573 | // Report Compress Status |
| 574 | m_reporting->FFDNCompressible = bFFDNSurfCompressible; | |
| 575 | m_reporting->FFDNCompressMode = (uint8_t)(FFDNSurfCompressionMode); | |
| 574 | m_reporting->GetFeatures().ffdnCompressible = bFFDNSurfCompressible; | |
| 575 | m_reporting->GetFeatures().ffdnCompressMode = (uint8_t)(FFDNSurfCompressionMode); | |
| 576 | 576 | } |
| 577 | 577 | } |
| 578 | 578 | } |
| 630 | 630 | VPHAL_RENDER_CHK_STATUS(VeboxInitSTMMHistory(i)); |
| 631 | 631 | |
| 632 | 632 | // Report Compress Status |
| 633 | m_reporting->STMMCompressible = bSurfCompressible; | |
| 634 | m_reporting->STMMCompressMode = (uint8_t)(SurfCompressionMode); | |
| 633 | m_reporting->GetFeatures().stmmCompressible = bSurfCompressible; | |
| 634 | m_reporting->GetFeatures().stmmCompressMode = (uint8_t)(SurfCompressionMode); | |
| 635 | 635 | } |
| 636 | 636 | } |
| 637 | 637 | } |
| 963 | 963 | sliceState.dwBatchBufferForPakSlicesStartOffset = batchBufferForPakSlicesStartOffset; |
| 964 | 964 | } |
| 965 | 965 | |
| 966 | if (m_avcRoundingParams != nullptr && m_avcRoundingParams->bEnableCustomRoudingIntra) | |
| 967 | { | |
| 968 | sliceState.dwRoundingIntraValue = m_avcRoundingParams->dwRoundingIntra; | |
| 969 | } | |
| 970 | else | |
| 971 | { | |
| 972 | sliceState.dwRoundingIntraValue = 5; | |
| 973 | } | |
| 974 | if (m_avcRoundingParams != nullptr && m_avcRoundingParams->bEnableCustomRoudingInter) | |
| 975 | { | |
| 976 | sliceState.bRoundingInterEnable = true; | |
| 977 | sliceState.dwRoundingValue = m_avcRoundingParams->dwRoundingInter; | |
| 978 | } | |
| 979 | else | |
| 980 | { | |
| 981 | sliceState.bRoundingInterEnable = m_roundingInterEnable; | |
| 982 | CODECHAL_ENCODE_CHK_STATUS_RETURN(GetInterRounding(&sliceState)); | |
| 983 | } | |
| 966 | CODECHAL_ENCODE_CHK_STATUS_RETURN(SetRounding(m_avcRoundingParams, &sliceState)); | |
| 984 | 967 | |
| 985 | 968 | sliceState.oneOnOneMapping = m_oneOnOneMapping; |
| 986 | 969 | CODECHAL_ENCODE_CHK_STATUS_RETURN(SendSlice(&cmdBuffer, &sliceState)); |
| 992 | 992 | return (m_numPipe <= 1) ? 0 : (int)(m_currPass) % (int)m_numPipe; |
| 993 | 993 | } |
| 994 | 994 | |
| 995 | int GetCurrentPass() | |
| 995 | int GetCurrentPass() override | |
| 996 | 996 | { |
| 997 | 997 | return (m_numPipe <= 1) ? m_currPass : (int)(m_currPass) / (int)m_numPipe; |
| 998 | 998 | } |
| 999 | 999 | |
| 1000 | int GetNumPasses() | |
| 1000 | int GetNumPasses() override | |
| 1001 | 1001 | { |
| 1002 | 1002 | return m_numPassesInOnePipe; |
| 1003 | 1003 | } |
| 1012 | 1012 | return (GetCurrentPipe() == 0) ? true : false; |
| 1013 | 1013 | } |
| 1014 | 1014 | |
| 1015 | bool IsFirstPass() | |
| 1015 | bool IsFirstPass() override | |
| 1016 | 1016 | { |
| 1017 | 1017 | return (GetCurrentPass() == 0) ? true : false; |
| 1018 | 1018 | } |
| 1019 | 1019 | |
| 1020 | bool IsLastPass() | |
| 1020 | bool IsLastPass() override | |
| 1021 | 1021 | { |
| 1022 | 1022 | return (GetCurrentPass() == m_numPassesInOnePipe) ? true : false; |
| 1023 | 1023 | } |
| 1031 | 1031 | { |
| 1032 | 1032 | return (m_osInterface->pfnGetGpuContext(m_osInterface) == m_renderContext); |
| 1033 | 1033 | } |
| 1034 | MOS_STATUS VerifyCommandBufferSize(); | |
| 1034 | ||
| 1035 | MOS_STATUS VerifyCommandBufferSize() override; | |
| 1035 | 1036 | |
| 1036 | 1037 | MOS_STATUS GetSystemPipeNumberCommon(); |
| 1037 | 1038 | |
| 1042 | 1043 | MeSurfaceParams * params); |
| 1043 | 1044 | |
| 1044 | 1045 | MOS_STATUS GetCommandBuffer( |
| 1045 | PMOS_COMMAND_BUFFER cmdBuffer); | |
| 1046 | PMOS_COMMAND_BUFFER cmdBuffer) override; | |
| 1046 | 1047 | |
| 1047 | 1048 | MOS_STATUS ReturnCommandBuffer( |
| 1048 | PMOS_COMMAND_BUFFER cmdBuffer); | |
| 1049 | PMOS_COMMAND_BUFFER cmdBuffer) override; | |
| 1049 | 1050 | |
| 1050 | 1051 | MOS_STATUS SubmitCommandBuffer( |
| 1051 | 1052 | PMOS_COMMAND_BUFFER cmdBuffer, |
| 1052 | bool nullRendering); | |
| 1053 | bool nullRendering) override; | |
| 1053 | 1054 | |
| 1054 | 1055 | MOS_STATUS SetMeCurbeParams( |
| 1055 | 1056 | MeCurbeParams* meParams); |
| 1060 | 1061 | MOS_STATUS SendPrologWithFrameTracking( |
| 1061 | 1062 | PMOS_COMMAND_BUFFER cmdBuffer, |
| 1062 | 1063 | bool frameTrackingRequested, |
| 1063 | MHW_MI_MMIOREGISTERS *mmioRegister = nullptr); | |
| 1064 | MHW_MI_MMIOREGISTERS *mmioRegister = nullptr) override; | |
| 1064 | 1065 | |
| 1065 | 1066 | MOS_STATUS SetSemaphoreMem( |
| 1066 | 1067 | PMOS_RESOURCE semaphoreMem, |
| 1067 | 1068 | PMOS_COMMAND_BUFFER cmdBuffer, |
| 1068 | 1069 | uint32_t value); |
| 1069 | 1070 | |
| 1070 | MOS_STATUS UserFeatureKeyReport(); | |
| 1071 | MOS_STATUS UserFeatureKeyReport() override; | |
| 1071 | 1072 | |
| 1072 | 1073 | MOS_STATUS SendMIAtomicCmd( |
| 1073 | 1074 | PMOS_RESOURCE semaMem, |
| 1082 | 1083 | uint32_t value); |
| 1083 | 1084 | |
| 1084 | 1085 | MOS_STATUS ConstructPicStateBatchBuf( |
| 1085 | PMOS_RESOURCE picStateBuffer); | |
| 1086 | PMOS_RESOURCE picStateBuffer) override; | |
| 1086 | 1087 | |
| 1087 | 1088 | MOS_STATUS SetDmemHuCPakInt(); |
| 1088 | 1089 | |
| 1089 | 1090 | MOS_STATUS HuCVp9PakInt( |
| 1090 | 1091 | PMOS_COMMAND_BUFFER cmdBuffer); |
| 1091 | 1092 | |
| 1092 | MOS_STATUS HuCVp9Prob(); | |
| 1093 | ||
| 1094 | MOS_STATUS HuCBrcUpdate(); | |
| 1095 | ||
| 1096 | MOS_STATUS HuCBrcInitReset(); | |
| 1093 | MOS_STATUS HuCVp9Prob() override; | |
| 1094 | ||
| 1095 | MOS_STATUS HuCBrcUpdate() override; | |
| 1096 | ||
| 1097 | MOS_STATUS HuCBrcInitReset() override; | |
| 1097 | 1098 | |
| 1098 | 1099 | MOS_STATUS SetHcpPipeBufAddrParams(MHW_VDBOX_PIPE_BUF_ADDR_PARAMS& pipeBufAddrParams, |
| 1099 | 1100 | PMOS_SURFACE* refSurface, |
| 1100 | 1101 | PMOS_SURFACE* refSurfaceNonScaled, |
| 1101 | 1102 | PMOS_SURFACE* dsRefSurface4x, |
| 1102 | PMOS_SURFACE* dsRefSurface8x); | |
| 1103 | PMOS_SURFACE* dsRefSurface8x) override; | |
| 1103 | 1104 | |
| 1104 | 1105 | uint16_t GetNumTilesInFrame(); |
| 1105 | 1106 | |
| 1106 | MOS_STATUS ExecutePictureLevel(); | |
| 1107 | ||
| 1108 | MOS_STATUS SetSequenceStructs(); | |
| 1109 | ||
| 1110 | MOS_STATUS SetPictureStructs(); | |
| 1111 | ||
| 1112 | MOS_STATUS AllocateResources(); | |
| 1113 | ||
| 1114 | void FreeResources(); | |
| 1107 | MOS_STATUS ExecutePictureLevel() override; | |
| 1108 | ||
| 1109 | MOS_STATUS SetSequenceStructs() override; | |
| 1110 | ||
| 1111 | MOS_STATUS SetPictureStructs() override; | |
| 1112 | ||
| 1113 | MOS_STATUS AllocateResources() override; | |
| 1114 | ||
| 1115 | void FreeResources() override; | |
| 1115 | 1116 | |
| 1116 | 1117 | MOS_STATUS SetCurbeMe( |
| 1117 | 1118 | MeCurbeParams *params); |
| 1118 | 1119 | |
| 1119 | MOS_STATUS ExecuteKernelFunctions(); | |
| 1120 | MOS_STATUS ExecuteKernelFunctions() override; | |
| 1120 | 1121 | |
| 1121 | 1122 | MOS_STATUS ExecuteMeKernel( |
| 1122 | 1123 | MeCurbeParams * meParams, |
| 1123 | 1124 | MeSurfaceParams *meSurfaceParams, |
| 1124 | HmeLevel hmeLevel); | |
| 1125 | ||
| 1126 | MOS_STATUS SetupSegmentationStreamIn(); | |
| 1127 | ||
| 1128 | void SetHcpPipeModeSelectParams(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& pipeModeSelectParams); | |
| 1129 | ||
| 1130 | void SetHcpIndObjBaseAddrParams(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS& indObjBaseAddrParams); | |
| 1131 | ||
| 1132 | MOS_STATUS ExecuteSliceLevel(); | |
| 1133 | ||
| 1134 | MOS_STATUS ExecuteDysSliceLevel(); | |
| 1135 | ||
| 1136 | MOS_STATUS Initialize(CodechalSetting * settings); | |
| 1125 | HmeLevel hmeLevel) override; | |
| 1126 | ||
| 1127 | MOS_STATUS SetupSegmentationStreamIn() override; | |
| 1128 | ||
| 1129 | void SetHcpPipeModeSelectParams(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS& pipeModeSelectParams) override; | |
| 1130 | ||
| 1131 | void SetHcpIndObjBaseAddrParams(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS& indObjBaseAddrParams) override; | |
| 1132 | ||
| 1133 | MOS_STATUS ExecuteSliceLevel() override; | |
| 1134 | ||
| 1135 | MOS_STATUS ExecuteDysSliceLevel() override; | |
| 1136 | ||
| 1137 | MOS_STATUS Initialize(CodechalSetting * settings) override; | |
| 1137 | 1138 | |
| 1138 | 1139 | MOS_STATUS InitKernelStates(); |
| 1139 | 1140 | |
| 1145 | 1146 | |
| 1146 | 1147 | MOS_STATUS SetTileData(); |
| 1147 | 1148 | |
| 1148 | MOS_STATUS SetGpuCtxCreatOption(); | |
| 1149 | MOS_STATUS SetGpuCtxCreatOption() override; | |
| 1149 | 1150 | |
| 1150 | 1151 | MOS_STATUS SetTileCommands( |
| 1151 | 1152 | PMOS_COMMAND_BUFFER cmdBuffer); |
| 1152 | 1153 | |
| 1153 | 1154 | MOS_STATUS GetStatusReport( |
| 1154 | 1155 | EncodeStatus* encodeStatus, |
| 1155 | EncodeStatusReport* encodeStatusReport); | |
| 1156 | EncodeStatusReport* encodeStatusReport) override; | |
| 1156 | 1157 | |
| 1157 | 1158 | MOS_STATUS DecideEncodingPipeNumber(); |
| 1158 | 1159 | |
| 1159 | MOS_STATUS PlatformCapabilityCheck(); | |
| 1160 | MOS_STATUS PlatformCapabilityCheck() override; | |
| 1160 | 1161 | |
| 1161 | 1162 | uint32_t GetSegmentBlockIndexInFrame( |
| 1162 | 1163 | uint32_t frameWidth, |
| 1171 | 1172 | uint32_t currTileStartYInFrame, |
| 1172 | 1173 | uint32_t currTileStartXInFrame); |
| 1173 | 1174 | |
| 1174 | MOS_STATUS CalculateVdencPictureStateCommandSize(); | |
| 1175 | MOS_STATUS CalculateVdencPictureStateCommandSize() override; | |
| 1175 | 1176 | |
| 1176 | 1177 | PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS CreateHcpPipeBufAddrParams( |
| 1177 | PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS pipeBufAddrParams); | |
| 1178 | PMHW_VDBOX_PIPE_BUF_ADDR_PARAMS pipeBufAddrParams) override; | |
| 1178 | 1179 | |
| 1179 | 1180 | MOS_STATUS UpdateCmdBufAttribute( |
| 1180 | 1181 | PMOS_COMMAND_BUFFER cmdBuffer, |
| 1181 | bool renderEngineInUse); | |
| 1182 | bool renderEngineInUse) override; | |
| 1182 | 1183 | |
| 1183 | 1184 | //! |
| 1184 | 1185 | //! \brief Set And Populate VE Hint parameters |
| 1293 | 1293 | cmd.DW5.MbSliceThresholdValue = params->dwMbSlcThresholdValue; |
| 1294 | 1294 | } |
| 1295 | 1295 | |
| 1296 | cmd.DW6.SliceMacroblockHeightMinusOne = params->wSlcHeightInMb - 1; | |
| 1296 | cmd.DW6.SliceMacroblockHeightMinusOne = params->wPicHeightInMb - 1; | |
| 1297 | 1297 | |
| 1298 | 1298 | cmd.DW8.LumaIntraPartitionMask = avcPicParams->transform_8x8_mode_flag ? 0 : TVdencCmds::VDENC_IMG_STATE_CMD::LUMA_INTRA_PARTITION_MASK_UNNAMED2; |
| 1299 | 1299 |
| 0 | 0 | /* |
| 1 | * Copyright (c) 2017-2018, Intel Corporation | |
| 1 | * Copyright (c) 2017-2021, Intel Corporation | |
| 2 | 2 | * |
| 3 | 3 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 4 | 4 | * copy of this software and associated documentation files (the "Software"), |
| 26 | 26 | #ifndef __RENDERHAL_G11_H__ |
| 27 | 27 | #define __RENDERHAL_G11_H__ |
| 28 | 28 | |
| 29 | #include "renderhal_platform_interface.h" | |
| 29 | #include "renderhal_platform_interface_legacy.h" | |
| 30 | 30 | #include "mhw_render_hwcmd_g11_X.h" |
| 31 | 31 | #include "mhw_state_heap_hwcmd_g11_X.h" |
| 32 | 32 | #include "mhw_render_g11_X.h" |
| 43 | 43 | |
| 44 | 44 | #define RENDERHAL_SAMPLERS_AVS_G11 6 |
| 45 | 45 | |
| 46 | class XRenderHal_Interface_g11 : public XRenderHal_Platform_Interface | |
| 46 | class XRenderHal_Interface_g11 : public XRenderHal_Platform_Interface_Legacy | |
| 47 | 47 | { |
| 48 | 48 | public: |
| 49 | 49 | XRenderHal_Interface_g11() {} |
| 484 | 484 | if (bAllocated) |
| 485 | 485 | { |
| 486 | 486 | // Report Compress Status |
| 487 | m_reporting->FFDICompressible = bSurfCompressible; | |
| 488 | m_reporting->FFDICompressMode = (uint8_t)(SurfCompressionMode); | |
| 487 | m_reporting->GetFeatures().ffdiCompressible = bSurfCompressible; | |
| 488 | m_reporting->GetFeatures().ffdiCompressMode = (uint8_t)(SurfCompressionMode); | |
| 489 | 489 | } |
| 490 | 490 | } |
| 491 | 491 | } |
| 578 | 578 | if (bAllocated) |
| 579 | 579 | { |
| 580 | 580 | // Report Compress Status |
| 581 | m_reporting->FFDNCompressible = bFFDNSurfCompressible; | |
| 582 | m_reporting->FFDNCompressMode = (uint8_t)(FFDNSurfCompressionMode); | |
| 581 | m_reporting->GetFeatures().ffdnCompressible = bFFDNSurfCompressible; | |
| 582 | m_reporting->GetFeatures().ffdnCompressMode = (uint8_t)(FFDNSurfCompressionMode); | |
| 583 | 583 | } |
| 584 | 584 | } |
| 585 | 585 | } |
| 637 | 637 | VPHAL_RENDER_CHK_STATUS(VeboxInitSTMMHistory(i)); |
| 638 | 638 | |
| 639 | 639 | // Report Compress Status |
| 640 | m_reporting->STMMCompressible = bSurfCompressible; | |
| 641 | m_reporting->STMMCompressMode = (uint8_t)(SurfCompressionMode); | |
| 640 | m_reporting->GetFeatures().stmmCompressible = bSurfCompressible; | |
| 641 | m_reporting->GetFeatures().stmmCompressMode = (uint8_t)(SurfCompressionMode); | |
| 642 | 642 | } |
| 643 | 643 | } |
| 644 | 644 | } |
| 751 | 751 | m_resDataBuffer = *(m_decodeParams.m_dataBuffer); |
| 752 | 752 | } |
| 753 | 753 | |
| 754 | if (m_hevcPicParams->RequestCRC) | |
| 755 | { | |
| 756 | m_reportFrameCrc = true; | |
| 757 | } | |
| 754 | m_reportFrameCrc = true; | |
| 758 | 755 | |
| 759 | 756 | CODECHAL_DECODE_CHK_STATUS_RETURN(CheckAndCopyBitstream()); |
| 760 | 757 | |
| 2271 | 2268 | CODECHAL_DECODE_CHK_NULL_RETURN(settings); |
| 2272 | 2269 | |
| 2273 | 2270 | CODECHAL_DECODE_CHK_STATUS_RETURN(InitMmcState()); |
| 2274 | ||
| 2275 | #if (_DEBUG || _RELEASE_INTERNAL) | |
| 2276 | m_debugInterface->SetSWCrcMode(true); | |
| 2277 | #endif | |
| 2278 | 2271 | |
| 2279 | 2272 | m_width = settings->width; |
| 2280 | 2273 | m_height = settings->height; |
| 542 | 542 | if (!CodecHal_PictureIsField(m_vc1PicParams->CurrPic) && |
| 543 | 543 | m_vc1PicParams->picture_fields.picture_type == vc1SkippedFrame) |
| 544 | 544 | { |
| 545 | if (!bSkipFrameReported) | |
| 546 | { | |
| 547 | MOS_USER_FEATURE_VALUE_WRITE_DATA userFeatureWriteData; | |
| 548 | MOS_ZeroMemory(&userFeatureWriteData, sizeof(userFeatureWriteData)); | |
| 549 | userFeatureWriteData.Value.i32Data = true; | |
| 550 | userFeatureWriteData.ValueID = __MEDIA_USER_FEATURE_VALUE_SKIP_FRAME_IN_USE_ID; | |
| 551 | MOS_UserFeature_WriteValues_ID(nullptr, &userFeatureWriteData, 1, m_osInterface->pOsContext); | |
| 552 | bSkipFrameReported = true; | |
| 553 | } | |
| 554 | ||
| 545 | 555 | CODECHAL_DECODE_CHK_STATUS_RETURN(HandleSkipFrame()); |
| 546 | 556 | goto submit; |
| 547 | 557 | } |
| 849 | 859 | |
| 850 | 860 | if (m_olpNeeded) |
| 851 | 861 | { |
| 862 | if (!bOlpReported) | |
| 863 | { | |
| 864 | MOS_USER_FEATURE_VALUE_WRITE_DATA userFeatureWriteData; | |
| 865 | MOS_ZeroMemory(&userFeatureWriteData, sizeof(userFeatureWriteData)); | |
| 866 | userFeatureWriteData.Value.i32Data = m_olpNeeded; | |
| 867 | userFeatureWriteData.ValueID = __MEDIA_USER_FEATURE_VALUE_OLP_IN_USE_ID; | |
| 868 | MOS_UserFeature_WriteValues_ID(nullptr, &userFeatureWriteData, 1, m_osInterface->pOsContext); | |
| 869 | bOlpReported = true; | |
| 870 | } | |
| 871 | ||
| 852 | 872 | CODECHAL_DECODE_CHK_STATUS_RETURN(PerformVc1Olp()); |
| 853 | 873 | } |
| 854 | 874 | else |
| 99 | 99 | uint32_t m_HucStateCmdBufferSizeNeeded = 0; |
| 100 | 100 | //! \Huc state level patch list size is required |
| 101 | 101 | uint32_t m_HucPatchListSizeNeeded = 0; |
| 102 | //! \Record whether status reported | |
| 103 | bool bOlpReported = 0; | |
| 104 | bool bSkipFrameReported = 0; | |
| 102 | 105 | }; |
| 103 | 106 | #endif // __CODECHAL_DECODER_VC1_G12_H__ |
| 1264 | 1264 | |
| 1265 | 1265 | CODECHAL_DECODE_CHK_STATUS_RETURN(InitMmcState()); |
| 1266 | 1266 | |
| 1267 | #if (_DEBUG || _RELEASE_INTERNAL) | |
| 1268 | m_debugInterface->SetSWCrcMode(true); | |
| 1269 | #endif | |
| 1270 | ||
| 1271 | 1267 | m_width = settings->width; |
| 1272 | 1268 | m_height = settings->height; |
| 1273 | 1269 | if (settings->lumaChromaDepth & CODECHAL_LUMA_CHROMA_DEPTH_8_BITS) |
| 41 | 41 | MOS_FUNCTION_ENTER(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_ENCODE); |
| 42 | 42 | MOS_CHK_NULL_RETURN(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_ENCODE, pipeBufAddrParams); |
| 43 | 43 | MOS_CHK_NULL_RETURN(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_ENCODE, pipeBufAddrParams->psRawSurface); |
| 44 | MOS_CHK_NULL_RETURN(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_ENCODE, pipeBufAddrParams->pRawSurfParam); | |
| 44 | 45 | |
| 45 | 46 | if (m_mmcEnabled) |
| 46 | 47 | { |
| 47 | 48 | MOS_CHK_STATUS_RETURN(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_ENCODE, m_osInterface->pfnGetMemoryCompressionMode(m_osInterface, |
| 48 | 49 | &pipeBufAddrParams->psRawSurface->OsResource, &pipeBufAddrParams->RawSurfMmcState)); |
| 50 | MOS_CHK_STATUS_RETURN(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_ENCODE, m_osInterface->pfnGetMemoryCompressionFormat(m_osInterface, | |
| 51 | &pipeBufAddrParams->psRawSurface->OsResource, &pipeBufAddrParams->pRawSurfParam->dwCompressionFormat)); | |
| 49 | 52 | } |
| 50 | 53 | else |
| 51 | 54 | { |
| 1551 | 1551 | } |
| 1552 | 1552 | } |
| 1553 | 1553 | |
| 1554 | MOS_STATUS CodechalVdencAvcStateG12::PrepareHWMetaData( | |
| 1555 | PMOS_RESOURCE presMetadataBuffer, | |
| 1556 | PMOS_RESOURCE presSliceSizeStreamoutBuffer, | |
| 1557 | PMOS_COMMAND_BUFFER cmdBuffer) | |
| 1558 | { | |
| 1559 | CODECHAL_ENCODE_FUNCTION_ENTER; | |
| 1560 | MOS_STATUS eStatus = MOS_STATUS_SUCCESS; | |
| 1561 | ||
| 1562 | if (!presMetadataBuffer) | |
| 1563 | { | |
| 1564 | return eStatus; | |
| 1565 | } | |
| 1566 | ||
| 1567 | MHW_MI_STORE_REGISTER_MEM_PARAMS miStoreRegMemParamsAVC; | |
| 1568 | MOS_ZeroMemory(&miStoreRegMemParamsAVC, sizeof(miStoreRegMemParamsAVC)); | |
| 1569 | miStoreRegMemParamsAVC.presStoreBuffer = presSliceSizeStreamoutBuffer; | |
| 1570 | miStoreRegMemParamsAVC.dwOffset = 0; | |
| 1571 | ||
| 1572 | CODECHAL_ENCODE_CHK_COND_RETURN((m_vdboxIndex > m_hwInterface->GetMfxInterface()->GetMaxVdboxIndex()), "ERROR - vdbox index exceed the maximum"); | |
| 1573 | MmioRegistersMfx *mmioRegisters = m_hwInterface->SelectVdboxAndGetMmioRegister(m_vdboxIndex, cmdBuffer); | |
| 1574 | miStoreRegMemParamsAVC.dwRegister = mmioRegisters->mfcBitstreamBytecountFrameRegOffset; | |
| 1575 | CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiStoreRegisterMemCmd(cmdBuffer, &miStoreRegMemParamsAVC)); | |
| 1576 | ||
| 1577 | eStatus = CodechalVdencAvcState::PrepareHWMetaData(presMetadataBuffer, presSliceSizeStreamoutBuffer, cmdBuffer); | |
| 1578 | ||
| 1579 | return eStatus; | |
| 1580 | } | |
| 1581 | ||
| 1582 | 1554 | #if USE_CODECHAL_DEBUG_TOOL |
| 1583 | 1555 | MOS_STATUS CodechalVdencAvcStateG12::PopulateBrcInitParam( |
| 1584 | 1556 | void *cmd) |
| 153 | 153 | //! |
| 154 | 154 | MOS_STATUS SetAndPopulateVEHintParams( |
| 155 | 155 | PMOS_COMMAND_BUFFER cmdBuffer); |
| 156 | //! | |
| 157 | //! \brief Prepare HW MetaData buffer | |
| 158 | //! \details Prepare HW MetaData buffer (with G12 specific) | |
| 159 | //! \param [in] presMetadataBuffer | |
| 160 | //! Pointer to allocated HW MetaData buffer | |
| 161 | //! [in] presSliceSizeStreamoutBuffer | |
| 162 | //! Pointer to m_pakSliceSizeStreamoutBuffer | |
| 163 | //! [in] cmdBuffer | |
| 164 | //! Pointer to primary cmd buffer | |
| 165 | //! \return MOS_STATUS | |
| 166 | //! MOS_STATUS_SUCCESS if success, else fail reason | |
| 167 | //! | |
| 168 | virtual MOS_STATUS PrepareHWMetaData( | |
| 169 | PMOS_RESOURCE presMetadataBuffer, | |
| 170 | PMOS_RESOURCE presSliceSizeStreamoutBuffer, | |
| 171 | PMOS_COMMAND_BUFFER cmdBuffer) override; | |
| 172 | 156 | |
| 173 | 157 | //! |
| 174 | 158 | //! \brief Set VDENC StreamIn QP Surface state |
| 6313 | 6313 | m_osInterface->pOsContext); |
| 6314 | 6314 | m_CaptureModeEnable = userFeatureData.i32Data ? true : false; |
| 6315 | 6315 | |
| 6316 | #if (_DEBUG || _RELEASE_INTERNAL) | |
| 6317 | MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData)); | |
| 6318 | MOS_UserFeature_ReadValue_ID( | |
| 6319 | nullptr, | |
| 6320 | __MEDIA_USER_FEATURE_VALUE_HEVC_VDENC_TCBRC_ARB_DISABLE_ID, | |
| 6321 | &userFeatureData, | |
| 6322 | m_osInterface->pOsContext); | |
| 6323 | m_brcAdaptiveRegionBoostSupported = userFeatureData.i32Data ? false : m_brcAdaptiveRegionBoostSupported; | |
| 6324 | #endif | |
| 6325 | ||
| 6316 | 6326 | // common initilization |
| 6317 | 6327 | CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalVdencHevcState::Initialize(settings)); |
| 6318 | 6328 |
| 0 | 0 | /* |
| 1 | * Copyright (c) 2017-2019, Intel Corporation | |
| 1 | * Copyright (c) 2017-2021, Intel Corporation | |
| 2 | 2 | * |
| 3 | 3 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 4 | 4 | * copy of this software and associated documentation files (the "Software"), |
| 3839 | 3839 | CODECHAL_ENCODE_CHK_STATUS_RETURN(StartStatusReport(&cmdBuffer, CODECHAL_NUM_MEDIA_STATES)); |
| 3840 | 3840 | } |
| 3841 | 3841 | |
| 3842 | // Send VDENC_CONTROL_STATE Pipe Initialization | |
| 3843 | MHW_VDBOX_VDENC_CONTROL_STATE_PARAMS vdencControlStateParams; | |
| 3844 | { | |
| 3845 | MOS_ZeroMemory(&vdencControlStateParams, sizeof(MHW_VDBOX_VDENC_CONTROL_STATE_PARAMS)); | |
| 3846 | vdencControlStateParams.bVdencInitialization = true; | |
| 3847 | CODECHAL_ENCODE_CHK_STATUS_RETURN( | |
| 3848 | static_cast<MhwVdboxVdencInterfaceG12X *>(m_vdencInterface)->AddVdencControlStateCmd(&cmdBuffer, &vdencControlStateParams)); | |
| 3849 | } | |
| 3850 | ||
| 3842 | 3851 | //Send VD_CONTROL_STATE Pipe Initialization |
| 3843 | 3852 | MHW_MI_VD_CONTROL_STATE_PARAMS vdCtrlParam; |
| 3844 | 3853 | MOS_ZeroMemory(&vdCtrlParam, sizeof(MHW_MI_VD_CONTROL_STATE_PARAMS)); |
| 0 | /* | |
| 1 | * Copyright (c) 2017-2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codec_def_decode_av1.h | |
| 23 | //! \brief Defines decode AV1 types and macros shared by CodecHal, MHW, and DDI layer | |
| 24 | //! \details Applies to AV1 decode only. Should not contain any DDI specific code. | |
| 25 | //! | |
| 26 | #ifndef __CODEC_DEF_DECODE_AV1_H__ | |
| 27 | #define __CODEC_DEF_DECODE_AV1_H__ | |
| 28 | ||
| 29 | #include "codec_def_common_av1.h" | |
| 30 | ||
| 31 | #define CODECHAL_MAX_DPB_NUM_AV1 127 // Maximum number of uncompressed decoded buffers that driver supports for non-LST mode | |
| 32 | #define CODEC_NUM_REF_AV1_TEMP_BUFFERS 8 | |
| 33 | #define CODEC_NUM_AV1_SECOND_BB 64 | |
| 34 | #define CODEC_NUM_AV1_TEMP_BUFFERS (CODEC_NUM_REF_AV1_TEMP_BUFFERS + 1) //!< Temp buffers number | |
| 35 | #define CODECHAL_MAX_DPB_NUM_LST_AV1 255 // Maximum number of uncompressed decoded buffers that driver supports with LST support | |
| 36 | ||
| 37 | // AV1 parameters definition | |
| 38 | ||
| 39 | //! | |
| 40 | //! \struct CodecAv1FilmGrainParams | |
| 41 | //! \brief Define the film grain parameters for AV1 | |
| 42 | //! | |
| 43 | struct CodecAv1FilmGrainParams | |
| 44 | { | |
| 45 | union | |
| 46 | { | |
| 47 | struct | |
| 48 | { | |
| 49 | uint32_t m_applyGrain : 1; //!< apply Grain flag | |
| 50 | uint32_t m_chromaScalingFromLuma : 1; //!< chroma scaling from luma | |
| 51 | uint32_t m_grainScalingMinus8 : 2; //!< Grain scaling minus 8 | |
| 52 | uint32_t m_arCoeffLag : 2; //!< AR Coeff lag | |
| 53 | uint32_t m_arCoeffShiftMinus6 : 2; //!< AR coeff shift minus 6 | |
| 54 | uint32_t m_grainScaleShift : 2; //!< grain scale shift | |
| 55 | uint32_t m_overlapFlag : 1; //!< overlap flag | |
| 56 | uint32_t m_clipToRestrictedRange : 1; //!< clip to restricted range flag | |
| 57 | uint32_t m_reservedBits : 20; //!< reserved bits | |
| 58 | } m_fields; | |
| 59 | uint32_t m_value; //!< film grain info flag value | |
| 60 | } m_filmGrainInfoFlags; | |
| 61 | ||
| 62 | uint16_t m_randomSeed; //!< random seed | |
| 63 | uint8_t m_numYPoints; //!< num Y points, range [0..14] | |
| 64 | uint8_t m_pointYValue[14]; //!< point Y value array | |
| 65 | uint8_t m_pointYScaling[14]; //!< point Y scaling array | |
| 66 | uint8_t m_numCbPoints; //!< num Cb Points, range [0..10] | |
| 67 | uint8_t m_pointCbValue[10]; //!< point Cb Value | |
| 68 | uint8_t m_pointCbScaling[10]; //!< point Cb Scaling | |
| 69 | uint8_t m_numCrPoints; //!< num Cr Points, range [0..10] | |
| 70 | uint8_t m_pointCrValue[10]; //!< point Cr Value | |
| 71 | uint8_t m_pointCrScaling[10]; //!< point Cr Scaling | |
| 72 | int8_t m_arCoeffsY[24]; //!< ar coeffs for Y, range [-128..127] | |
| 73 | int8_t m_arCoeffsCb[25]; //!< ar coeffs for Cb, range [-128..127] | |
| 74 | int8_t m_arCoeffsCr[25]; //!< ar coeffs for Cr, range [-128..127] | |
| 75 | uint8_t m_cbMult; //!< cb multipler | |
| 76 | uint8_t m_cbLumaMult; //!< cb Luma Multipler | |
| 77 | uint16_t m_cbOffset; //!< cb offset, range [0..512] | |
| 78 | uint8_t m_crMult; //!< Cr multipler | |
| 79 | uint8_t m_crLumaMult; //!< Cr Luma Multipler | |
| 80 | uint16_t m_crOffset; //!< Cr Offset, range [0..512] | |
| 81 | uint32_t m_reservedDws[4]; //!< reserved DWs | |
| 82 | }; | |
| 83 | ||
| 84 | //! | |
| 85 | //! \struct CodecAv1PicParams | |
| 86 | //! \brief Define AV1 picture parameters | |
| 87 | //! | |
| 88 | struct CodecAv1PicParams | |
| 89 | { | |
| 90 | CODEC_PICTURE m_currPic; | |
| 91 | CODEC_PICTURE m_currDisplayPic; | |
| 92 | uint8_t m_profile; // [0..2] | |
| 93 | uint8_t m_anchorFrameInsertion; | |
| 94 | uint8_t m_anchorFrameNum; | |
| 95 | PMOS_SURFACE m_anchorFrameList; | |
| 96 | ||
| 97 | // sequence info | |
| 98 | uint8_t m_orderHintBitsMinus1; // [0..7] | |
| 99 | uint8_t m_bitDepthIdx; // [0..2] | |
| 100 | uint8_t m_matrixCoefficients; // [0..14] | |
| 101 | uint8_t m_reserved8b; | |
| 102 | ||
| 103 | union | |
| 104 | { | |
| 105 | struct | |
| 106 | { | |
| 107 | uint32_t m_stillPicture : 1; | |
| 108 | uint32_t m_use128x128Superblock : 1; | |
| 109 | uint32_t m_enableFilterIntra : 1; | |
| 110 | uint32_t m_enableIntraEdgeFilter : 1; | |
| 111 | ||
| 112 | // read_compound_tools | |
| 113 | uint32_t m_enableInterintraCompound : 1; // [0..1] | |
| 114 | uint32_t m_enableMaskedCompound : 1; // [0..1] | |
| 115 | ||
| 116 | uint32_t m_enableDualFilter : 1; | |
| 117 | uint32_t m_enableOrderHint : 1; | |
| 118 | uint32_t m_enableJntComp : 1; | |
| 119 | uint32_t m_enableCdef : 1; | |
| 120 | uint32_t m_reserved3b : 3; | |
| 121 | ||
| 122 | uint32_t m_monoChrome : 1; | |
| 123 | uint32_t m_colorRange : 1; | |
| 124 | uint32_t m_subsamplingX : 1; | |
| 125 | uint32_t m_subsamplingY : 1; | |
| 126 | uint32_t m_chromaSamplePosition : 1; | |
| 127 | uint32_t m_filmGrainParamsPresent : 1; | |
| 128 | uint32_t m_reservedSeqInfoBits : 13; | |
| 129 | } m_fields; | |
| 130 | uint32_t m_value; | |
| 131 | } m_seqInfoFlags; | |
| 132 | ||
| 133 | // frame info | |
| 134 | union | |
| 135 | { | |
| 136 | struct | |
| 137 | { | |
| 138 | uint32_t m_frameType : 2; | |
| 139 | uint32_t m_showFrame : 1; | |
| 140 | uint32_t m_showableFrame : 1; | |
| 141 | uint32_t m_errorResilientMode : 1; | |
| 142 | uint32_t m_disableCdfUpdate : 1; | |
| 143 | uint32_t m_allowScreenContentTools : 1; // [0..1] | |
| 144 | uint32_t m_forceIntegerMv : 1; // [0..1] | |
| 145 | uint32_t m_allowIntrabc : 1; | |
| 146 | uint32_t m_useSuperres : 1; | |
| 147 | uint32_t m_allowHighPrecisionMv : 1; | |
| 148 | uint32_t m_isMotionModeSwitchable : 1; | |
| 149 | uint32_t m_useRefFrameMvs : 1; | |
| 150 | uint32_t m_disableFrameEndUpdateCdf : 1; | |
| 151 | uint32_t m_uniformTileSpacingFlag : 1; | |
| 152 | uint32_t m_allowWarpedMotion : 1; | |
| 153 | uint32_t m_largeScaleTile : 1; | |
| 154 | uint32_t m_reservedPicInfoBits : 15; | |
| 155 | } m_fields; | |
| 156 | uint32_t m_value; | |
| 157 | } m_picInfoFlags; | |
| 158 | ||
| 159 | uint16_t m_frameWidthMinus1; // [0..65535] //!< Super-Res downscaled resolution | |
| 160 | uint16_t m_frameHeightMinus1; // [0..65535] //!< Super-Res downscaled resolution | |
| 161 | ||
| 162 | CODEC_PICTURE m_refFrameMap[8]; | |
| 163 | uint8_t m_refFrameIdx[7]; // [0..7] | |
| 164 | uint8_t m_primaryRefFrame; // [0..7] | |
| 165 | ||
| 166 | uint16_t m_outputFrameWidthInTilesMinus1;// [0..65535] | |
| 167 | uint16_t m_outputFrameHeightInTilesMinus1;// [0..65535] | |
| 168 | uint32_t m_reserved32b2; | |
| 169 | ||
| 170 | // deblocking filter | |
| 171 | uint8_t m_filterLevel[2]; // [0..63] | |
| 172 | uint8_t m_filterLevelU; // [0..63] | |
| 173 | uint8_t m_filterLevelV; // [0..63] | |
| 174 | union | |
| 175 | { | |
| 176 | struct | |
| 177 | { | |
| 178 | uint8_t m_sharpnessLevel : 3; // [0..7] | |
| 179 | uint8_t m_modeRefDeltaEnabled : 1; | |
| 180 | uint8_t m_modeRefDeltaUpdate : 1; | |
| 181 | uint8_t m_reservedField : 3; // [0] | |
| 182 | } m_fields; | |
| 183 | uint8_t m_value; | |
| 184 | } m_loopFilterInfoFlags; | |
| 185 | ||
| 186 | uint8_t m_orderHint; | |
| 187 | uint8_t m_superresScaleDenominator; // [9..16] | |
| 188 | uint8_t m_interpFilter; // [0..9] | |
| 189 | ||
| 190 | int8_t m_refDeltas[8]; // [-63..63] | |
| 191 | int8_t m_modeDeltas[2]; // [-63..63] | |
| 192 | ||
| 193 | // quantization | |
| 194 | uint16_t m_baseQindex; // [0..255] | |
| 195 | int8_t m_yDcDeltaQ; // [-63..63] | |
| 196 | int8_t m_uDcDeltaQ; // [-63..63] | |
| 197 | int8_t m_uAcDeltaQ; // [-63..63] | |
| 198 | int8_t m_vDcDeltaQ; // [-63..63] | |
| 199 | int8_t m_vAcDeltaQ; // [-63..63] | |
| 200 | uint8_t m_reserved8b2; | |
| 201 | ||
| 202 | // quantization_matrix | |
| 203 | union | |
| 204 | { | |
| 205 | struct | |
| 206 | { | |
| 207 | uint16_t m_usingQmatrix : 1; | |
| 208 | // valid only when using_qmatrix is 1. | |
| 209 | uint16_t m_qmY : 4; // [0..15] | |
| 210 | uint16_t m_qmU : 4; // [0..15] | |
| 211 | uint16_t m_qmV : 4; // [0..15] | |
| 212 | uint16_t m_reservedField : 3; // [0] | |
| 213 | } m_fields; | |
| 214 | uint16_t m_value; | |
| 215 | } m_qMatrixFlags; | |
| 216 | ||
| 217 | union | |
| 218 | { | |
| 219 | struct | |
| 220 | { | |
| 221 | // delta_q parameters | |
| 222 | uint32_t m_deltaQPresentFlag : 1; // [0..1] | |
| 223 | uint32_t m_log2DeltaQRes : 2; // [0..3] | |
| 224 | ||
| 225 | // delta_lf parameters | |
| 226 | uint32_t m_deltaLfPresentFlag : 1; // [0..1] | |
| 227 | uint32_t m_log2DeltaLfRes : 2; // [0..3] | |
| 228 | uint32_t m_deltaLfMulti : 1; // [0..1] | |
| 229 | ||
| 230 | // read_tx_mode | |
| 231 | uint32_t m_txMode : 2; // [0..3] | |
| 232 | ||
| 233 | // read_frame_reference_mode | |
| 234 | uint32_t m_referenceMode : 2; // [0..3] will be replaced by reference_select | |
| 235 | uint32_t m_reducedTxSetUsed : 1; // [0..1] | |
| 236 | ||
| 237 | // tiles | |
| 238 | uint32_t m_skipModePresent : 1; // [0..1] | |
| 239 | uint32_t m_reservedField : 19; // [0] | |
| 240 | } m_fields; | |
| 241 | uint32_t m_value; | |
| 242 | } m_modeControlFlags; | |
| 243 | ||
| 244 | CodecAv1SegmentsParams m_av1SegData; //!< segment data | |
| 245 | ||
| 246 | uint8_t m_tileCols; | |
| 247 | uint16_t m_widthInSbsMinus1[64]; //!< note: 64 not 63 | |
| 248 | uint8_t m_tileRows; | |
| 249 | uint16_t m_heightInSbsMinus1[64]; | |
| 250 | ||
| 251 | uint16_t m_tileCountMinus1; | |
| 252 | uint16_t m_contextUpdateTileId; | |
| 253 | ||
| 254 | // CDEF | |
| 255 | uint8_t m_cdefDampingMinus3; // [0..3] | |
| 256 | uint8_t m_cdefBits; // [0..3] | |
| 257 | uint8_t m_cdefYStrengths[8]; // [0..63] | |
| 258 | uint8_t m_cdefUvStrengths[8]; // [0..63] | |
| 259 | ||
| 260 | union | |
| 261 | { | |
| 262 | struct | |
| 263 | { | |
| 264 | uint16_t m_yframeRestorationType : 2; // [0..3] | |
| 265 | uint16_t m_cbframeRestorationType : 2; // [0..3] | |
| 266 | uint16_t m_crframeRestorationType : 2; // [0..3] | |
| 267 | uint16_t m_lrUnitShift : 2; // [0..2] | |
| 268 | uint16_t m_lrUvShift : 1; // [0..1] | |
| 269 | uint16_t m_reservedField : 7; // [0] | |
| 270 | } m_fields; | |
| 271 | uint16_t m_value; | |
| 272 | } m_loopRestorationFlags; | |
| 273 | ||
| 274 | // global motion | |
| 275 | CodecAv1WarpedMotionParams m_wm[7]; | |
| 276 | CodecAv1FilmGrainParams m_filmGrainParams; | |
| 277 | ||
| 278 | uint32_t m_bsBytesInBuffer; | |
| 279 | uint32_t m_statusReportFeedbackNumber; | |
| 280 | ||
| 281 | // Below are parameters for driver internal use only, not corresponding to any DDI parameter | |
| 282 | bool m_losslessMode; //!< frame lossless mode | |
| 283 | uint16_t m_superResUpscaledWidthMinus1; //!< Super-Res upscaled width, [0..65535] | |
| 284 | uint16_t m_superResUpscaledHeightMinus1; //!< Super-Res upscaled height, [0..65535] | |
| 285 | uint8_t m_activeRefBitMaskMfmv[7]; //!< active reference bitmask for Motion Field Projection, [0]: LAST_FRAME, [6]: ALTREF | |
| 286 | uint8_t m_refFrameSide[8]; //!< ref_frame_side for each reference | |
| 287 | }; | |
| 288 | ||
| 289 | struct CodecAv1TileParams | |
| 290 | { | |
| 291 | uint32_t m_bsTileDataLocation; | |
| 292 | uint32_t m_bsTileBytesInBuffer; | |
| 293 | uint16_t m_badBSBufferChopping; | |
| 294 | uint16_t m_tileRow; | |
| 295 | uint16_t m_tileColumn; | |
| 296 | uint16_t m_tileIndex; | |
| 297 | uint16_t m_reserved16b; | |
| 298 | uint16_t m_startTileIdx; | |
| 299 | uint16_t m_endTileIdx; | |
| 300 | uint16_t m_tile_idx_in_tile_list; | |
| 301 | CODEC_PICTURE m_anchorFrameIdx; | |
| 302 | uint32_t m_bsTilePayloadSizeInBytes; | |
| 303 | }; | |
| 304 | ||
| 305 | #endif // __CODEC_DEF_DECODE_AV1_H__ | |
| 306 |
| 21 | 21 | set(TMP_SOURCES_ "") |
| 22 | 22 | |
| 23 | 23 | set(TMP_HEADERS_ "") |
| 24 | ||
| 25 | if( ${AV1_Decode_Supported} STREQUAL "yes" ) | |
| 26 | set(TMP_HEADERS_ | |
| 27 | ${TMP_HEADERS_} | |
| 28 | ${CMAKE_CURRENT_LIST_DIR}/codec_def_decode_av1.h | |
| 29 | ) | |
| 30 | endif() | |
| 31 | 24 | |
| 32 | 25 | if ("${HEVC_Encode_VME_Supported}" STREQUAL "yes" OR "${HEVC_Encode_VDEnc_Supported}" STREQUAL "yes") |
| 33 | 26 | set(TMP_HEADERS_ |
| 2798 | 2798 | (uint32_t)pSurfaceParam->rcSrc.right, |
| 2799 | 2799 | *pdwSurfaceHeight, |
| 2800 | 2800 | *pdwSurfaceWidth); |
| 2801 | MT_LOG5(MT_VP_VE_ADJUST_SURFPARAM, MT_NORMAL, MT_VP_RENDER_VE_CROPPING, 1, MT_RECT_BOTTOM, pSurfaceParam->rcSrc.bottom, MT_RECT_RIGHT, pSurfaceParam->rcSrc.right, | |
| 2802 | MT_SURF_HEIGHT, *pdwSurfaceHeight, MT_SURF_WIDTH, *pdwSurfaceWidth); | |
| 2801 | 2803 | } |
| 2802 | 2804 | else |
| 2803 | 2805 | { |
| 717 | 717 | mhw_vdbox_mfx_g12_X::MFX_SURFACE_STATE_CMD cmd; |
| 718 | 718 | cmd.DW1.SurfaceId = params->ucSurfaceStateId; |
| 719 | 719 | |
| 720 | cmd.DW2.Height = params->psSurface->dwHeight - 1; | |
| 721 | cmd.DW2.Width = params->psSurface->dwWidth - 1; | |
| 720 | if (params->ucSurfaceStateId == CODECHAL_MFX_SRC_SURFACE_ID) // Take actual height/width from SPS in case of source surface | |
| 721 | { | |
| 722 | cmd.DW2.Height = params->dwActualHeight - 1; | |
| 723 | cmd.DW2.Width = params->dwActualWidth - 1; | |
| 724 | } | |
| 725 | else | |
| 726 | { | |
| 727 | cmd.DW2.Height = params->psSurface->dwHeight - 1; | |
| 728 | cmd.DW2.Width = params->psSurface->dwWidth - 1; | |
| 729 | } | |
| 722 | 730 | |
| 723 | 731 | cmd.DW3.TileWalk = mhw_vdbox_mfx_g12_X::MFX_SURFACE_STATE_CMD::TILE_WALK_YMAJOR; |
| 724 | 732 | cmd.DW3.TiledSurface = 1; |
| 1663 | 1663 | cmd.DW5.MbSliceThresholdValue = params->dwMbSlcThresholdValue; |
| 1664 | 1664 | } |
| 1665 | 1665 | |
| 1666 | cmd.DW6.SliceMacroblockHeightMinusOne = params->wSlcHeightInMb - 1; | |
| 1666 | cmd.DW6.SliceMacroblockHeightMinusOne = params->wPicHeightInMb - 1; | |
| 1667 | 1667 | |
| 1668 | 1668 | cmd.DW8.LumaIntraPartitionMask = avcPicParams->transform_8x8_mode_flag ? 0 : TVdencCmds::VDENC_IMG_STATE_CMD::LUMA_INTRA_PARTITION_MASK_UNNAMED2; |
| 1669 | 1669 |
| 681 | 681 | if (bAllocated) |
| 682 | 682 | { |
| 683 | 683 | // Report Compress Status |
| 684 | m_reporting->FFDICompressible = bSurfCompressible; | |
| 685 | m_reporting->FFDICompressMode = (uint8_t)(SurfCompressionMode); | |
| 684 | m_reporting->GetFeatures().ffdiCompressible = bSurfCompressible; | |
| 685 | m_reporting->GetFeatures().ffdiCompressMode = (uint8_t)(SurfCompressionMode); | |
| 686 | 686 | } |
| 687 | 687 | } |
| 688 | 688 | } |
| 786 | 786 | if (bAllocated) |
| 787 | 787 | { |
| 788 | 788 | // Report Compress Status |
| 789 | m_reporting->FFDNCompressible = bFFDNSurfCompressible; | |
| 790 | m_reporting->FFDNCompressMode = (uint8_t)(FFDNSurfCompressionMode); | |
| 789 | m_reporting->GetFeatures().ffdnCompressible = bFFDNSurfCompressible; | |
| 790 | m_reporting->GetFeatures().ffdnCompressMode = (uint8_t)(FFDNSurfCompressionMode); | |
| 791 | 791 | } |
| 792 | 792 | } |
| 793 | 793 | } |
| 845 | 845 | VPHAL_RENDER_CHK_STATUS(VeboxInitSTMMHistory(i)); |
| 846 | 846 | |
| 847 | 847 | // Report Compress Status |
| 848 | m_reporting->STMMCompressible = bSurfCompressible; | |
| 849 | m_reporting->STMMCompressMode = (uint8_t)(SurfCompressionMode); | |
| 848 | m_reporting->GetFeatures().stmmCompressible = bSurfCompressible; | |
| 849 | m_reporting->GetFeatures().stmmCompressMode = (uint8_t)(SurfCompressionMode); | |
| 850 | 850 | } |
| 851 | 851 | } |
| 852 | 852 | } |
| 2388 | 2388 | VPHAL_RENDER_CHK_NULL_NO_STATUS(pcRenderParams); |
| 2389 | 2389 | VPHAL_RENDER_CHK_NULL_NO_STATUS(pRenderData); |
| 2390 | 2390 | VPHAL_RENDER_CHK_NULL_NO_STATUS(pSrcSurface); |
| 2391 | VPHAL_RENDER_CHK_NULL_NO_STATUS(pcRenderParams->pTarget[0]); | |
| 2392 | ||
| 2393 | pTarget = pcRenderParams->pTarget[0]; | |
| 2391 | 2394 | |
| 2392 | 2395 | bCompBypassFeasible = IS_COMP_BYPASS_FEASIBLE(pRenderData->bCompNeeded, pcRenderParams, pSrcSurface); |
| 2393 | 2396 | |
| 2410 | 2413 | goto finish; |
| 2411 | 2414 | } |
| 2412 | 2415 | |
| 2416 | // Let Kernel to output P010 instead of VEBOX output | |
| 2417 | if (pSrcSurface->p3DLutParams && | |
| 2418 | (pTarget->Format == Format_P010 || | |
| 2419 | pTarget->Format == Format_P016)) | |
| 2420 | { | |
| 2421 | OutputPipe = VPHAL_OUTPUT_PIPE_MODE_COMP; | |
| 2422 | goto finish; | |
| 2423 | } | |
| 2424 | ||
| 2413 | 2425 | bOutputPipeVeboxFeasible = IS_OUTPUT_PIPE_VEBOX_FEASIBLE(pVeboxState, pcRenderParams, pSrcSurface); |
| 2414 | 2426 | if (bOutputPipeVeboxFeasible) |
| 2415 | 2427 | { |
| 2422 | 2434 | OutputPipe = VPHAL_OUTPUT_PIPE_MODE_COMP; |
| 2423 | 2435 | goto finish; |
| 2424 | 2436 | } |
| 2425 | ||
| 2426 | pTarget = pcRenderParams->pTarget[0]; | |
| 2427 | VPHAL_RENDER_CHK_NULL_NO_STATUS(pcRenderParams->pTarget[0]); | |
| 2428 | 2437 | |
| 2429 | 2438 | bHDRToneMappingNeed = (pSrcSurface->pHDRParams || pTarget->pHDRParams); |
| 2430 | 2439 | // Check if SFC can be the output pipe |
| 0 | 0 | /* |
| 1 | * Copyright (c) 2009-2017, Intel Corporation | |
| 1 | * Copyright (c) 2009-2021, Intel Corporation | |
| 2 | 2 | * |
| 3 | 3 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 4 | 4 | * copy of this software and associated documentation files (the "Software"), |
| 30 | 30 | #ifndef __RENDERHAL_G8_H__ |
| 31 | 31 | #define __RENDERHAL_G8_H__ |
| 32 | 32 | |
| 33 | #include "renderhal_platform_interface.h" | |
| 33 | #include "renderhal_platform_interface_legacy.h" | |
| 34 | 34 | #include "mhw_render_hwcmd_g8_X.h" |
| 35 | 35 | #include "mhw_state_heap_hwcmd_g8_X.h" |
| 36 | 36 | #include "mhw_mmio_g8.h" |
| 84 | 84 | RENDERHAL_MO_CACHE_CONTROL_WB_G8 = 0x3 |
| 85 | 85 | } RENDERHAL_MO_CACHE_CONTROL_G8; |
| 86 | 86 | |
| 87 | class XRenderHal_Interface_g8 : public XRenderHal_Platform_Interface | |
| 87 | class XRenderHal_Interface_g8 : public XRenderHal_Platform_Interface_Legacy | |
| 88 | 88 | { |
| 89 | 89 | public: |
| 90 | 90 | XRenderHal_Interface_g8() {} |
| 0 | 0 | /* |
| 1 | * Copyright (c) 2012-2017, Intel Corporation | |
| 1 | * Copyright (c) 2012-2021, Intel Corporation | |
| 2 | 2 | * |
| 3 | 3 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 4 | 4 | * copy of this software and associated documentation files (the "Software"), |
| 30 | 30 | #ifndef __RENDERHAL_G9_H__ |
| 31 | 31 | #define __RENDERHAL_G9_H__ |
| 32 | 32 | |
| 33 | #include "renderhal_platform_interface.h" | |
| 33 | #include "renderhal_platform_interface_legacy.h" | |
| 34 | 34 | #include "mhw_render_hwcmd_g9_X.h" |
| 35 | 35 | #include "mhw_state_heap_hwcmd_g9_X.h" |
| 36 | 36 | #if (_RELEASE_INTERNAL || _DEBUG) |
| 93 | 93 | } WORK_QUEUE_CMD_GUC, *PWORK_QUEUE_CMD_GUC; |
| 94 | 94 | #endif |
| 95 | 95 | #endif |
| 96 | class XRenderHal_Interface_g9 : public XRenderHal_Platform_Interface | |
| 96 | class XRenderHal_Interface_g9 : public XRenderHal_Platform_Interface_Legacy | |
| 97 | 97 | { |
| 98 | 98 | public: |
| 99 | 99 | XRenderHal_Interface_g9() {} |
| 1630 | 1630 | |
| 1631 | 1631 | if (pHdrState->pSrcSurf[i]->SurfType == SURF_IN_PRIMARY) |
| 1632 | 1632 | { |
| 1633 | pHdrState->Reporting.HDRMode = pHdrState->HdrMode[i]; | |
| 1633 | pHdrState->Reporting.GetFeatures().hdrMode = pHdrState->HdrMode[i]; | |
| 1634 | 1634 | } |
| 1635 | 1635 | |
| 1636 | 1636 | // EOTF/CCM/Tone Mapping/OETF require RGB input |
| 2731 | 2731 | { |
| 2732 | 2732 | if (b3dLut) |
| 2733 | 2733 | { |
| 2734 | pHdrState->Reporting.HDRMode = (VPHAL_HDR_MODE)(((uint32_t)pHdrState->Reporting.HDRMode) | VPHAL_HDR_MODE_3DLUT_MASK); | |
| 2734 | pHdrState->Reporting.GetFeatures().hdrMode = (VPHAL_HDR_MODE)(((uint32_t)pHdrState->Reporting.GetFeatures().hdrMode) | VPHAL_HDR_MODE_3DLUT_MASK); | |
| 2735 | 2735 | } |
| 2736 | 2736 | } |
| 2737 | 2737 | |
| 473 | 473 | if (bAllocated) |
| 474 | 474 | { |
| 475 | 475 | // Report Compress Status |
| 476 | m_reporting->FFDICompressible = bSurfCompressible; | |
| 477 | m_reporting->FFDICompressMode = (uint8_t)(SurfCompressionMode); | |
| 476 | m_reporting->GetFeatures().ffdiCompressible = bSurfCompressible; | |
| 477 | m_reporting->GetFeatures().ffdiCompressMode = (uint8_t)(SurfCompressionMode); | |
| 478 | 478 | } |
| 479 | 479 | } |
| 480 | 480 | } |
| 567 | 567 | if (bAllocated) |
| 568 | 568 | { |
| 569 | 569 | // Report Compress Status |
| 570 | m_reporting->FFDNCompressible = bFFDNSurfCompressible; | |
| 571 | m_reporting->FFDNCompressMode = (uint8_t)(FFDNSurfCompressionMode); | |
| 570 | m_reporting->GetFeatures().ffdnCompressible = bFFDNSurfCompressible; | |
| 571 | m_reporting->GetFeatures().ffdnCompressMode = (uint8_t)(FFDNSurfCompressionMode); | |
| 572 | 572 | } |
| 573 | 573 | } |
| 574 | 574 | } |
| 626 | 626 | VPHAL_RENDER_CHK_STATUS(VeboxInitSTMMHistory(i)); |
| 627 | 627 | |
| 628 | 628 | // Report Compress Status |
| 629 | m_reporting->STMMCompressible = bSurfCompressible; | |
| 630 | m_reporting->STMMCompressMode = (uint8_t)(SurfCompressionMode); | |
| 629 | m_reporting->GetFeatures().stmmCompressible = bSurfCompressible; | |
| 630 | m_reporting->GetFeatures().stmmCompressMode = (uint8_t)(SurfCompressionMode); | |
| 631 | 631 | } |
| 632 | 632 | } |
| 633 | 633 | } |
| 1327 | 1327 | mediaCtx->uiNumBufs++; |
| 1328 | 1328 | |
| 1329 | 1329 | // return success if data is nullptr, no need to copy data |
| 1330 | if (data == nullptr || (VAEncMacroblockMapBufferType == type && m_cpuFormat)) | |
| 1330 | if (data == nullptr) | |
| 1331 | 1331 | { |
| 1332 | 1332 | return va; |
| 1333 | 1333 | } |
| 232 | 232 | seqParams->RateControlMethod = RATECONTROL_CQL; |
| 233 | 233 | } |
| 234 | 234 | |
| 235 | seqParams->TargetUsage = vp9TargetUsage; | |
| 235 | if (m_encodeCtx->bNewSeq) | |
| 236 | seqParams->TargetUsage = vp9TargetUsage; | |
| 236 | 237 | |
| 237 | 238 | /* If the segmentation is not enabled, the SegData will be reset */ |
| 238 | 239 | if (vp9PicParam->PicFlags.fields.segmentation_enabled == 0) |
| 141 | 141 | #define MEDIAAPI_EXPORT __attribute__((visibility("default"))) |
| 142 | 142 | |
| 143 | 143 | class MediaLibvaCaps; |
| 144 | class MediaLibvaCapsNext; | |
| 144 | 145 | |
| 145 | 146 | typedef enum _DDI_MEDIA_FORMAT |
| 146 | 147 | { |
| 549 | 550 | MEDIA_MUTEX_T PutSurfaceRenderMutex; |
| 550 | 551 | MEDIA_MUTEX_T PutSurfaceSwapBufferMutex; |
| 551 | 552 | #endif |
| 552 | bool m_apoMosEnabled; | |
| 553 | bool m_apoMosEnabled; | |
| 553 | 554 | DdiMediaFunctions *m_compList[CompCount]; |
| 554 | 555 | MediaInterfacesHwInfo *m_hwInfo; |
| 556 | MediaLibvaCapsNext *m_capsNext; | |
| 555 | 557 | }; |
| 556 | 558 | |
| 557 | 559 | static __inline PDDI_MEDIA_CONTEXT DdiMedia_GetMediaContext (VADriverContextP ctx) |
| 319 | 319 | hRes = VA_STATUS_ERROR_UNSUPPORTED_RT_FORMAT; |
| 320 | 320 | goto finish; |
| 321 | 321 | } |
| 322 | //different alignment requirement for different codec and different platform | |
| 323 | //for MPEG2 and AVC , it should be 16 | |
| 324 | //for HEVC on the platform pre-gen12 (include), it is 64 | |
| 325 | //may need api change for to convey different codec usage. | |
| 326 | if(VA_SURFACE_ATTRIB_USAGE_HINT_ENCODER & mediaSurface->surfaceUsageHint) | |
| 327 | { | |
| 328 | alignedWidth = MOS_ALIGN_CEIL(alignedWidth, 16); | |
| 329 | alignedHeight = MOS_ALIGN_CEIL(alignedHeight, 16); | |
| 330 | } | |
| 322 | 331 | |
| 323 | 332 | if (DdiMediaUtil_IsExternalSurface(mediaSurface)) |
| 324 | 333 | { |
| 53 | 53 | #endif |
| 54 | 54 | |
| 55 | 55 | //Read user feature key here for Per Utility Tool Enabling |
| 56 | #if _RELEASE_INTERNAL | |
| 57 | 56 | if (!g_perfutility->bPerfUtilityKey) |
| 58 | 57 | { |
| 59 | 58 | MOS_USER_FEATURE_VALUE_DATA UserFeatureData; |
| 87 | 86 | |
| 88 | 87 | g_perfutility->bPerfUtilityKey = true; |
| 89 | 88 | } |
| 90 | #endif | |
| 89 | ||
| 91 | 90 | return MOS_STATUS_SUCCESS; |
| 92 | 91 | } |
| 93 | 92 | |
| 65 | 65 | |
| 66 | 66 | typedef struct _MOS_OCA_RESOURCE_INFO |
| 67 | 67 | { |
| 68 | uint64_t gfxAddress; | |
| 68 | 69 | uint64_t sizeAllocation; |
| 69 | 70 | uint64_t sizeSurface; |
| 70 | 71 | uint64_t sizeSurfacePhy; |
| 402 | 403 | |
| 403 | 404 | PMOS_MUTEX m_ocaMutex = nullptr; |
| 404 | 405 | |
| 405 | bool m_isOcaEnabled = true; | |
| 406 | bool m_isOcaEnabled = false; | |
| 406 | 407 | bool m_isInitialized = false; |
| 407 | 408 | MOS_OCA_RESOURCE_INFO *m_resInfoPool = nullptr; |
| 408 | 409 | MOS_OCA_BUF_CONTEXT m_ocaBufContextList[MAX_NUM_OF_OCA_BUF_CONTEXT] = {}; |
| 378 | 378 | { |
| 379 | 379 | resMmcMode = MOS_MEMCOMP_DISABLED; |
| 380 | 380 | } |
| 381 | ||
| 381 | m_ocaBufContextList[ocaBufHandle].logSection.resInfo.resInfoList[i].gfxAddress = MosInterface::GetResourceGfxAddress(&steamState, &resource); | |
| 382 | 382 | m_ocaBufContextList[ocaBufHandle].logSection.resInfo.resInfoList[i].sizeAllocation = resource.pGmmResInfo->GetSizeAllocation(); |
| 383 | 383 | m_ocaBufContextList[ocaBufHandle].logSection.resInfo.resInfoList[i].sizeSurface = resource.pGmmResInfo->GetSizeSurface(); |
| 384 | 384 | m_ocaBufContextList[ocaBufHandle].logSection.resInfo.resInfoList[i].sizeSurfacePhy = resource.pGmmResInfo->GetSizeSurface(); |
| 6232 | 6232 | } |
| 6233 | 6233 | |
| 6234 | 6234 | //! |
| 6235 | //! \brief Get interface version | |
| 6236 | //! \details Get interface version | |
| 6237 | //! | |
| 6238 | //! \param PMOS_INTERFACE pOsInterface | |
| 6239 | //! [in] OS Interface | |
| 6240 | //! | |
| 6241 | //! \return uint32_t | |
| 6242 | //! Read-only OS runtime interface version, it's meaning diff from OS and API | |
| 6243 | //! | |
| 6244 | uint32_t Mos_Specific_GetInterfaceVersion( | |
| 6245 | PMOS_INTERFACE pOsInterface) | |
| 6246 | { | |
| 6247 | MOS_UNUSED(pOsInterface); | |
| 6248 | return 0; | |
| 6249 | } | |
| 6250 | ||
| 6251 | //! | |
| 6235 | 6252 | //! \brief Determines if the resource should be CPU cacheable during allocation |
| 6236 | 6253 | //! \param PMOS_INTERFACE pOsInterface |
| 6237 | 6254 | //! [in] Pointer to OS Interface |
| 7606 | 7623 | pOsInterface->pfnGetIndirectState = Mos_Specific_GetIndirectState; |
| 7607 | 7624 | pOsInterface->pfnGetIndirectStatePointer = Mos_Specific_GetIndirectStatePointer; |
| 7608 | 7625 | pOsInterface->pfnSetPatchEntry = Mos_Specific_SetPatchEntry; |
| 7626 | pOsInterface->pfnGetInterfaceVersion = Mos_Specific_GetInterfaceVersion; | |
| 7609 | 7627 | |
| 7610 | 7628 | pOsInterface->pfnLoadLibrary = Mos_Specific_LoadLibrary; |
| 7611 | 7629 | pOsInterface->pfnFreeLibrary = Mos_Specific_FreeLibrary; |
| 81 | 81 | return; |
| 82 | 82 | } |
| 83 | 83 | ocaBufHandle = GetOcaBufferHandle(cmdBuffer, mosContext); |
| 84 | if (ocaBufHandle) | |
| 85 | { | |
| 86 | OnOcaError(&mosContext, status, __FUNCTION__, __LINE__); | |
| 84 | if (ocaBufHandle != MOS_OCA_INVALID_BUFFER_HANDLE) | |
| 85 | { | |
| 86 | // will come here when On1stLevelBBStart being called twice without On1stLevelBBEnd being called. | |
| 87 | OnOcaError(&mosContext, MOS_STATUS_INVALID_PARAMETER, __FUNCTION__, __LINE__); | |
| 87 | 88 | return; |
| 88 | 89 | } |
| 89 | 90 | else |
| 91 | 92 | ocaBufHandle = pOcaInterface->LockOcaBufAvailable(&mosContext, gpuContextHandle); |
| 92 | 93 | if (MOS_OCA_INVALID_BUFFER_HANDLE == ocaBufHandle) |
| 93 | 94 | { |
| 94 | OnOcaError(&mosContext, MOS_STATUS_UNKNOWN, __FUNCTION__, __LINE__); | |
| 95 | OnOcaError(&mosContext, MOS_STATUS_INVALID_HANDLE, __FUNCTION__, __LINE__); | |
| 95 | 96 | return; |
| 96 | 97 | } |
| 97 | 98 | MosOcaAutoLock autoLock(mutex); |
| 168 | 169 | MOS_OCA_BUFFER_HANDLE ocaBufHandle = 0; |
| 169 | 170 | MOS_STATUS status = MOS_STATUS_SUCCESS; |
| 170 | 171 | |
| 171 | if (nullptr == pOcaInterface || !((MosOcaInterfaceSpecific*)pOcaInterface)->IsOcaEnabled() || (ocaBufHandle = GetOcaBufferHandle(cmdBuffer, mosContext)) >= MAX_NUM_OF_OCA_BUF_CONTEXT) | |
| 172 | if (nullptr == pOcaInterface || !((MosOcaInterfaceSpecific*)pOcaInterface)->IsOcaEnabled()) | |
| 172 | 173 | { |
| 173 | 174 | // Will come here for UMD_OCA not being enabled case. |
| 175 | return; | |
| 176 | } | |
| 177 | if ((ocaBufHandle = GetOcaBufferHandle(cmdBuffer, mosContext)) == MOS_OCA_INVALID_BUFFER_HANDLE) | |
| 178 | { | |
| 179 | // May come here for workloads not enabling UMD_OCA. | |
| 174 | 180 | return; |
| 175 | 181 | } |
| 176 | 182 | |
| 272 | 278 | MOS_OCA_BUFFER_HANDLE ocaBufHandle = 0; |
| 273 | 279 | MOS_STATUS status = MOS_STATUS_SUCCESS; |
| 274 | 280 | |
| 275 | if (nullptr == pOcaInterface || !((MosOcaInterfaceSpecific*)pOcaInterface)->IsOcaEnabled() || (ocaBufHandle = GetOcaBufferHandle(cmdBuffer, mosContext)) >= MAX_NUM_OF_OCA_BUF_CONTEXT) | |
| 276 | { | |
| 281 | if (nullptr == pOcaInterface || !((MosOcaInterfaceSpecific*)pOcaInterface)->IsOcaEnabled()) | |
| 282 | { | |
| 283 | return; | |
| 284 | } | |
| 285 | if ((ocaBufHandle = GetOcaBufferHandle(cmdBuffer, mosContext)) == MOS_OCA_INVALID_BUFFER_HANDLE) | |
| 286 | { | |
| 287 | // May come here for workloads not enabling UMD_OCA. | |
| 277 | 288 | return; |
| 278 | 289 | } |
| 279 | 290 | |
| 314 | 325 | MOS_STATUS status = MOS_STATUS_SUCCESS; |
| 315 | 326 | MOS_OCA_BUFFER_HANDLE ocaBufHandle = 0; |
| 316 | 327 | |
| 317 | if (nullptr == pOcaInterface || !((MosOcaInterfaceSpecific*)pOcaInterface)->IsOcaEnabled() || (ocaBufHandle = GetOcaBufferHandle(cmdBuffer, mosContext)) >= MAX_NUM_OF_OCA_BUF_CONTEXT) | |
| 318 | { | |
| 328 | if (nullptr == pOcaInterface || !((MosOcaInterfaceSpecific*)pOcaInterface)->IsOcaEnabled()) | |
| 329 | { | |
| 330 | return; | |
| 331 | } | |
| 332 | ||
| 333 | if ((ocaBufHandle = GetOcaBufferHandle(cmdBuffer, mosContext)) == MOS_OCA_INVALID_BUFFER_HANDLE) | |
| 334 | { | |
| 335 | // May come here for workloads not enabling UMD_OCA. | |
| 319 | 336 | return; |
| 320 | 337 | } |
| 321 | 338 | |
| 367 | 384 | MOS_OCA_BUFFER_HANDLE ocaBufHandle = 0; |
| 368 | 385 | uint32_t updateSize = 0; |
| 369 | 386 | |
| 370 | if (nullptr == pOcaInterface || !((MosOcaInterfaceSpecific*)pOcaInterface)->IsOcaEnabled() || (ocaBufHandle = GetOcaBufferHandle(cmdBuffer, mosContext)) >= MAX_NUM_OF_OCA_BUF_CONTEXT) | |
| 371 | { | |
| 387 | if (nullptr == pOcaInterface || !((MosOcaInterfaceSpecific*)pOcaInterface)->IsOcaEnabled()) | |
| 388 | { | |
| 389 | return; | |
| 390 | } | |
| 391 | ||
| 392 | if ((ocaBufHandle = GetOcaBufferHandle(cmdBuffer, mosContext)) == MOS_OCA_INVALID_BUFFER_HANDLE) | |
| 393 | { | |
| 394 | // May come here for workloads not enabling UMD_OCA. | |
| 372 | 395 | return; |
| 373 | 396 | } |
| 374 | 397 | |
| 413 | 436 | MOS_OCA_BUFFER_HANDLE ocaBufHandle = 0; |
| 414 | 437 | uint32_t updateSize = 0; |
| 415 | 438 | |
| 416 | if (nullptr == pOcaInterface || !((MosOcaInterfaceSpecific*)pOcaInterface)->IsOcaEnabled() || (ocaBufHandle = GetOcaBufferHandle(cmdBuffer, mosContext)) >= MAX_NUM_OF_OCA_BUF_CONTEXT || | |
| 439 | if (nullptr == pOcaInterface || | |
| 440 | !((MosOcaInterfaceSpecific*)pOcaInterface)->IsOcaEnabled() || | |
| 417 | 441 | nullptr == pVphalDumper) |
| 418 | 442 | { |
| 443 | return; | |
| 444 | } | |
| 445 | if ((ocaBufHandle = GetOcaBufferHandle(cmdBuffer, mosContext)) == MOS_OCA_INVALID_BUFFER_HANDLE) | |
| 446 | { | |
| 447 | // May come here for workloads not enabling UMD_OCA. | |
| 419 | 448 | return; |
| 420 | 449 | } |
| 421 | 450 | |
| 447 | 476 | |
| 448 | 477 | MOS_OCA_BUFFER_HANDLE HalOcaInterface::GetOcaBufferHandle(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext) |
| 449 | 478 | { |
| 450 | MosOcaInterface *pOcaInterface = &MosOcaInterfaceSpecific::GetInstance(); | |
| 479 | MosOcaInterface *pOcaInterface = &MosOcaInterfaceSpecific::GetInstance(); | |
| 451 | 480 | if(pOcaInterface == nullptr) |
| 452 | 481 | { |
| 453 | 482 | OnOcaError(&mosContext, MOS_STATUS_NULL_POINTER, __FUNCTION__, __LINE__); |
| 454 | return -1; | |
| 455 | } | |
| 456 | PMOS_MUTEX mutex = pOcaInterface->GetMutex(); | |
| 483 | return MOS_OCA_INVALID_BUFFER_HANDLE; | |
| 484 | } | |
| 485 | PMOS_MUTEX mutex = pOcaInterface->GetMutex(); | |
| 457 | 486 | if (mutex == nullptr) |
| 458 | 487 | { |
| 459 | OnOcaError(&mosContext, MOS_STATUS_INVALID_PARAMETER, __FUNCTION__, __LINE__); | |
| 460 | return -1; | |
| 488 | return MOS_OCA_INVALID_BUFFER_HANDLE; | |
| 461 | 489 | } |
| 462 | 490 | MosOcaAutoLock autoLock(mutex); |
| 463 | 491 | std::map<uint32_t*, MOS_OCA_BUFFER_HANDLE>::iterator it = s_hOcaMap.find(cmdBuffer.pCmdBase); |
| 464 | return it == s_hOcaMap.end() ? 0 : it->second; | |
| 492 | if (it == s_hOcaMap.end()) | |
| 493 | { | |
| 494 | // May come here for workloads not enabling UMD_OCA. | |
| 495 | return MOS_OCA_INVALID_BUFFER_HANDLE; | |
| 496 | } | |
| 497 | if (it->second >= MAX_NUM_OF_OCA_BUF_CONTEXT || it->second < 0) | |
| 498 | { | |
| 499 | OnOcaError(&mosContext, MOS_STATUS_NULL_POINTER, __FUNCTION__, __LINE__); | |
| 500 | return MOS_OCA_INVALID_BUFFER_HANDLE; | |
| 501 | } | |
| 502 | return it->second; | |
| 465 | 503 | } |
| 466 | 504 | |
| 467 | 505 | void HalOcaInterface::RemoveOcaBufferHandle(MOS_COMMAND_BUFFER &cmdBuffer, MOS_CONTEXT &mosContext) |
| 139 | 139 | { |
| 140 | 140 | if (picParam->anchor_frames_num <= MAX_ANCHOR_FRAME_NUM_AV1) |
| 141 | 141 | { |
| 142 | MOS_SecureMemcpy(anchorFrameListVA, picParam->anchor_frames_num, picParam->anchor_frames_list, picParam->anchor_frames_num); | |
| 142 | MOS_SecureMemcpy(anchorFrameListVA, picParam->anchor_frames_num * sizeof(VASurfaceID), | |
| 143 | picParam->anchor_frames_list, picParam->anchor_frames_num * sizeof(VASurfaceID)); | |
| 143 | 144 | } |
| 144 | 145 | else |
| 145 | 146 | { |
| 26 | 26 | #ifndef __RENDERHAL_G12_BASE_H__ |
| 27 | 27 | #define __RENDERHAL_G12_BASE_H__ |
| 28 | 28 | |
| 29 | #include "renderhal_platform_interface.h" | |
| 29 | #include "renderhal_platform_interface_legacy.h" | |
| 30 | 30 | #include "mhw_render_g12_X.h" |
| 31 | 31 | #include "mhw_render_hwcmd_g12_X.h" |
| 32 | 32 | #include "mhw_state_heap_hwcmd_g12_X.h" |
| 42 | 42 | //! SLM URB DC RO Rest/L3 Client Pool |
| 43 | 43 | //! 0 64 0 0 416 (KB chunks based on GT2) |
| 44 | 44 | #define RENDERHAL_L3_CACHE_CONFIG_CNTLREG_VALUE_G12LP_RENDERHAL (0xD0000020) |
| 45 | class XRenderHal_Interface_G12_Base : public XRenderHal_Platform_Interface | |
| 45 | class XRenderHal_Interface_G12_Base : public XRenderHal_Platform_Interface_Legacy | |
| 46 | 46 | { |
| 47 | 47 | public: |
| 48 | 48 | XRenderHal_Interface_G12_Base(); |
+2
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| 30 | 30 | #include "decode_filmgrain_surf_init_g12.h" |
| 31 | 31 | #include "decode_filmgrain_presubpipeline_g12.h" |
| 32 | 32 | #include "decode_filmgrain_postsubpipeline_g12.h" |
| 33 | #include "decode_huc_packet_creator_g12.h" | |
| 33 | 34 | |
| 34 | 35 | namespace decode |
| 35 | 36 | { |
| 37 | 38 | class FilmGrainPreSubPipeline; |
| 38 | 39 | class FilmGrainPostSubPipeline; |
| 39 | 40 | class Av1DecodePktG12; |
| 40 | class Av1PipelineG12 : public Av1Pipeline | |
| 41 | class Av1PipelineG12 : public Av1Pipeline, public HucPacketCreatorG12 | |
| 41 | 42 | { |
| 42 | 43 | public: |
| 43 | 44 | //! |
+2
-2
| 59 | 59 | m_filmGrainFeature = dynamic_cast<Av1DecodeFilmGrainG12 *>(featureManager->GetFeature(Av1FeatureIDs::av1SwFilmGrain)); |
| 60 | 60 | DECODE_CHK_NULL(m_filmGrainFeature); |
| 61 | 61 | |
| 62 | m_surfInitPkt = MOS_New(HucCopyPkt, m_pipeline, m_task, hwInterface); | |
| 62 | m_surfInitPkt = MOS_New(HucCopyPktG12, m_pipeline, m_task, hwInterface); | |
| 63 | 63 | DECODE_CHK_NULL(m_surfInitPkt); |
| 64 | 64 | Av1PipelineG12 *pipeline = dynamic_cast<Av1PipelineG12 *>(m_pipeline); |
| 65 | 65 | DECODE_CHK_STATUS(RegisterPacket(DecodePacketId(pipeline, hucCopyPacketId), *m_surfInitPkt)); |
| 107 | 107 | DECODE_CHK_STATUS(m_allocator->Resize(m_tmpInitBuf, allocSize, lockableVideoMem, false, true)); |
| 108 | 108 | } |
| 109 | 109 | |
| 110 | HucCopyPkt::HucCopyParams copyParams; | |
| 110 | HucCopyPktG12::HucCopyParams copyParams; | |
| 111 | 111 | copyParams.srcBuffer = &(m_tmpInitBuf->OsResource); |
| 112 | 112 | copyParams.srcOffset = 0; |
| 113 | 113 | copyParams.destBuffer = &(m_filmGrainFeature->m_coordinatesRandomValuesSurface->OsResource); |
+6
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| 30 | 30 | |
| 31 | 31 | #include "decode_av1_pipeline_g12.h" |
| 32 | 32 | #include "decode_av1_filmgrain_feature_g12.h" |
| 33 | #include "decode_huc_copy_packet_g12.h" | |
| 34 | ||
| 33 | 35 | |
| 34 | 36 | namespace decode { |
| 35 | 37 | |
| 93 | 95 | virtual void InitScalabilityPars(PMOS_INTERFACE osInterface) override; |
| 94 | 96 | |
| 95 | 97 | private: |
| 96 | Av1DecodeFilmGrainG12 *m_filmGrainFeature = nullptr; //!< Film Grain feature | |
| 97 | DecodeAllocator * m_allocator = nullptr; //!< Resource allocator | |
| 98 | HucCopyPkt * m_surfInitPkt = nullptr; //!< Surface init packet | |
| 99 | PMOS_BUFFER m_tmpInitBuf = nullptr; //!< Init buffer filled with 0 | |
| 98 | Av1DecodeFilmGrainG12 * m_filmGrainFeature = nullptr; //!< Film Grain feature | |
| 99 | DecodeAllocator * m_allocator = nullptr; //!< Resource allocator | |
| 100 | HucCopyPktG12 * m_surfInitPkt = nullptr; //!< Surface init packet | |
| 101 | PMOS_BUFFER m_tmpInitBuf = nullptr; //!< Init buffer filled with 0 | |
| 100 | 102 | }; |
| 101 | 103 | } // namespace decode |
| 102 | 104 | #endif |
| 116 | 116 | // not Finished |
| 117 | 117 | //#define VP_FF_VEBOX_FORMAT(SurfaceFormat, bInput, bOutput, _MaxResolution, _MinResolution, _HorizUnit, _VertUnit, _HdrSupported, _CapturePipeSupported, |
| 118 | 118 | // _DNSupported, _DISupported, _LACESupported, _FrontCscSupported, _BackEndCscSupported, _3DLutSupported, _IecpSupported) |
| 119 | /* Vebox HSB Mode Suppored -------------------------------------------------------------------------------------------------------------------------------o | |
| 120 | IECP Suppored ----------------------------------------------------------------------------------------------------------------------------------o | | |
| 121 | 3DLut Suppored -----------------------------------------------------------------------------------------------------------------------------o | | | |
| 122 | BackEnd CSC Suppored -------------------------------------------------------------------------------------------------------------------o | | | | |
| 123 | Front CSC Suppored -----------------------------------------------------------------------------------------------------------------o | | | | | |
| 124 | LACE Suppored ------------------------------------------------------------------------------------------------------------------o | | | | | | |
| 125 | De-interlace Suppored ------------------------------------------------------------------------------------------------------o | | | | | | | |
| 126 | Denoise Suppored -------------------------------------------------------------------------------------------------------o | | | | | | | | |
| 127 | CapPipe Suppored ---------------------------------------------------------------------------------------------------o | | | | | | | | | |
| 128 | HDR Suppored ---------------------------------------------------------------------------------------------------o | | | | | | | | | | |
| 129 | Processing Unit in Vertical --------------------------------------------------------------------------------o | | | | | | | | | | | |
| 130 | Processing Unit in Horizontal --------------------------------------------------------------------------o | | | | | | | | | | | | |
| 131 | MAX Process Resolution(Width/Height) ---------------------------------------------o | | | | | | | | | | | | | |
| 132 | MAX Process Resolution(Width/Height) ------------------o | | | | | | | | | | | | | | |
| 133 | Output Format Supported --------------------o | | | | | | | | | | | | | | | |
| 134 | Input Format Supported -----------------o | | | | | | | | | | | | | | | | |
| 135 | Format | | | | | | | | | | | | | | | | | |
| 136 | --------------------------------------------------------------------------------------------------------------------------------------------------------*/ | |
| 137 | VP_FF_VEBOX_FORMAT(Format_NV12, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 2, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 138 | VP_FF_VEBOX_FORMAT(Format_P010, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 2, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 139 | VP_FF_VEBOX_FORMAT(Format_P016, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 2, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 140 | VP_FF_VEBOX_FORMAT(Format_YUY2, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 141 | VP_FF_VEBOX_FORMAT(Format_YUYV, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 142 | VP_FF_VEBOX_FORMAT(Format_UYVY, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 143 | VP_FF_VEBOX_FORMAT(Format_Y216, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 144 | VP_FF_VEBOX_FORMAT(Format_Y210, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 145 | VP_FF_VEBOX_FORMAT(Format_P216, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 146 | VP_FF_VEBOX_FORMAT(Format_P210, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 147 | VP_FF_VEBOX_FORMAT(Format_AYUV, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 148 | VP_FF_VEBOX_FORMAT(Format_Y416, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 149 | VP_FF_VEBOX_FORMAT(Format_Y410, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 150 | VP_FF_VEBOX_FORMAT(Format_YVYU, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 151 | VP_FF_VEBOX_FORMAT(Format_VYUY, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 119 | /* Vebox TCC Suppored ----------------------------------------------------------------------------------------------------------------------------------------o | |
| 120 | HSB Mode Suppored -------------------------------------------------- -----------------------------------------------------------------------------o | | |
| 121 | IECP Suppored ----------------------------------------------------------------------------------------------------------------------------------o | | | |
| 122 | 3DLut Suppored -----------------------------------------------------------------------------------------------------------------------------o | | | | |
| 123 | BackEnd CSC Suppored -------------------------------------------------------------------------------------------------------------------o | | | | | |
| 124 | Front CSC Suppored -----------------------------------------------------------------------------------------------------------------o | | | | | | |
| 125 | LACE Suppored ------------------------------------------------------------------------------------------------------------------o | | | | | | | |
| 126 | De-interlace Suppored ------------------------------------------------------------------------------------------------------o | | | | | | | | |
| 127 | Denoise Suppored -------------------------------------------------------------------------------------------------------o | | | | | | | | | |
| 128 | CapPipe Suppored ---------------------------------------------------------------------------------------------------o | | | | | | | | | | |
| 129 | HDR Suppored ---------------------------------------------------------------------------------------------------o | | | | | | | | | | | |
| 130 | Processing Unit in Vertical --------------------------------------------------------------------------------o | | | | | | | | | | | | |
| 131 | Processing Unit in Horizontal --------------------------------------------------------------------------o | | | | | | | | | | | | | |
| 132 | MAX Process Resolution(Width/Height) ---------------------------------------------o | | | | | | | | | | | | | | |
| 133 | MAX Process Resolution(Width/Height) ------------------o | | | | | | | | | | | | | | | |
| 134 | Output Format Supported --------------------o | | | | | | | | | | | | | | | | |
| 135 | Input Format Supported -----------------o | | | | | | | | | | | | | | | | | |
| 136 | Format | | | | | | | | | | | | | | | | | | |
| 137 | ---------------------------------------------------------------------------------------------------------------------------------------------------------------*/ | |
| 138 | VP_FF_VEBOX_FORMAT(Format_NV12, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 2, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 139 | VP_FF_VEBOX_FORMAT(Format_P010, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 2, 1, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 140 | VP_FF_VEBOX_FORMAT(Format_P016, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 2, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 141 | VP_FF_VEBOX_FORMAT(Format_YUY2, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 142 | VP_FF_VEBOX_FORMAT(Format_YUYV, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 143 | VP_FF_VEBOX_FORMAT(Format_UYVY, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 144 | VP_FF_VEBOX_FORMAT(Format_Y216, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 145 | VP_FF_VEBOX_FORMAT(Format_Y210, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 146 | VP_FF_VEBOX_FORMAT(Format_P216, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0) | |
| 147 | VP_FF_VEBOX_FORMAT(Format_P210, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0) | |
| 148 | VP_FF_VEBOX_FORMAT(Format_AYUV, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 149 | VP_FF_VEBOX_FORMAT(Format_Y416, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 150 | VP_FF_VEBOX_FORMAT(Format_Y410, 1, 1, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 151 | VP_FF_VEBOX_FORMAT(Format_YVYU, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 152 | VP_FF_VEBOX_FORMAT(Format_VYUY, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 2, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 152 | 153 | |
| 153 | 154 | // Block ARGB output from Vebox as quality issue |
| 154 | VP_FF_VEBOX_FORMAT(Format_A8B8G8R8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1) | |
| 155 | VP_FF_VEBOX_FORMAT(Format_X8B8G8R8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1) | |
| 156 | VP_FF_VEBOX_FORMAT(Format_A8R8G8B8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1) | |
| 157 | VP_FF_VEBOX_FORMAT(Format_X8R8G8B8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1) | |
| 158 | VP_FF_VEBOX_FORMAT(Format_A16B16G16R16, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1) | |
| 159 | VP_FF_VEBOX_FORMAT(Format_A16R16G16B16, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1) | |
| 160 | VP_FF_VEBOX_FORMAT(Format_A16B16G16R16F, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1) | |
| 161 | VP_FF_VEBOX_FORMAT(Format_A16R16G16B16F, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1) | |
| 162 | VP_FF_VEBOX_FORMAT(Format_L8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1) | |
| 163 | VP_FF_VEBOX_FORMAT(Format_P8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1) | |
| 164 | VP_FF_VEBOX_FORMAT(Format_Y8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 165 | VP_FF_VEBOX_FORMAT(Format_Y16S, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1) | |
| 166 | VP_FF_VEBOX_FORMAT(Format_Y16U, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1) | |
| 167 | VP_FF_VEBOX_FORMAT(Format_R10G10B10A2, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1) | |
| 168 | VP_FF_VEBOX_FORMAT(Format_B10G10R10A2, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1) | |
| 169 | VP_FF_VEBOX_FORMAT(Format_R5G6B5, 0, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) | |
| 155 | VP_FF_VEBOX_FORMAT(Format_A8B8G8R8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 156 | VP_FF_VEBOX_FORMAT(Format_X8B8G8R8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 157 | VP_FF_VEBOX_FORMAT(Format_A8R8G8B8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 158 | VP_FF_VEBOX_FORMAT(Format_X8R8G8B8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 159 | VP_FF_VEBOX_FORMAT(Format_A16B16G16R16, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 1, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 160 | VP_FF_VEBOX_FORMAT(Format_A16R16G16B16, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 161 | VP_FF_VEBOX_FORMAT(Format_A16B16G16R16F, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 162 | VP_FF_VEBOX_FORMAT(Format_A16R16G16B16F, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 163 | VP_FF_VEBOX_FORMAT(Format_L8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 164 | VP_FF_VEBOX_FORMAT(Format_P8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 165 | VP_FF_VEBOX_FORMAT(Format_Y8, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 166 | VP_FF_VEBOX_FORMAT(Format_Y16S, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1) | |
| 167 | VP_FF_VEBOX_FORMAT(Format_Y16U, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 1) | |
| 168 | VP_FF_VEBOX_FORMAT(Format_R10G10B10A2, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 169 | VP_FF_VEBOX_FORMAT(Format_B10G10R10A2, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 0) | |
| 170 | VP_FF_VEBOX_FORMAT(Format_R5G6B5, 0, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) | |
| 170 | 171 | |
| 171 | VP_FF_VEBOX_FORMAT(Format_IRW0, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1) | |
| 172 | VP_FF_VEBOX_FORMAT(Format_IRW1, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1) | |
| 173 | VP_FF_VEBOX_FORMAT(Format_IRW2, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1) | |
| 174 | VP_FF_VEBOX_FORMAT(Format_IRW3, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1) | |
| 175 | VP_FF_VEBOX_FORMAT(Format_IRW4, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1) | |
| 176 | VP_FF_VEBOX_FORMAT(Format_IRW5, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1) | |
| 177 | VP_FF_VEBOX_FORMAT(Format_IRW6, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1) | |
| 178 | VP_FF_VEBOX_FORMAT(Format_IRW7, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1) | |
| 172 | VP_FF_VEBOX_FORMAT(Format_IRW0, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0) | |
| 173 | VP_FF_VEBOX_FORMAT(Format_IRW1, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0) | |
| 174 | VP_FF_VEBOX_FORMAT(Format_IRW2, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0) | |
| 175 | VP_FF_VEBOX_FORMAT(Format_IRW3, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0) | |
| 176 | VP_FF_VEBOX_FORMAT(Format_IRW4, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0) | |
| 177 | VP_FF_VEBOX_FORMAT(Format_IRW5, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0) | |
| 178 | VP_FF_VEBOX_FORMAT(Format_IRW6, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0) | |
| 179 | VP_FF_VEBOX_FORMAT(Format_IRW7, 1, 0, MHW_VEBOX_MAX_RESOLUTION_G12, MHW_VEBOX_MIN_RESOLUTION_G12, 1, 1, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 0) | |
| 179 | 180 | |
| 180 | 181 | #endif //__VP_FEATURE_CAPS__G12_H__⏎ |
+43
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| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file decode_huc_copy_creator_itf.h | |
| 23 | //! \brief Defines the implementation of huc copy creator | |
| 24 | //! | |
| 25 | ||
| 26 | #include "decode_huc_packet_creator_g12.h" | |
| 27 | #include "decode_huc_copy_packet_g12.h" | |
| 28 | ||
| 29 | namespace decode | |
| 30 | { | |
| 31 | HucCopyPktItf *HucPacketCreatorG12::CreateHucCopyPkt(MediaPipeline *pipeline, MediaTask *task, CodechalHwInterface *hwInterface) | |
| 32 | { | |
| 33 | HucCopyPktItf *copyPkt = MOS_New(HucCopyPktG12, pipeline, task, hwInterface); | |
| 34 | return copyPkt; | |
| 35 | } | |
| 36 | ||
| 37 | CmdPacket *HucPacketCreatorG12::CreateProbUpdatePkt(MediaPipeline *pipeline, MediaTask *task, CodechalHwInterface *hwInterface) | |
| 38 | { | |
| 39 | return nullptr; | |
| 40 | } | |
| 41 | ||
| 42 | } // namespace decode |
+49
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| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file decode_huc_packet_creator_g12.h | |
| 23 | //! | |
| 24 | ||
| 25 | #ifndef __CODECHAL_HUC_PACKET_CREATOR_G12_H__ | |
| 26 | #define __CODECHAL_HUC_PACKET_CREATOR_G12_H__ | |
| 27 | ||
| 28 | #include "decode_huc_packet_creator_base.h" | |
| 29 | ||
| 30 | ||
| 31 | namespace decode | |
| 32 | { | |
| 33 | class HucPacketCreatorG12 : public HucPacketCreatorBase | |
| 34 | { | |
| 35 | public: | |
| 36 | ||
| 37 | HucPacketCreatorG12() | |
| 38 | { | |
| 39 | } | |
| 40 | ||
| 41 | virtual ~HucPacketCreatorG12() {} | |
| 42 | ||
| 43 | virtual HucCopyPktItf *CreateHucCopyPkt(MediaPipeline *pipeline, MediaTask *task, CodechalHwInterface *hwInterface) override; | |
| 44 | virtual CmdPacket * CreateProbUpdatePkt(MediaPipeline *pipeline, MediaTask *task, CodechalHwInterface *hwInterface) override; | |
| 45 | }; | |
| 46 | ||
| 47 | } // namespace decode | |
| 48 | #endif⏎ |
+30
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| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | set(TMP_SOURCES_ | |
| 20 | ${TMP_SOURCES_} | |
| 21 | ${CMAKE_CURRENT_LIST_DIR}/decode_huc_packet_creator_g12.cpp | |
| 22 | ) | |
| 23 | ||
| 24 | set(TMP_HEADERS_ | |
| 25 | ${TMP_HEADERS_} | |
| 26 | ${CMAKE_CURRENT_LIST_DIR}/decode_huc_packet_creator_g12.h | |
| 27 | ) | |
| 28 | ||
| 29 | media_add_curr_to_include_path() |
+1
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| 18 | 18 | # OTHER DEALINGS IN THE SOFTWARE. |
| 19 | 19 | |
| 20 | 20 | media_include_subdirectory(packet) |
| 21 | media_include_subdirectory(hucitf) |
+240
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| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file decode_huc_copy_packet_g12.cpp | |
| 23 | //! \brief Defines the interface for huc copy packet | |
| 24 | //! | |
| 25 | #include "decode_huc_copy_packet_g12.h" | |
| 26 | #include "mhw_vdbox.h" | |
| 27 | #include "decode_pipeline.h" | |
| 28 | ||
| 29 | namespace decode | |
| 30 | { | |
| 31 | ||
| 32 | MOS_STATUS HucCopyPktG12::PushCopyParams(HucCopyParams ©Params) | |
| 33 | { | |
| 34 | m_copyParamsList.push_back(copyParams); | |
| 35 | return MOS_STATUS_SUCCESS; | |
| 36 | } | |
| 37 | ||
| 38 | MOS_STATUS HucCopyPktG12::Submit(MOS_COMMAND_BUFFER *commandBuffer, uint8_t packetPhase) | |
| 39 | { | |
| 40 | DECODE_FUNC_CALL(); | |
| 41 | DECODE_CHK_NULL(commandBuffer); | |
| 42 | ||
| 43 | bool firstTaskInPhase = packetPhase & firstPacket; | |
| 44 | bool requestProlog = false; | |
| 45 | ||
| 46 | if ((!m_pipeline->IsSingleTaskPhaseSupported() || firstTaskInPhase) && (m_pipeline->GetPipeNum() == 1)) | |
| 47 | { | |
| 48 | // Send command buffer header at the beginning (OS dependent) | |
| 49 | requestProlog = true; | |
| 50 | } | |
| 51 | DECODE_CHK_STATUS(Execute(*commandBuffer, requestProlog)); | |
| 52 | ||
| 53 | return MOS_STATUS_SUCCESS; | |
| 54 | } | |
| 55 | ||
| 56 | MOS_STATUS HucCopyPktG12::Execute(MOS_COMMAND_BUFFER &cmdBuffer, bool prologNeeded) | |
| 57 | { | |
| 58 | DECODE_FUNC_CALL(); | |
| 59 | DECODE_CHK_NULL(m_hucInterface); | |
| 60 | ||
| 61 | SetPerfTag(); | |
| 62 | ||
| 63 | for (m_copyParamsIdx = 0; m_copyParamsIdx < m_copyParamsList.size(); m_copyParamsIdx++) | |
| 64 | { | |
| 65 | if (prologNeeded && (m_copyParamsIdx == 0)) | |
| 66 | { | |
| 67 | DECODE_CHK_STATUS(SendPrologCmds(cmdBuffer)); | |
| 68 | } | |
| 69 | ||
| 70 | DECODE_CHK_STATUS(AddHucPipeModeSelect(cmdBuffer)); | |
| 71 | DECODE_CHK_STATUS(AddHucIndObj(cmdBuffer)); | |
| 72 | CODEC_HEVC_SLICE_PARAMS unused; | |
| 73 | DECODE_CHK_STATUS(AddHucStreamObject(cmdBuffer, unused)); | |
| 74 | ||
| 75 | // Flush the engine to ensure memory written out | |
| 76 | DECODE_CHK_STATUS(MemoryFlush(cmdBuffer)); | |
| 77 | ||
| 78 | DECODE_CHK_STATUS(m_allocator->SyncOnResource(m_copyParamsList[m_copyParamsIdx].srcBuffer, false)); | |
| 79 | DECODE_CHK_STATUS(m_allocator->SyncOnResource(m_copyParamsList[m_copyParamsIdx].destBuffer, true)); | |
| 80 | } | |
| 81 | ||
| 82 | // clear copy params since it is consumed | |
| 83 | m_copyParamsList.clear(); | |
| 84 | ||
| 85 | return MOS_STATUS_SUCCESS; | |
| 86 | } | |
| 87 | ||
| 88 | void HucCopyPktG12::SetImemParameters(MHW_VDBOX_HUC_IMEM_STATE_PARAMS &imemParams) | |
| 89 | { | |
| 90 | DECODE_FUNC_CALL(); | |
| 91 | } | |
| 92 | ||
| 93 | MOS_STATUS HucCopyPktG12::AddHucImem(MOS_COMMAND_BUFFER &cmdBuffer) | |
| 94 | { | |
| 95 | DECODE_FUNC_CALL(); | |
| 96 | return MOS_STATUS_SUCCESS; | |
| 97 | } | |
| 98 | ||
| 99 | void HucCopyPktG12::SetHucPipeModeSelectParameters(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS &pipeModeSelectParams) | |
| 100 | { | |
| 101 | DECODE_FUNC_CALL(); | |
| 102 | pipeModeSelectParams.Mode = m_basicFeature->m_mode; | |
| 103 | pipeModeSelectParams.dwMediaSoftResetCounterValue = 2400; | |
| 104 | pipeModeSelectParams.bStreamObjectUsed = true; | |
| 105 | pipeModeSelectParams.bStreamOutEnabled = true; | |
| 106 | pipeModeSelectParams.disableProtectionSetting = true; | |
| 107 | } | |
| 108 | ||
| 109 | MOS_STATUS HucCopyPktG12::AddHucPipeModeSelect(MOS_COMMAND_BUFFER &cmdBuffer) | |
| 110 | { | |
| 111 | MHW_VDBOX_PIPE_MODE_SELECT_PARAMS pipeModeSelectParams; | |
| 112 | SetHucPipeModeSelectParameters(pipeModeSelectParams); | |
| 113 | DECODE_CHK_STATUS(m_hucInterface->AddHucPipeModeSelectCmd(&cmdBuffer, &pipeModeSelectParams)); | |
| 114 | return MOS_STATUS_SUCCESS; | |
| 115 | } | |
| 116 | ||
| 117 | void HucCopyPktG12::SetDmemParameters(MHW_VDBOX_HUC_DMEM_STATE_PARAMS &dmemParams) | |
| 118 | { | |
| 119 | DECODE_FUNC_CALL(); | |
| 120 | } | |
| 121 | ||
| 122 | MOS_STATUS HucCopyPktG12::AddHucDmem(MOS_COMMAND_BUFFER &cmdBuffer) | |
| 123 | { | |
| 124 | DECODE_FUNC_CALL(); | |
| 125 | return MOS_STATUS_SUCCESS; | |
| 126 | } | |
| 127 | ||
| 128 | void HucCopyPktG12::SetRegionParameters(MHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS &virtualAddrParams) | |
| 129 | { | |
| 130 | DECODE_FUNC_CALL(); | |
| 131 | } | |
| 132 | ||
| 133 | MOS_STATUS HucCopyPktG12::AddHucRegion(MOS_COMMAND_BUFFER &cmdBuffer) | |
| 134 | { | |
| 135 | DECODE_FUNC_CALL(); | |
| 136 | return MOS_STATUS_SUCCESS; | |
| 137 | } | |
| 138 | ||
| 139 | void HucCopyPktG12::SetIndObjParameters(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS &indObjParams) | |
| 140 | { | |
| 141 | DECODE_FUNC_CALL(); | |
| 142 | ||
| 143 | HucCopyParams& copyParams = m_copyParamsList.at(m_copyParamsIdx); | |
| 144 | ||
| 145 | uint32_t dataSize = copyParams.srcOffset + copyParams.copyLength; | |
| 146 | uint32_t dataOffset = MOS_ALIGN_FLOOR(copyParams.srcOffset, MHW_PAGE_SIZE); | |
| 147 | uint32_t inputRelativeOffset = copyParams.srcOffset - dataOffset; | |
| 148 | ||
| 149 | uint32_t destSize = copyParams.destOffset + copyParams.copyLength; | |
| 150 | uint32_t destOffset = MOS_ALIGN_FLOOR(copyParams.destOffset, MHW_PAGE_SIZE); | |
| 151 | uint32_t outputRelativeOffset = copyParams.destOffset - destOffset; | |
| 152 | ||
| 153 | // Enlarge the stream in/out data size to avoid upper bound hit assert in HuC | |
| 154 | dataSize += inputRelativeOffset; | |
| 155 | destSize += outputRelativeOffset; | |
| 156 | ||
| 157 | // pass bit-stream buffer by Ind Obj Addr command | |
| 158 | indObjParams.presDataBuffer = copyParams.srcBuffer; | |
| 159 | indObjParams.dwDataSize = MOS_ALIGN_CEIL(dataSize, MHW_PAGE_SIZE); | |
| 160 | indObjParams.dwDataOffset = dataOffset; | |
| 161 | indObjParams.presStreamOutObjectBuffer = copyParams.destBuffer; | |
| 162 | indObjParams.dwStreamOutObjectSize = MOS_ALIGN_CEIL(destSize, MHW_PAGE_SIZE); | |
| 163 | indObjParams.dwStreamOutObjectOffset = destOffset; | |
| 164 | } | |
| 165 | ||
| 166 | MOS_STATUS HucCopyPktG12::AddHucIndObj(MOS_COMMAND_BUFFER &cmdBuffer) | |
| 167 | { | |
| 168 | DECODE_FUNC_CALL(); | |
| 169 | MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS indObjParams; | |
| 170 | MOS_ZeroMemory(&indObjParams, sizeof(indObjParams)); | |
| 171 | SetIndObjParameters(indObjParams); | |
| 172 | DECODE_CHK_STATUS(m_hucInterface->AddHucIndObjBaseAddrStateCmd(&cmdBuffer, &indObjParams)); | |
| 173 | return MOS_STATUS_SUCCESS; | |
| 174 | } | |
| 175 | ||
| 176 | void HucCopyPktG12::SetStreamObjectParameters(MHW_VDBOX_HUC_STREAM_OBJ_PARAMS &streamObjParams, | |
| 177 | CODEC_HEVC_SLICE_PARAMS &sliceParams) | |
| 178 | { | |
| 179 | DECODE_FUNC_CALL(); | |
| 180 | ||
| 181 | HucCopyParams& copyParams = m_copyParamsList.at(m_copyParamsIdx); | |
| 182 | ||
| 183 | uint32_t dataOffset = MOS_ALIGN_FLOOR(copyParams.srcOffset, MHW_PAGE_SIZE); | |
| 184 | uint32_t inputRelativeOffset = copyParams.srcOffset - dataOffset; | |
| 185 | ||
| 186 | uint32_t destOffset = MOS_ALIGN_FLOOR(copyParams.destOffset, MHW_PAGE_SIZE); | |
| 187 | uint32_t outputRelativeOffset = copyParams.destOffset - destOffset; | |
| 188 | ||
| 189 | // set stream object with stream out enabled | |
| 190 | streamObjParams.dwIndStreamInLength = copyParams.copyLength; | |
| 191 | streamObjParams.dwIndStreamInStartAddrOffset = inputRelativeOffset; | |
| 192 | streamObjParams.dwIndStreamOutStartAddrOffset = outputRelativeOffset; | |
| 193 | streamObjParams.bHucProcessing = true; | |
| 194 | streamObjParams.bStreamInEnable = true; | |
| 195 | streamObjParams.bStreamOutEnable = true; | |
| 196 | } | |
| 197 | ||
| 198 | MOS_STATUS HucCopyPktG12::AddHucStreamObject(MOS_COMMAND_BUFFER &cmdBuffer, CODEC_HEVC_SLICE_PARAMS &sliceParams) | |
| 199 | { | |
| 200 | DECODE_FUNC_CALL(); | |
| 201 | MHW_VDBOX_HUC_STREAM_OBJ_PARAMS streamObjParams; | |
| 202 | MOS_ZeroMemory(&streamObjParams, sizeof(streamObjParams)); | |
| 203 | SetStreamObjectParameters(streamObjParams, sliceParams); | |
| 204 | DECODE_CHK_STATUS(m_hucInterface->AddHucStreamObjectCmd(&cmdBuffer, &streamObjParams)); | |
| 205 | return MOS_STATUS_SUCCESS; | |
| 206 | } | |
| 207 | ||
| 208 | void HucCopyPktG12::SetPerfTag() | |
| 209 | { | |
| 210 | DECODE_FUNC_CALL(); | |
| 211 | ||
| 212 | uint16_t perfTag = ((m_basicFeature->m_mode << 4) & 0xF0) | COPY_TYPE; | |
| 213 | m_osInterface->pfnSetPerfTag(m_osInterface, perfTag); | |
| 214 | } | |
| 215 | ||
| 216 | MOS_STATUS HucCopyPktG12::CalculateCommandSize(uint32_t &commandBufferSize, uint32_t &requestedPatchListSize) | |
| 217 | { | |
| 218 | DECODE_FUNC_CALL(); | |
| 219 | ||
| 220 | uint32_t hucCommandsSize = 0; | |
| 221 | uint32_t hucPatchListSize = 0; | |
| 222 | MHW_VDBOX_STATE_CMDSIZE_PARAMS stateCmdSizeParams; | |
| 223 | ||
| 224 | if (m_hwInterface) | |
| 225 | { | |
| 226 | DECODE_CHK_STATUS(m_hwInterface->GetHucStateCommandSize( | |
| 227 | m_basicFeature->m_mode, (uint32_t*)&hucCommandsSize, (uint32_t*)&hucPatchListSize, &stateCmdSizeParams)); | |
| 228 | } | |
| 229 | ||
| 230 | commandBufferSize = hucCommandsSize; | |
| 231 | requestedPatchListSize = m_osInterface->bUsesPatchList ? hucPatchListSize : 0; | |
| 232 | ||
| 233 | // 4K align since allocation is in chunks of 4K bytes. | |
| 234 | commandBufferSize = MOS_ALIGN_CEIL(commandBufferSize, 0x1000); | |
| 235 | ||
| 236 | return MOS_STATUS_SUCCESS; | |
| 237 | } | |
| 238 | ||
| 239 | } |
+107
-0
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file decode_huc_copy_packet_g12.h | |
| 23 | //! \brief Defines the implementation of huc copy packet | |
| 24 | //! | |
| 25 | ||
| 26 | #ifndef __CODECHAL_HUC_COPY_PACKET_G12_H__ | |
| 27 | #define __CODECHAL_HUC_COPY_PACKET_G12_H__ | |
| 28 | ||
| 29 | #include "media_cmd_packet.h" | |
| 30 | #include "decode_huc_g12_base.h" | |
| 31 | #include "media_pipeline.h" | |
| 32 | #include "codechal_hw.h" | |
| 33 | #include "decode_utils.h" | |
| 34 | #include "decode_huc_copy_packet_itf.h" | |
| 35 | ||
| 36 | namespace decode | |
| 37 | { | |
| 38 | class HucCopyPktG12 : public DecodeHucBasic_G12_Base, public HucCopyPktItf | |
| 39 | { | |
| 40 | public: | |
| 41 | ||
| 42 | HucCopyPktG12(MediaPipeline *pipeline, MediaTask *task, CodechalHwInterface *hwInterface) | |
| 43 | : DecodeHucBasic_G12_Base(pipeline, task, hwInterface) | |
| 44 | { | |
| 45 | } | |
| 46 | ||
| 47 | virtual ~HucCopyPktG12() { m_copyParamsList.clear(); } | |
| 48 | ||
| 49 | virtual MOS_STATUS PushCopyParams(HucCopyParams ©Params) override; | |
| 50 | ||
| 51 | MOS_STATUS Submit(MOS_COMMAND_BUFFER *commandBuffer, uint8_t packetPhase = otherPacket) override; | |
| 52 | ||
| 53 | //! | |
| 54 | //! \brief Calculate Command Size | |
| 55 | //! | |
| 56 | //! \param [in, out] commandBufferSize | |
| 57 | //! requested size | |
| 58 | //! \param [in, out] requestedPatchListSize | |
| 59 | //! requested size | |
| 60 | //! \return MOS_STATUS | |
| 61 | //! status | |
| 62 | //! | |
| 63 | virtual MOS_STATUS CalculateCommandSize( | |
| 64 | uint32_t &commandBufferSize, | |
| 65 | uint32_t &requestedPatchListSize) override; | |
| 66 | ||
| 67 | //! | |
| 68 | //! \brief Get Packet Name | |
| 69 | //! \return std::string | |
| 70 | //! | |
| 71 | virtual std::string GetPacketName() override | |
| 72 | { | |
| 73 | return "HUC_COPY"; | |
| 74 | } | |
| 75 | ||
| 76 | protected: | |
| 77 | virtual MOS_STATUS Execute(MOS_COMMAND_BUFFER& cmdBuffer, bool prologNeeded) override; | |
| 78 | ||
| 79 | virtual void SetImemParameters(MHW_VDBOX_HUC_IMEM_STATE_PARAMS &imemParams) override; | |
| 80 | virtual MOS_STATUS AddHucImem(MOS_COMMAND_BUFFER &cmdBuffer) override; | |
| 81 | ||
| 82 | virtual void SetHucPipeModeSelectParameters(MHW_VDBOX_PIPE_MODE_SELECT_PARAMS &pipeModeSelectParams) override; | |
| 83 | virtual MOS_STATUS AddHucPipeModeSelect(MOS_COMMAND_BUFFER &cmdBuffer) override; | |
| 84 | ||
| 85 | virtual void SetDmemParameters(MHW_VDBOX_HUC_DMEM_STATE_PARAMS &dmemParams) override; | |
| 86 | virtual MOS_STATUS AddHucDmem(MOS_COMMAND_BUFFER &cmdBuffer) override; | |
| 87 | ||
| 88 | virtual void SetRegionParameters(MHW_VDBOX_HUC_VIRTUAL_ADDR_PARAMS &virtualAddrParams) override; | |
| 89 | virtual MOS_STATUS AddHucRegion(MOS_COMMAND_BUFFER &cmdBuffer) override; | |
| 90 | ||
| 91 | virtual void SetIndObjParameters(MHW_VDBOX_IND_OBJ_BASE_ADDR_PARAMS &indObjParams) override; | |
| 92 | virtual MOS_STATUS AddHucIndObj(MOS_COMMAND_BUFFER &cmdBuffer) override; | |
| 93 | ||
| 94 | virtual void SetStreamObjectParameters(MHW_VDBOX_HUC_STREAM_OBJ_PARAMS &streamObjParams, | |
| 95 | CODEC_HEVC_SLICE_PARAMS &sliceParams) override; | |
| 96 | virtual MOS_STATUS AddHucStreamObject(MOS_COMMAND_BUFFER &cmdBuffer, | |
| 97 | CODEC_HEVC_SLICE_PARAMS &sliceParams) override; | |
| 98 | ||
| 99 | void SetPerfTag(); | |
| 100 | ||
| 101 | std::vector<HucCopyParams> m_copyParamsList; //!< Copy parameters list | |
| 102 | uint32_t m_copyParamsIdx = 0; //!< Copy parameters index | |
| 103 | }; | |
| 104 | ||
| 105 | } // namespace decode | |
| 106 | #endif |
+2
-0
| 19 | 19 | set(TMP_SOURCES_ |
| 20 | 20 | ${TMP_SOURCES_} |
| 21 | 21 | ${CMAKE_CURRENT_LIST_DIR}/decode_huc_g12_base.cpp |
| 22 | ${CMAKE_CURRENT_LIST_DIR}/decode_huc_copy_packet_g12.cpp | |
| 22 | 23 | ) |
| 23 | 24 | |
| 24 | 25 | set(TMP_HEADERS_ |
| 25 | 26 | ${TMP_HEADERS_} |
| 26 | 27 | ${CMAKE_CURRENT_LIST_DIR}/decode_huc_g12_base.h |
| 28 | ${CMAKE_CURRENT_LIST_DIR}/decode_huc_copy_packet_g12.h | |
| 27 | 29 | ) |
| 28 | 30 | |
| 29 | 31 | media_add_curr_to_include_path() |
| 69 | 69 | media_include_subdirectory(../media_softlet/linux) |
| 70 | 70 | |
| 71 | 71 | include(${MEDIA_EXT}/media_srcs_ext.cmake OPTIONAL) |
| 72 | include(${MEDIA_COMMON_EXT}/media_srcs_ext.cmake OPTIONAL) | |
| 72 | 73 | include(${MEDIA_SOFTLET_EXT}/media_srcs_ext.cmake OPTIONAL) |
| 73 | 74 | |
| 74 | 75 | include(${MEDIA_DRIVER_CMAKE}/media_include_paths.cmake) |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | ||
| 21 | cmake_minimum_required(VERSION 3.5) | |
| 22 | ||
| 23 | if(NOT DEFINED BS_USE_OSDM_BUILD_SYSTEM) | |
| 24 | if(DEFINED ENV{BS_USE_OSDM_BUILD_SYSTEM}) | |
| 25 | set(BS_USE_OSDM_BUILD_SYSTEM "$ENV{BS_USE_OSDM_BUILD_SYSTEM}") | |
| 26 | else() | |
| 27 | set(BS_USE_OSDM_BUILD_SYSTEM FALSE) | |
| 28 | endif() | |
| 29 | endif() | |
| 30 | ||
| 31 | # begin -- label bldsys file prologue | |
| 32 | # WARNING: The "project" statement triggers reading of CMAKE_TOOLCHAIN_FILE | |
| 33 | # and so must precede the inclusion below of bs_init.cmake . | |
| 34 | function(bs_find_build_system gfx_dev_dir build_sys_dir build_sys_inc) | |
| 35 | # If we are not building as a standalone project | |
| 36 | if(DEFINED GFX_DEVELOPMENT_DIR) | |
| 37 | set(_bs_gfx_development_dir "${GFX_DEVELOPMENT_DIR}") | |
| 38 | elseif(DEFINED ENV{GFX_DEVELOPMENT_DIR}) | |
| 39 | set(_bs_gfx_development_dir "$ENV{GFX_DEVELOPMENT_DIR}") | |
| 40 | else() | |
| 41 | get_filename_component(_bs_cur_cmake_dir "${CMAKE_CURRENT_LIST_FILE}" PATH) | |
| 42 | get_filename_component(_bs_parent_dir "${_bs_cur_cmake_dir}" DIRECTORY) | |
| 43 | set(_bs_gfx_dir_found false) | |
| 44 | while(NOT _bs_gfx_dir_found) | |
| 45 | set(_bs_bldsys_dir "${_bs_parent_dir}/Tools/bldsys") | |
| 46 | if(EXISTS ${_bs_bldsys_dir}) | |
| 47 | set(_bs_gfx_development_dir ${_bs_parent_dir}) | |
| 48 | set(_bs_gfx_dir_found true) | |
| 49 | break() | |
| 50 | endif() | |
| 51 | get_filename_component(_bs_parent_dir "${_bs_parent_dir}" DIRECTORY) | |
| 52 | if(${_bs_parent_dir} STREQUAL "/") | |
| 53 | break() | |
| 54 | endif() | |
| 55 | endwhile(NOT _bs_gfx_dir_found) | |
| 56 | if (NOT _bs_gfx_development_dir) | |
| 57 | message(FATAL_ERROR "GFX_DEVELOPMENT_DIR not found (${_bs_gfx_development_dir}) - exiting!") | |
| 58 | exit(1) | |
| 59 | endif() | |
| 60 | endif() | |
| 61 | set(${gfx_dev_dir} "${_bs_gfx_development_dir}" PARENT_SCOPE) | |
| 62 | set(${build_sys_dir} "${_bs_gfx_development_dir}/Tools/bldsys" PARENT_SCOPE) | |
| 63 | set(${build_sys_inc} "${_bs_gfx_development_dir}/Tools/bldsys/include" PARENT_SCOPE) | |
| 64 | endfunction(bs_find_build_system) | |
| 65 | ||
| 66 | bs_find_build_system(GFX_DEVELOPMENT_DIR BUILD_SYS_DIR BUILD_SYS_INC) | |
| 67 | ||
| 68 | include(${BUILD_SYS_DIR}/bs_init.cmake) | |
| 69 | # end -- label bldsys file prologue | |
| 70 | ||
| 71 | if(NOT BUILD_KERNELS) | |
| 72 | # We regenerate shaders (kernels) and store them in-source. | |
| 73 | set(CMAKE_DISABLE_SOURCE_CHANGES ON) | |
| 74 | endif() | |
| 75 | set(CMAKE_DISABLE_IN_SOURCE_BUILD ON) | |
| 76 | ||
| 77 | if ("${BUILD_TYPE}" STREQUAL "release") | |
| 78 | set(CMAKE_BUILD_TYPE "Release") | |
| 79 | elseif ("${BUILD_TYPE}" STREQUAL "release-internal") | |
| 80 | set(CMAKE_BUILD_TYPE "ReleaseInternal") | |
| 81 | elseif ("${BUILD_TYPE}" STREQUAL "debug") | |
| 82 | set(CMAKE_BUILD_TYPE "Debug") | |
| 83 | endif() | |
| 84 | ||
| 85 | include(media_pre_top_cmake.cmake OPTIONAL) | |
| 86 | ||
| 87 | include(${BS_DIR_MEDIA}/media_softlet/cmake/media_defs.cmake) | |
| 88 | ||
| 89 | include(${MEDIA_SOFTLET_CMAKE}/media_utils.cmake) | |
| 90 | ||
| 91 | find_file(EXT_CONF NAMES media_top_cmake_ext.cmake PATHS ${CMAKE_CURRENT_LIST_DIR}) | |
| 92 | ||
| 93 | if(EXT_CONF) | |
| 94 | include(${CMAKE_CURRENT_LIST_DIR}/media_top_cmake_ext.cmake) | |
| 95 | else() | |
| 96 | include(${CMAKE_CURRENT_LIST_DIR}/media_top_cmake.cmake) | |
| 97 | endif() |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codechal_common.cpp | |
| 23 | //! \brief Impelements the public interface for CodecHal. | |
| 24 | //! \details | |
| 25 | //! | |
| 26 | ||
| 27 | #include "codechal_common.h" | |
| 28 | #include "codechal_hw.h" | |
| 29 | #include "codechal_debug.h" | |
| 30 | #include "mos_solo_generic.h" | |
| 31 | #include "codechal_setting.h" | |
| 32 | ||
| 33 | Codechal::Codechal( | |
| 34 | CodechalHwInterface *hwInterface, | |
| 35 | CodechalDebugInterface *debugInterface) | |
| 36 | { | |
| 37 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 38 | ||
| 39 | CODECHAL_PUBLIC_CHK_NULL_NO_STATUS_RETURN(hwInterface); | |
| 40 | CODECHAL_PUBLIC_CHK_NULL_NO_STATUS_RETURN(hwInterface->GetOsInterface()); | |
| 41 | MOS_UNUSED(debugInterface); | |
| 42 | ||
| 43 | m_hwInterface = hwInterface; | |
| 44 | m_osInterface = hwInterface->GetOsInterface(); | |
| 45 | ||
| 46 | if (m_hwInterface->bEnableVdboxBalancingbyUMD && m_osInterface->bEnableVdboxBalancing) | |
| 47 | { | |
| 48 | m_hwInterface->m_getVdboxNodeByUMD = true; | |
| 49 | } | |
| 50 | ||
| 51 | #if USE_CODECHAL_DEBUG_TOOL | |
| 52 | CODECHAL_PUBLIC_CHK_NULL_NO_STATUS_RETURN(debugInterface); | |
| 53 | m_debugInterface = debugInterface; | |
| 54 | #endif // USE_CODECHAL_DEBUG_TOOL | |
| 55 | } | |
| 56 | ||
| 57 | Codechal::~Codechal() | |
| 58 | { | |
| 59 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 60 | ||
| 61 | MOS_TraceEvent(EVENT_CODECHAL_DESTROY, EVENT_TYPE_START, nullptr, 0, nullptr, 0); | |
| 62 | ||
| 63 | #if USE_CODECHAL_DEBUG_TOOL | |
| 64 | if (m_debugInterface != nullptr) | |
| 65 | { | |
| 66 | MOS_Delete(m_debugInterface); | |
| 67 | m_debugInterface = nullptr; | |
| 68 | } | |
| 69 | ||
| 70 | if (m_statusReportDebugInterface != nullptr) | |
| 71 | { | |
| 72 | MOS_Delete(m_statusReportDebugInterface); | |
| 73 | m_statusReportDebugInterface = nullptr; | |
| 74 | } | |
| 75 | #endif // USE_CODECHAL_DEBUG_TOOL | |
| 76 | ||
| 77 | // Destroy HW interface objects (GSH, SSH, etc) | |
| 78 | if (m_hwInterface != nullptr) | |
| 79 | { | |
| 80 | MOS_Delete(m_hwInterface); | |
| 81 | m_hwInterface = nullptr; | |
| 82 | } | |
| 83 | ||
| 84 | // Destroy OS interface objects (CBs, etc) | |
| 85 | if (m_osInterface != nullptr) | |
| 86 | { | |
| 87 | m_osInterface->pfnDestroy(m_osInterface, false); | |
| 88 | ||
| 89 | // Deallocate OS interface structure (except if externally provided) | |
| 90 | if (m_osInterface->bDeallocateOnExit) | |
| 91 | { | |
| 92 | MOS_FreeMemory(m_osInterface); | |
| 93 | } | |
| 94 | } | |
| 95 | ||
| 96 | MOS_TraceEvent(EVENT_CODECHAL_DESTROY, EVENT_TYPE_END, nullptr, 0, nullptr, 0); | |
| 97 | } | |
| 98 | ||
| 99 | MOS_STATUS Codechal::Allocate(CodechalSetting *codecHalSettings) | |
| 100 | { | |
| 101 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 102 | ||
| 103 | CODECHAL_PUBLIC_CHK_NULL_RETURN(codecHalSettings); | |
| 104 | CODECHAL_PUBLIC_CHK_NULL_RETURN(m_hwInterface); | |
| 105 | CODECHAL_PUBLIC_CHK_NULL_RETURN(m_osInterface); | |
| 106 | ||
| 107 | MOS_TraceEvent(EVENT_CODECHAL_CREATE, | |
| 108 | EVENT_TYPE_INFO, | |
| 109 | &codecHalSettings->codecFunction, | |
| 110 | sizeof(uint32_t), | |
| 111 | nullptr, | |
| 112 | 0); | |
| 113 | ||
| 114 | CODECHAL_PUBLIC_CHK_STATUS_RETURN(m_hwInterface->Initialize(codecHalSettings)); | |
| 115 | ||
| 116 | MOS_NULL_RENDERING_FLAGS nullHWAccelerationEnable; | |
| 117 | nullHWAccelerationEnable.Value = 0; | |
| 118 | ||
| 119 | #if (_DEBUG || _RELEASE_INTERNAL) | |
| 120 | if (!m_statusReportDebugInterface) | |
| 121 | { | |
| 122 | m_statusReportDebugInterface = MOS_New(CodechalDebugInterface); | |
| 123 | CODECHAL_PUBLIC_CHK_NULL_RETURN(m_statusReportDebugInterface); | |
| 124 | CODECHAL_PUBLIC_CHK_STATUS_RETURN( | |
| 125 | m_statusReportDebugInterface->Initialize(m_hwInterface, codecHalSettings->codecFunction)); | |
| 126 | } | |
| 127 | ||
| 128 | MOS_USER_FEATURE_VALUE_DATA userFeatureData; | |
| 129 | MOS_ZeroMemory(&userFeatureData, sizeof(userFeatureData)); | |
| 130 | MOS_UserFeature_ReadValue_ID( | |
| 131 | nullptr, | |
| 132 | __MEDIA_USER_FEATURE_VALUE_NULL_HW_ACCELERATION_ENABLE_ID, | |
| 133 | &userFeatureData, | |
| 134 | m_osInterface->pOsContext); | |
| 135 | nullHWAccelerationEnable.Value = userFeatureData.u32Data; | |
| 136 | ||
| 137 | m_useNullHw[MOS_GPU_CONTEXT_VIDEO] = | |
| 138 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVideo); | |
| 139 | m_useNullHw[MOS_GPU_CONTEXT_VIDEO2] = | |
| 140 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVideo2); | |
| 141 | m_useNullHw[MOS_GPU_CONTEXT_VIDEO3] = | |
| 142 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVideo3); | |
| 143 | m_useNullHw[MOS_GPU_CONTEXT_VDBOX2_VIDEO] = | |
| 144 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVDBox2Video); | |
| 145 | m_useNullHw[MOS_GPU_CONTEXT_VDBOX2_VIDEO2] = | |
| 146 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVDBox2Video2); | |
| 147 | m_useNullHw[MOS_GPU_CONTEXT_VDBOX2_VIDEO3] = | |
| 148 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxVDBox2Video3); | |
| 149 | m_useNullHw[MOS_GPU_CONTEXT_RENDER] = | |
| 150 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxRender); | |
| 151 | m_useNullHw[MOS_GPU_CONTEXT_RENDER2] = | |
| 152 | (nullHWAccelerationEnable.CodecGlobal || nullHWAccelerationEnable.CtxRender2); | |
| 153 | #endif // _DEBUG || _RELEASE_INTERNAL | |
| 154 | ||
| 155 | return MOS_STATUS_SUCCESS; | |
| 156 | } | |
| 157 | ||
| 158 | MOS_STATUS Codechal::BeginFrame() | |
| 159 | { | |
| 160 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 161 | return MOS_STATUS_SUCCESS; | |
| 162 | } | |
| 163 | ||
| 164 | MOS_STATUS Codechal::EndFrame() | |
| 165 | { | |
| 166 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 167 | return MOS_STATUS_SUCCESS; | |
| 168 | } | |
| 169 | ||
| 170 | MOS_STATUS Codechal::Execute(void *params) | |
| 171 | { | |
| 172 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 173 | ||
| 174 | CODECHAL_PUBLIC_CHK_NULL_RETURN(params); | |
| 175 | ||
| 176 | CODECHAL_DEBUG_TOOL( | |
| 177 | CODECHAL_PUBLIC_CHK_NULL_RETURN(m_osInterface); | |
| 178 | CODECHAL_PUBLIC_CHK_NULL_RETURN(m_debugInterface); | |
| 179 | ||
| 180 | CODECHAL_PUBLIC_CHK_STATUS_RETURN(Mos_Solo_ForceDumps( | |
| 181 | m_debugInterface->m_bufferDumpFrameNum, | |
| 182 | m_osInterface));) | |
| 183 | ||
| 184 | return MOS_STATUS_SUCCESS; | |
| 185 | } | |
| 186 | ||
| 187 | MOS_STATUS Codechal::GetStatusReport( | |
| 188 | void *status, | |
| 189 | uint16_t numStatus) | |
| 190 | { | |
| 191 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 192 | MOS_UNUSED(status); | |
| 193 | MOS_UNUSED(numStatus); | |
| 194 | CODECHAL_PUBLIC_ASSERTMESSAGE("Unsupported codec function requested."); | |
| 195 | return MOS_STATUS_UNKNOWN; | |
| 196 | } | |
| 197 | ||
| 198 | void Codechal::Destroy() | |
| 199 | { | |
| 200 | CODECHAL_PUBLIC_FUNCTION_ENTER; | |
| 201 | } | |
| 202 | ||
| 203 | MOS_STATUS Codechal::ResolveMetaData(PMOS_RESOURCE pInput, PMOS_RESOURCE pOutput) | |
| 204 | { | |
| 205 | return MOS_STATUS_SUCCESS; | |
| 206 | }⏎ |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codechal_common.h | |
| 23 | //! \brief Defines the public interface for CodecHal. | |
| 24 | //! | |
| 25 | #ifndef __CODECHAL_COMMON_H__ | |
| 26 | #define __CODECHAL_COMMON_H__ | |
| 27 | ||
| 28 | #include "mos_os.h" | |
| 29 | #include "mos_util_debug.h" | |
| 30 | ||
| 31 | class CodechalDebugInterface; | |
| 32 | class CodechalHwInterface; | |
| 33 | class CodechalSetting; | |
| 34 | ||
| 35 | //------------------------------------------------------------------------------ | |
| 36 | // Simplified macros for debug message, Assert, Null check and MOS eStatus check | |
| 37 | // within Codechal without the need to explicitly pass comp and sub-comp name | |
| 38 | //------------------------------------------------------------------------------ | |
| 39 | //------------------------------------------------------------------------------ | |
| 40 | // Macros specific to MOS_CODEC_SUBCOMP_PUBLIC sub-comp | |
| 41 | //------------------------------------------------------------------------------ | |
| 42 | #define CODECHAL_PUBLIC_ASSERT(_expr) \ | |
| 43 | MOS_ASSERT(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _expr) | |
| 44 | ||
| 45 | #define CODECHAL_PUBLIC_ASSERTMESSAGE(_message, ...) \ | |
| 46 | MOS_ASSERTMESSAGE(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _message, ##__VA_ARGS__) | |
| 47 | ||
| 48 | #define CODECHAL_PUBLIC_NORMALMESSAGE(_message, ...) \ | |
| 49 | MOS_NORMALMESSAGE(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _message, ##__VA_ARGS__) | |
| 50 | ||
| 51 | #define CODECHAL_PUBLIC_VERBOSEMESSAGE(_message, ...) \ | |
| 52 | MOS_VERBOSEMESSAGE(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _message, ##__VA_ARGS__) | |
| 53 | ||
| 54 | #define CODECHAL_PUBLIC_FUNCTION_ENTER \ | |
| 55 | MOS_FUNCTION_ENTER(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC) | |
| 56 | ||
| 57 | #define CODECHAL_PUBLIC_CHK_STATUS_RETURN(_stmt) \ | |
| 58 | MOS_CHK_STATUS_RETURN(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _stmt) | |
| 59 | ||
| 60 | #define CODECHAL_PUBLIC_CHK_STATUS_MESSAGE(_stmt, _message, ...) \ | |
| 61 | MOS_CHK_STATUS_MESSAGE(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _stmt, _message, ##__VA_ARGS__) | |
| 62 | ||
| 63 | #define CODECHAL_PUBLIC_CHK_NULL_RETURN(_ptr) \ | |
| 64 | MOS_CHK_NULL_RETURN(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _ptr) | |
| 65 | ||
| 66 | #define CODECHAL_PUBLIC_CHK_NULL_NO_STATUS_RETURN(_ptr) \ | |
| 67 | MOS_CHK_NULL_NO_STATUS_RETURN(MOS_COMPONENT_CODEC, MOS_CODEC_SUBCOMP_PUBLIC, _ptr) | |
| 68 | ||
| 69 | //! | |
| 70 | //! \class Codechal | |
| 71 | //! \brief This class defines the common member fields, functions etc as Codechal base class. | |
| 72 | //! | |
| 73 | class Codechal | |
| 74 | { | |
| 75 | public: | |
| 76 | //! | |
| 77 | //! \brief Constructor | |
| 78 | //! \param [in] hwInterface | |
| 79 | //! Hardware interface | |
| 80 | //! \param [in] debugInterface | |
| 81 | //! Debug interface | |
| 82 | //! | |
| 83 | Codechal( | |
| 84 | CodechalHwInterface *hwInterface, | |
| 85 | CodechalDebugInterface *debugInterface); | |
| 86 | ||
| 87 | //! | |
| 88 | //! \brief Copy constructor | |
| 89 | //! | |
| 90 | Codechal(const Codechal&) = delete; | |
| 91 | ||
| 92 | //! | |
| 93 | //! \brief Copy assignment operator | |
| 94 | //! | |
| 95 | Codechal& operator=(const Codechal&) = delete; | |
| 96 | ||
| 97 | //! | |
| 98 | //! \brief Destructor | |
| 99 | //! | |
| 100 | virtual ~Codechal(); | |
| 101 | ||
| 102 | //! | |
| 103 | //! \brief Allocate and intialize the Codechal. | |
| 104 | //! \param [in] codecHalSettings | |
| 105 | //! Settings used to finalize the creation of the CodecHal device | |
| 106 | //! \return MOS_STATUS | |
| 107 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 108 | //! | |
| 109 | virtual MOS_STATUS Allocate(CodechalSetting *codecHalSettings); | |
| 110 | ||
| 111 | //! | |
| 112 | //! \brief Signals the beginning of a picture. | |
| 113 | //! \details Initializes necessary parameters to perform the requested operation. | |
| 114 | //! \return MOS_STATUS | |
| 115 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 116 | //! | |
| 117 | virtual MOS_STATUS BeginFrame(); | |
| 118 | ||
| 119 | //! | |
| 120 | //! \brief Signals the end of a picture. | |
| 121 | //! \details This function closes out the picture which was started by BeginFrame(). | |
| 122 | //! All Execute() calls for a particular picture must be complete before | |
| 123 | //! EndFrame() is called. Resets all current picture parameters in | |
| 124 | //! preparation for the next BeginFrame(). For decode, in the case | |
| 125 | //! of incomplete frames, if the picture is still incomplete at EndFrame(), | |
| 126 | //! CodecHal conceals the error internally and submits the codec workload. | |
| 127 | //! \return MOS_STATUS | |
| 128 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 129 | //! | |
| 130 | virtual MOS_STATUS EndFrame(); | |
| 131 | ||
| 132 | //! | |
| 133 | //! \brief Performs the operation requested by the codec function. | |
| 134 | //! \param [in] params | |
| 135 | //! Parameters need to perform the requested function. The parameter structure | |
| 136 | //! changes based on codec function. | |
| 137 | //! \return MOS_STATUS | |
| 138 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 139 | //! | |
| 140 | virtual MOS_STATUS Execute(void *params); | |
| 141 | ||
| 142 | //! | |
| 143 | //! \brief Gets available statuses for executed pictures. | |
| 144 | //! \details All pictures for which EndFrame() has been called are eligable | |
| 145 | //! for status reporting. Once a successful or error status is reported out by | |
| 146 | //! CodecHal, it is discarded. | |
| 147 | //! \param [out] status | |
| 148 | //! Array to store statuses up to a maximum of wNumStatus, valid pointer | |
| 149 | //! must be passed in to GetStatusReport() | |
| 150 | //! \param [in] numStatus | |
| 151 | //! The size of the pCodecStatus array | |
| 152 | //! \return MOS_STATUS | |
| 153 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 154 | //! | |
| 155 | virtual MOS_STATUS GetStatusReport( | |
| 156 | void *status, | |
| 157 | uint16_t numStatus); | |
| 158 | ||
| 159 | //! | |
| 160 | //! \brief Destroy codechl state | |
| 161 | //! | |
| 162 | //! \return void | |
| 163 | //! | |
| 164 | virtual void Destroy(); | |
| 165 | ||
| 166 | //! | |
| 167 | //! \brief Resolve MetaData. | |
| 168 | //! \details Resolve MetaData from Input to Output. | |
| 169 | //! \param [out] pOutput | |
| 170 | //! Resolved Metadata resource. | |
| 171 | //! \param [in] pInput | |
| 172 | //! Metadata resource to be resolve. | |
| 173 | //! \return MOS_STATUS | |
| 174 | //! MOS_STATUS_SUCCESS if success else fail reason | |
| 175 | //! | |
| 176 | virtual MOS_STATUS ResolveMetaData(PMOS_RESOURCE pInput, PMOS_RESOURCE pOutput); | |
| 177 | ||
| 178 | //! | |
| 179 | //! \brief Gets hardware interface. | |
| 180 | //! \return CodechalHwInterface | |
| 181 | //! return hardware interface | |
| 182 | //! | |
| 183 | CodechalHwInterface *GetHwInterface() { return m_hwInterface; } | |
| 184 | ||
| 185 | //! | |
| 186 | //! \brief Gets OS interface. | |
| 187 | //! \return PMOS_INTERFACE | |
| 188 | //! return OS interface | |
| 189 | //! | |
| 190 | PMOS_INTERFACE GetOsInterface() { return m_osInterface; } | |
| 191 | ||
| 192 | //! | |
| 193 | //! \brief Gets debug interface. | |
| 194 | //! \return CodechalDebugInterface | |
| 195 | //! return debug interface | |
| 196 | //! | |
| 197 | CodechalDebugInterface *GetDebugInterface() { return m_debugInterface; } | |
| 198 | ||
| 199 | //! | |
| 200 | //! \brief Check if Apogeios enabled. | |
| 201 | //! \return bool | |
| 202 | //! return m_apogeiosEnable | |
| 203 | //! | |
| 204 | bool IsApogeiosEnabled() { return m_apogeiosEnable; } | |
| 205 | protected: | |
| 206 | //! \brief HW Inteface | |
| 207 | //! \details Responsible for constructing all defined states and commands. | |
| 208 | //! Each HAL has a separate OS interface. | |
| 209 | CodechalHwInterface *m_hwInterface = nullptr; | |
| 210 | ||
| 211 | //! \brief Os Inteface | |
| 212 | //! \details Used to abstract all OS and KMD interactions such that CodecHal may be | |
| 213 | //! OS agnostic. Each HAL has a separate OS interface. | |
| 214 | PMOS_INTERFACE m_osInterface = nullptr; | |
| 215 | ||
| 216 | //! \brief Interface used for debug dumps. | |
| 217 | //! \details This interface is only valid for release internal and debug builds. | |
| 218 | CodechalDebugInterface *m_debugInterface = nullptr; | |
| 219 | ||
| 220 | //! \brief Interface used for debug dumps in GetStatusReport. | |
| 221 | //! \details This interface is only valid for release internal and debug builds. | |
| 222 | CodechalDebugInterface *m_statusReportDebugInterface = nullptr; | |
| 223 | ||
| 224 | //! \brief Indicates whether or not using null hardware | |
| 225 | bool m_useNullHw[MOS_GPU_CONTEXT_MAX] = { false }; | |
| 226 | ||
| 227 | //! \brief Apogeios Enable Flag | |
| 228 | bool m_apogeiosEnable = false; | |
| 229 | }; | |
| 230 | ||
| 231 | #endif |
| 0 | /* | |
| 1 | * Copyright (c) 2011-2017, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codechal_setting.cpp | |
| 23 | //! \brief Implements class CodechalSetting | |
| 24 | //! | |
| 25 | ||
| 26 | #include "codechal_setting.h" | |
| 27 | ||
| 28 | ||
| 29 | CodechalSetting *CodechalSetting::CreateCodechalSetting() | |
| 30 | { | |
| 31 | return MOS_New(CodechalSetting); | |
| 32 | } | |
| 33 |
| 0 | /* | |
| 1 | * Copyright (c) 2011-2020, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file codechal_setting.h | |
| 23 | //! \brief Defines class CodechalSetting | |
| 24 | //! | |
| 25 | #ifndef __CODECHAL_SETTING_H__ | |
| 26 | #define __CODECHAL_SETTING_H__ | |
| 27 | ||
| 28 | #include "codec_def_common.h" | |
| 29 | //! | |
| 30 | //! \class CodechalSetting | |
| 31 | //! \brief Settings used to finalize the creation of the CodecHal device | |
| 32 | //! | |
| 33 | class CodechalSetting | |
| 34 | { | |
| 35 | public: | |
| 36 | CODECHAL_FUNCTION codecFunction = CODECHAL_FUNCTION_INVALID; //!< High level codec functionality requested. | |
| 37 | /*! \brief Width requested. | |
| 38 | * | |
| 39 | * For encode this width must be the maximum width for the entire stream to be encoded, for decode dynamic allocation is supported and this width is the largest width recieved. | |
| 40 | */ | |
| 41 | uint32_t width = 0; | |
| 42 | /*! \brief Height requested. | |
| 43 | * | |
| 44 | * For encode this height must be the maximum height for the entire stream to be encoded, for decode dynamic allocation is supported and this height is the largest height recieved. | |
| 45 | */ | |
| 46 | uint32_t height = 0; | |
| 47 | uint32_t mode = 0; //!< Mode requested (high level combination between Standard and CodecFunction). | |
| 48 | uint32_t standard = 0; //!< Codec standard requested. | |
| 49 | uint8_t lumaChromaDepth = 0; //!< Applies currently to HEVC only, specifies bit depth as either 8 or 10 bits. | |
| 50 | uint8_t chromaFormat = 0; //!< Applies currently to HEVC/VP9 only, specifies chromaformat as 420/422/444. | |
| 51 | bool intelEntrypointInUse = false; //!< Applies to decode only, application is using a Intel-specific entrypoint. | |
| 52 | bool shortFormatInUse = false; //!< Applies to decode only, application is passing short format slice data. | |
| 53 | ||
| 54 | bool disableDecodeSyncLock = false; //!< Flag to indicate if Decode O/P can be locked for sync. | |
| 55 | ||
| 56 | // Decode Downsampling | |
| 57 | bool downsamplingHinted = false; //!< Applies to decode only, application may request field scaling. | |
| 58 | ||
| 59 | bool disableUltraHME = false; //!< Applies currently to HEVC VDEnc only to disable UHME | |
| 60 | bool disableSuperHME = false; //!< Applies currently to HEVC VDEnc only to disable SHME | |
| 61 | void *cpParams = nullptr; //!< CP params | |
| 62 | bool isMfeEnabled = false; //!< Flag to indicate if Mfe is enabled. | |
| 63 | ||
| 64 | // Decode SFC enabling | |
| 65 | bool sfcEnablingHinted = false; //!< Applies to decode only, application may request field sfc. | |
| 66 | bool sfcInUseHinted = false; //!< Applies to decode only, application may request sfc engine. | |
| 67 | bool enableCodecMmc = true; //!< Applies to both of decode and encode, to indicate if codec MMC could be enabled by default | |
| 68 | bool secureMode = false; //!< secure decoder is required if enabled | |
| 69 | ||
| 70 | // HEVC Encode only | |
| 71 | bool isSCCEnabled = false; //!< Flag to indicate if HEVC SCC is enabled. | |
| 72 | ||
| 73 | //! | |
| 74 | //! \brief Destructor | |
| 75 | //! | |
| 76 | virtual ~CodechalSetting(){}; | |
| 77 | ||
| 78 | //! | |
| 79 | //! \brief Return the pointer to CP parameters | |
| 80 | //! | |
| 81 | void *GetCpParams() { return cpParams; }; | |
| 82 | ||
| 83 | //! | |
| 84 | //! \brief Return the indicate if cenc advance is used or not | |
| 85 | //! | |
| 86 | virtual bool CheckCencAdvance() {return false; }; | |
| 87 | ||
| 88 | //! | |
| 89 | //! \brief Create CodechalSetting instance | |
| 90 | //! | |
| 91 | static CodechalSetting *CreateCodechalSetting(); | |
| 92 | }; | |
| 93 | ||
| 94 | #endif |
| 27 | 27 | #include "media_user_settings_mgr_g12.h" |
| 28 | 28 | #include "codechal_setting.h" |
| 29 | 29 | #include "decode_av1_feature_manager.h" |
| 30 | #include "decode_huc_packet_creator_base.h" | |
| 30 | 31 | |
| 31 | 32 | namespace decode { |
| 32 | 33 | |
| 43 | 44 | DECODE_FUNC_CALL(); |
| 44 | 45 | DECODE_CHK_STATUS(DecodePipeline::Initialize(settings)); |
| 45 | 46 | |
| 46 | m_cdfCopyPkt = MOS_New(HucCopyPkt, this, m_task, m_hwInterface); | |
| 47 | HucPacketCreatorBase *hucPktCreator = dynamic_cast<HucPacketCreatorBase *>(this); | |
| 48 | DECODE_CHK_NULL(hucPktCreator); | |
| 49 | m_cdfCopyPkt = hucPktCreator->CreateHucCopyPkt(this, m_task, m_hwInterface); | |
| 47 | 50 | DECODE_CHK_NULL(m_cdfCopyPkt); |
| 48 | DECODE_CHK_STATUS(RegisterPacket(DecodePacketId(this, defaultCdfBufCopyPacketId), m_cdfCopyPkt)); | |
| 49 | DECODE_CHK_STATUS(m_cdfCopyPkt->Init()); | |
| 51 | MediaPacket *packet = dynamic_cast<MediaPacket *>(m_cdfCopyPkt); | |
| 52 | DECODE_CHK_NULL(packet); | |
| 53 | DECODE_CHK_STATUS(RegisterPacket(DecodePacketId(this, defaultCdfBufCopyPacketId), packet)); | |
| 54 | DECODE_CHK_STATUS(packet->Init()); | |
| 50 | 55 | |
| 51 | 56 | auto *codecSettings = (CodechalSetting*)settings; |
| 52 | 57 | DECODE_CHK_NULL(codecSettings); |
| 80 | 85 | { |
| 81 | 86 | for (uint8_t i = 0; i < basicFeature->av1DefaultCdfTableNum; i++) |
| 82 | 87 | { |
| 83 | HucCopyPkt::HucCopyParams copyParams = {}; | |
| 88 | HucCopyPktItf::HucCopyParams copyParams = {}; | |
| 84 | 89 | copyParams.srcBuffer = &(basicFeature->m_tmpCdfBuffers[i]->OsResource); |
| 85 | 90 | copyParams.srcOffset = 0; |
| 86 | 91 | copyParams.destBuffer = &(basicFeature->m_defaultCdfBuffers[i]->OsResource); |
| 156 | 161 | DECODE_FUNC_CALL(); |
| 157 | 162 | m_featureManager = MOS_New(DecodeAv1FeatureManager, m_allocator, m_hwInterface); |
| 158 | 163 | DECODE_CHK_NULL(m_featureManager); |
| 164 | return MOS_STATUS_SUCCESS; | |
| 165 | } | |
| 166 | ||
| 167 | MOS_STATUS Av1Pipeline::CreateSubPackets(DecodeSubPacketManager &subPacketManager, CodechalSetting &codecSettings) | |
| 168 | { | |
| 169 | DECODE_FUNC_CALL(); | |
| 170 | ||
| 171 | DECODE_CHK_STATUS(DecodePipeline::CreateSubPackets(subPacketManager, codecSettings)); | |
| 172 | ||
| 159 | 173 | return MOS_STATUS_SUCCESS; |
| 160 | 174 | } |
| 161 | 175 | |
| 110 | 110 | //! |
| 111 | 111 | virtual MOS_STATUS CreateFeatureManager() override; |
| 112 | 112 | |
| 113 | //! | |
| 114 | //! \brief Create sub packets | |
| 115 | //! \param [in] codecSettings | |
| 116 | //! Point to codechal settings | |
| 117 | //! \return MOS_STATUS | |
| 118 | //! MOS_STATUS_SUCCESS if success, else fail reason | |
| 119 | //! | |
| 120 | virtual MOS_STATUS CreateSubPackets(DecodeSubPacketManager &subPacketManager, CodechalSetting &codecSettings) override; | |
| 121 | ||
| 113 | 122 | #if USE_CODECHAL_DEBUG_TOOL |
| 114 | 123 | //! \brief Dump the parameters |
| 115 | 124 | //! |
| 140 | 149 | #endif |
| 141 | 150 | |
| 142 | 151 | protected: |
| 143 | HucCopyPkt *m_cdfCopyPkt = nullptr; //!< Update default cdf buffer with huc stream out packet | |
| 152 | HucCopyPktItf *m_cdfCopyPkt = nullptr; //!< Update default cdf buffer with huc stream out packet | |
| 144 | 153 | Av1DecodeMode m_decodeMode = baseDecodeMode; //!< Decode mode |
| 145 | 154 | uint16_t m_passNum = 1; //!< Decode pass number |
| 146 | 155 | bool m_isFirstTileInFrm = true; //!< First tile in the first frame |
| 96 | 96 | bool initOnAllocate, uint8_t initValue, bool bPersistent) |
| 97 | 97 | { |
| 98 | 98 | if (!m_allocator) |
| 99 | return nullptr; | |
| 99 | { | |
| 100 | return nullptr; | |
| 101 | } | |
| 100 | 102 | |
| 101 | 103 | BufferArray * bufferArray = MOS_New(BufferArray, this); |
| 102 | 104 | if (bufferArray == nullptr) |
| 121 | 123 | MOS_TILE_MODE_GMM gmmTileMode) |
| 122 | 124 | { |
| 123 | 125 | if (!m_allocator) |
| 124 | return nullptr; | |
| 126 | { | |
| 127 | return nullptr; | |
| 128 | } | |
| 125 | 129 | |
| 126 | 130 | MOS_ALLOC_GFXRES_PARAMS allocParams; |
| 127 | 131 | MOS_ZeroMemory(&allocParams, sizeof(MOS_ALLOC_GFXRES_PARAMS)); |
| 150 | 154 | return surface; |
| 151 | 155 | } |
| 152 | 156 | |
| 157 | #if (_DEBUG || _RELEASE_INTERNAL) | |
| 158 | MOS_SURFACE *DecodeAllocator::AllocateLinearSurface( | |
| 159 | const uint32_t width, const uint32_t height, const char *nameOfSurface, | |
| 160 | MOS_FORMAT format, bool isCompressible, | |
| 161 | ResourceUsage resUsageType, ResourceAccessReq accessReq, | |
| 162 | MOS_TILE_MODE_GMM gmmTileMode) | |
| 163 | { | |
| 164 | if (!m_allocator) | |
| 165 | { | |
| 166 | return nullptr; | |
| 167 | } | |
| 168 | ||
| 169 | MOS_ALLOC_GFXRES_PARAMS allocParams; | |
| 170 | MOS_ZeroMemory(&allocParams, sizeof(MOS_ALLOC_GFXRES_PARAMS)); | |
| 171 | allocParams.Type = MOS_GFXRES_2D; | |
| 172 | allocParams.TileType = MOS_TILE_LINEAR; | |
| 173 | allocParams.Format = format; | |
| 174 | allocParams.dwWidth = width; | |
| 175 | allocParams.dwHeight = height; | |
| 176 | allocParams.dwArraySize = 1; | |
| 177 | allocParams.pBufName = nameOfSurface; | |
| 178 | allocParams.bIsCompressible = isCompressible; | |
| 179 | allocParams.ResUsageType = static_cast<MOS_HW_RESOURCE_DEF>(resUsageType); | |
| 180 | allocParams.m_tileModeByForce = gmmTileMode; | |
| 181 | SetAccessRequirement(accessReq, allocParams); | |
| 182 | ||
| 183 | MOS_SURFACE *surface = m_allocator->AllocateSurface(allocParams, false, COMPONENT_Decode); | |
| 184 | if (surface == nullptr) | |
| 185 | { | |
| 186 | return nullptr; | |
| 187 | } | |
| 188 | if (GetSurfaceInfo(surface) != MOS_STATUS_SUCCESS) | |
| 189 | { | |
| 190 | DECODE_ASSERTMESSAGE("Failed to get surface informaton for %s", nameOfSurface); | |
| 191 | } | |
| 192 | ||
| 193 | return surface; | |
| 194 | } | |
| 195 | #endif | |
| 196 | ||
| 153 | 197 | SurfaceArray * DecodeAllocator::AllocateSurfaceArray( |
| 154 | 198 | const uint32_t width, const uint32_t height, const char* nameOfSurface, |
| 155 | 199 | const uint32_t numberOfSurface, MOS_FORMAT format, bool isCompressed, |
| 178 | 178 | const uint32_t numberOfSurface, MOS_FORMAT format = Format_NV12, bool isCompressed = false, |
| 179 | 179 | ResourceUsage resUsageType = resourceDefault, ResourceAccessReq accessReq = lockableVideoMem); |
| 180 | 180 | |
| 181 | #if (_DEBUG || _RELEASE_INTERNAL) | |
| 182 | //! | |
| 183 | //! \brief Allocate Linear Output Surface | |
| 184 | //! \param [in] width | |
| 185 | //! surface width | |
| 186 | //! \param [in] height | |
| 187 | //! surface height | |
| 188 | //! \param [in] surfaceName | |
| 189 | //! Surface name | |
| 190 | //! \param [in] format | |
| 191 | //! Surface format, by default is NV12 | |
| 192 | //! \param [in] compressible | |
| 193 | //! Compressible flag, by default is false | |
| 194 | //! \param [in] resUsageType | |
| 195 | //! ResourceUsage to be set | |
| 196 | //! \param [in] gmmTileMode | |
| 197 | //! Specified GMM tile mode | |
| 198 | //! | |
| 199 | MOS_SURFACE * AllocateLinearSurface( | |
| 200 | const uint32_t width, const uint32_t height, const char *nameOfSurface, | |
| 201 | MOS_FORMAT format = Format_NV12, bool isCompressible = false, | |
| 202 | ResourceUsage resUsageType = resourceDefault, ResourceAccessReq accessReq = lockableVideoMem, | |
| 203 | MOS_TILE_MODE_GMM gmmTileMode = MOS_TILE_UNSET_GMM); | |
| 204 | #endif | |
| 181 | 205 | //! |
| 182 | 206 | //! \brief Allocate batch buffer |
| 183 | 207 | //! \param [in] sizeOfBuffer |
| 29 | 29 | #include "decode_basic_feature.h" |
| 30 | 30 | #include "decode_pipeline.h" |
| 31 | 31 | |
| 32 | #include "decode_huc_packet_creator_base.h" | |
| 33 | ||
| 32 | 34 | namespace decode { |
| 33 | 35 | |
| 34 | 36 | DecodeInputBitstream::DecodeInputBitstream(DecodePipeline* pipeline, MediaTask* task, uint8_t numVdbox) |
| 58 | 60 | m_basicFeature = dynamic_cast<DecodeBasicFeature*>(featureManager->GetFeature(FeatureIDs::basicFeature)); |
| 59 | 61 | DECODE_CHK_NULL(m_basicFeature); |
| 60 | 62 | |
| 61 | m_concatPkt = MOS_New(HucCopyPkt, m_pipeline, m_task, hwInterface); | |
| 63 | HucPacketCreatorBase *hucPktCreator = dynamic_cast<HucPacketCreatorBase *>(m_pipeline); | |
| 64 | DECODE_CHK_NULL(hucPktCreator); | |
| 65 | m_concatPkt = hucPktCreator->CreateHucCopyPkt(m_pipeline, m_task, hwInterface); | |
| 62 | 66 | DECODE_CHK_NULL(m_concatPkt); |
| 63 | DECODE_CHK_STATUS(RegisterPacket(DecodePacketId(m_pipeline, hucCopyPacketId), *m_concatPkt)); | |
| 64 | DECODE_CHK_STATUS(m_concatPkt->Init()); | |
| 67 | MediaPacket *packet = dynamic_cast<MediaPacket *>(m_concatPkt); | |
| 68 | DECODE_CHK_NULL(packet); | |
| 69 | DECODE_CHK_STATUS(RegisterPacket(DecodePacketId(m_pipeline, hucCopyPacketId), *packet)); | |
| 70 | DECODE_CHK_STATUS(packet->Init()); | |
| 65 | 71 | |
| 66 | 72 | return MOS_STATUS_SUCCESS; |
| 67 | 73 | } |
| 144 | 150 | |
| 145 | 151 | void DecodeInputBitstream::AddNewSegment(MOS_RESOURCE& resource, uint32_t offset, uint32_t size) |
| 146 | 152 | { |
| 147 | HucCopyPkt::HucCopyParams copyParams; | |
| 153 | HucCopyPktItf::HucCopyParams copyParams; | |
| 148 | 154 | copyParams.srcBuffer = &resource; |
| 149 | 155 | copyParams.srcOffset = offset; |
| 150 | 156 | copyParams.destBuffer = &(m_catenatedBuffer->OsResource); |
| 29 | 29 | #define __DECODE_INPUT_BITSTREAM_H__ |
| 30 | 30 | |
| 31 | 31 | #include "decode_packet_id.h" |
| 32 | #include "decode_huc_copy_packet.h" | |
| 33 | 32 | #include "decode_resource_array.h" |
| 34 | 33 | #include "decode_sub_pipeline.h" |
| 35 | 34 | #include "codec_def_decode.h" |
| 36 | 35 | #include "media_feature_manager.h" |
| 36 | #include "decode_basic_feature.h" | |
| 37 | #include "decode_huc_copy_packet_itf.h" | |
| 38 | #include "decode_status_report.h" | |
| 37 | 39 | |
| 38 | 40 | namespace decode { |
| 39 | 41 | |
| 138 | 140 | DecodeBasicFeature* m_basicFeature = nullptr; //!< Decode basic feature |
| 139 | 141 | DecodeAllocator * m_allocator = nullptr; //!< Resource allocator |
| 140 | 142 | |
| 141 | HucCopyPkt * m_concatPkt = nullptr; //!< Bitstream concat packet | |
| 143 | HucCopyPktItf * m_concatPkt = nullptr; //!< Bitstream concat packet | |
| 142 | 144 | PMOS_BUFFER m_catenatedBuffer = nullptr; //!< Catenated bitstream for decode |
| 143 | 145 | uint32_t m_requiredSize = 0; //!< Size of bitstream in bytes of current frame |
| 144 | 146 | uint32_t m_segmentsTotalSize = 0; //!< Total size of segments in m_segments |
+56
-0
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file decode_huc_copy_packet_itf.h | |
| 23 | //! \brief Defines the implementation of huc copy packet | |
| 24 | //! | |
| 25 | ||
| 26 | #ifndef __CODECHAL_HUC_COPY_PACKET_ITF_H__ | |
| 27 | #define __CODECHAL_HUC_COPY_PACKET_ITF_H__ | |
| 28 | ||
| 29 | #include "decode_utils.h" | |
| 30 | #include "mos_os_specific.h" | |
| 31 | namespace decode | |
| 32 | { | |
| 33 | class HucCopyPktItf | |
| 34 | { | |
| 35 | public: | |
| 36 | struct HucCopyParams | |
| 37 | { | |
| 38 | PMOS_RESOURCE srcBuffer; | |
| 39 | uint32_t srcOffset; | |
| 40 | PMOS_RESOURCE destBuffer; | |
| 41 | uint32_t destOffset; | |
| 42 | uint32_t copyLength; | |
| 43 | }; | |
| 44 | ||
| 45 | HucCopyPktItf() | |
| 46 | { | |
| 47 | } | |
| 48 | ||
| 49 | virtual ~HucCopyPktItf() {} | |
| 50 | ||
| 51 | virtual MOS_STATUS PushCopyParams(HucCopyParams ©Params) = 0; | |
| 52 | }; | |
| 53 | ||
| 54 | } // namespace decode | |
| 55 | #endif⏎ |
+53
-0
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file decode_huc_packet_creator_base.h | |
| 23 | //! | |
| 24 | ||
| 25 | #ifndef __CODECHAL_HUC_PACKET_CREATOR_BASE_H__ | |
| 26 | #define __CODECHAL_HUC_PACKET_CREATOR_BASE_H__ | |
| 27 | ||
| 28 | #include "decode_huc_copy_packet_itf.h" | |
| 29 | #include "media_cmd_packet.h" | |
| 30 | #include "media_pipeline.h" | |
| 31 | #include "codechal_hw.h" | |
| 32 | ||
| 33 | namespace decode | |
| 34 | { | |
| 35 | class HucPacketCreatorBase | |
| 36 | { | |
| 37 | public: | |
| 38 | ||
| 39 | HucPacketCreatorBase() | |
| 40 | { | |
| 41 | } | |
| 42 | ||
| 43 | virtual ~HucPacketCreatorBase() {} | |
| 44 | ||
| 45 | virtual HucCopyPktItf *CreateHucCopyPkt(MediaPipeline *pipeline, MediaTask *task, CodechalHwInterface *hwInterface) = 0; | |
| 46 | virtual CmdPacket * CreateProbUpdatePkt(MediaPipeline *pipeline, MediaTask *task, CodechalHwInterface *hwInterface) = 0; | |
| 47 | ||
| 48 | ||
| 49 | }; | |
| 50 | ||
| 51 | } // namespace decode | |
| 52 | #endif⏎ |
| 0 | # Copyright (c) 2020, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | ||
| 21 | set(TMP_HEADERS_ | |
| 22 | ${TMP_HEADERS_} | |
| 23 | ${CMAKE_CURRENT_LIST_DIR}/decode_huc_packet_creator_base.h | |
| 24 | ${CMAKE_CURRENT_LIST_DIR}/decode_huc_copy_packet_itf.h | |
| 25 | ) | |
| 26 | ||
| 27 | media_add_curr_to_include_path() |
| 24 | 24 | media_include_subdirectory(scalability) |
| 25 | 25 | media_include_subdirectory(statusreport) |
| 26 | 26 | media_include_subdirectory(mmc) |
| 27 | media_include_subdirectory(hucItf) | |
| 27 | 28 | |
| 28 | 29 | set(TMP_SOURCES_ |
| 29 | 30 | ${TMP_SOURCES_} |
+21
-18
| 123 | 123 | |
| 124 | 124 | DECODE_CHK_NULL(m_downSampling->m_inputSurface); |
| 125 | 125 | |
| 126 | // x + width/ y + height is the effective width/height of SFC input, which may be smaller than frame width/height. | |
| 127 | sfcParams.input.width = m_downSampling->m_inputSurfaceRegion.m_x + | |
| 128 | m_downSampling->m_inputSurfaceRegion.m_width; | |
| 129 | sfcParams.input.height = m_downSampling->m_inputSurfaceRegion.m_y + | |
| 130 | m_downSampling->m_inputSurfaceRegion.m_height; | |
| 131 | sfcParams.input.format = m_downSampling->m_inputSurface->Format; | |
| 132 | sfcParams.input.colorSpace = CSpace_Any; | |
| 133 | sfcParams.input.chromaSiting = m_downSampling->m_chromaSitingType; | |
| 134 | sfcParams.input.mirrorEnabled = (m_downSampling->m_mirrorState != 0); | |
| 126 | // VD-SFC Input Frame width/height must equal to decoded frame width/height | |
| 127 | sfcParams.input.width = m_downSampling->m_inputSurface->dwWidth; | |
| 128 | sfcParams.input.height = m_downSampling->m_inputSurface->dwHeight; | |
| 129 | // x + width/ y + height is the right/bottom padding boundary of SFC input, which may be smaller than frame width/height. | |
| 130 | sfcParams.input.effectiveWidth = m_downSampling->m_inputSurfaceRegion.m_x + | |
| 131 | m_downSampling->m_inputSurfaceRegion.m_width; | |
| 132 | sfcParams.input.effectiveHeight = m_downSampling->m_inputSurfaceRegion.m_y + | |
| 133 | m_downSampling->m_inputSurfaceRegion.m_height; | |
| 134 | sfcParams.input.format = m_downSampling->m_inputSurface->Format; | |
| 135 | sfcParams.input.colorSpace = CSpace_Any; | |
| 136 | sfcParams.input.chromaSiting = m_downSampling->m_chromaSitingType; | |
| 137 | sfcParams.input.mirrorEnabled = (m_downSampling->m_mirrorState != 0); | |
| 135 | 138 | |
| 136 | sfcParams.output.surface = &(m_downSampling->m_outputSurface); | |
| 137 | sfcParams.output.colorSpace = CSpace_Any; | |
| 138 | sfcParams.output.chromaSiting = m_downSampling->m_chromaSitingType; | |
| 139 | sfcParams.output.rcDst.left = m_downSampling->m_outputSurfaceRegion.m_x; | |
| 140 | sfcParams.output.rcDst.top = m_downSampling->m_outputSurfaceRegion.m_y; | |
| 141 | sfcParams.output.rcDst.right = m_downSampling->m_outputSurfaceRegion.m_x + | |
| 142 | m_downSampling->m_outputSurfaceRegion.m_width; | |
| 143 | sfcParams.output.rcDst.bottom = m_downSampling->m_outputSurfaceRegion.m_y + | |
| 144 | m_downSampling->m_outputSurfaceRegion.m_height; | |
| 139 | sfcParams.output.surface = &(m_downSampling->m_outputSurface); | |
| 140 | sfcParams.output.colorSpace = CSpace_Any; | |
| 141 | sfcParams.output.chromaSiting = m_downSampling->m_chromaSitingType; | |
| 142 | sfcParams.output.rcDst.left = m_downSampling->m_outputSurfaceRegion.m_x; | |
| 143 | sfcParams.output.rcDst.top = m_downSampling->m_outputSurfaceRegion.m_y; | |
| 144 | sfcParams.output.rcDst.right = m_downSampling->m_outputSurfaceRegion.m_x + | |
| 145 | m_downSampling->m_outputSurfaceRegion.m_width; | |
| 146 | sfcParams.output.rcDst.bottom = m_downSampling->m_outputSurfaceRegion.m_y + | |
| 147 | m_downSampling->m_outputSurfaceRegion.m_height; | |
| 145 | 148 | |
| 146 | 149 | sfcParams.videoParams.codecStandard = m_basicFeature->m_standard; |
| 147 | 150 | sfcParams.scalingMode = m_downSampling->m_scalingMode; |
| 31 | 31 | #include "media_pipeline.h" |
| 32 | 32 | #include "codechal_hw.h" |
| 33 | 33 | #include "decode_utils.h" |
| 34 | #include "decode_huc_copy_packet_itf.h" | |
| 34 | 35 | |
| 35 | 36 | namespace decode |
| 36 | 37 | { |
| 37 | class HucCopyPkt : public DecodeHucBasic_G12_Base | |
| 38 | class HucCopyPkt : public DecodeHucBasic_G12_Base, public HucCopyPktItf | |
| 38 | 39 | { |
| 39 | 40 | public: |
| 40 | struct HucCopyParams | |
| 41 | { | |
| 42 | PMOS_RESOURCE srcBuffer; | |
| 43 | uint32_t srcOffset; | |
| 44 | PMOS_RESOURCE destBuffer; | |
| 45 | uint32_t destOffset; | |
| 46 | uint32_t copyLength; | |
| 47 | }; | |
| 48 | 41 | |
| 49 | 42 | HucCopyPkt(MediaPipeline *pipeline, MediaTask *task, CodechalHwInterface *hwInterface) |
| 50 | 43 | : DecodeHucBasic_G12_Base(pipeline, task, hwInterface) |
| 53 | 46 | |
| 54 | 47 | virtual ~HucCopyPkt() { m_copyParamsList.clear(); } |
| 55 | 48 | |
| 56 | virtual MOS_STATUS PushCopyParams(HucCopyParams ©Params); | |
| 49 | virtual MOS_STATUS PushCopyParams(HucCopyParams ©Params) override; | |
| 57 | 50 | |
| 58 | 51 | MOS_STATUS Submit(MOS_COMMAND_BUFFER *commandBuffer, uint8_t packetPhase = otherPacket) override; |
| 59 | 52 | |
+9
-4
| 28 | 28 | #include "decode_pipeline.h" |
| 29 | 29 | #include "decode_common_feature_defs.h" |
| 30 | 30 | #include "decode_sfc_histogram_postsubpipeline.h" |
| 31 | #include "decode_huc_packet_creator_base.h" | |
| 31 | 32 | |
| 32 | 33 | #ifdef _DECODE_PROCESSING_SUPPORTED |
| 33 | 34 | |
| 62 | 63 | DecodeFeatureIDs::decodeDownSampling)); |
| 63 | 64 | |
| 64 | 65 | //Create Packets |
| 65 | m_copyPkt = MOS_New(HucCopyPkt, m_pipeline, m_task, hwInterface); | |
| 66 | HucPacketCreatorBase *hucPktCreator = dynamic_cast<HucPacketCreatorBase *>(m_pipeline); | |
| 67 | DECODE_CHK_NULL(hucPktCreator); | |
| 68 | m_copyPkt = hucPktCreator->CreateHucCopyPkt(m_pipeline, m_task, hwInterface); | |
| 66 | 69 | DECODE_CHK_NULL(m_copyPkt); |
| 67 | DECODE_CHK_STATUS(RegisterPacket(DecodePacketId(m_pipeline, hucCopyPacketId), *m_copyPkt)); | |
| 68 | DECODE_CHK_STATUS(m_copyPkt->Init()); | |
| 70 | MediaPacket *packet = dynamic_cast<MediaPacket *>(m_copyPkt); | |
| 71 | DECODE_CHK_NULL(packet); | |
| 72 | DECODE_CHK_STATUS(RegisterPacket(DecodePacketId(m_pipeline, hucCopyPacketId), *packet)); | |
| 73 | DECODE_CHK_STATUS(packet->Init()); | |
| 69 | 74 | |
| 70 | 75 | return MOS_STATUS_SUCCESS; |
| 71 | 76 | } |
| 131 | 136 | |
| 132 | 137 | DECODE_CHK_STATUS(ActivatePacket(DecodePacketId(m_pipeline, hucCopyPacketId), true, 0, 0)); |
| 133 | 138 | |
| 134 | HucCopyPkt::HucCopyParams copyParams; | |
| 139 | HucCopyPktItf::HucCopyParams copyParams; | |
| 135 | 140 | copyParams.srcBuffer = src; |
| 136 | 141 | copyParams.srcOffset = 0; |
| 137 | 142 | copyParams.destBuffer = dest; |
+2
-2
| 29 | 29 | |
| 30 | 30 | #include "decode_sub_pipeline.h" |
| 31 | 31 | #include "decode_basic_feature.h" |
| 32 | #include "decode_huc_copy_packet.h" | |
| 32 | #include "decode_huc_copy_packet_itf.h" | |
| 33 | 33 | #include "decode_downsampling_feature.h" |
| 34 | 34 | |
| 35 | 35 | #ifdef _DECODE_PROCESSING_SUPPORTED |
| 102 | 102 | private: |
| 103 | 103 | DecodeBasicFeature* m_basicFeature = nullptr; //!< Decode basic feature |
| 104 | 104 | DecodeAllocator* m_allocator = nullptr; //!< Resource allocator |
| 105 | HucCopyPkt * m_copyPkt = nullptr; //!< Bitstream concat packet | |
| 105 | HucCopyPktItf * m_copyPkt = nullptr; //!< Bitstream concat packet | |
| 106 | 106 | PMOS_INTERFACE m_osInterface = nullptr; //!< MOS interface |
| 107 | 107 | DecodeDownSamplingFeature* m_downsampFeature = nullptr; //!< Downsampling feature |
| 108 | 108 | }; |
| 17 | 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 18 | 18 | # OTHER DEALINGS IN THE SOFTWARE. |
| 19 | 19 | |
| 20 | set(TMP_HEADERS_ | |
| 21 | ${CMAKE_CURRENT_LIST_DIR}/codechal_setting.h | |
| 22 | ${CMAKE_CURRENT_LIST_DIR}/codechal_common.h | |
| 23 | ) | |
| 24 | ||
| 25 | set(TMP_1_SOURCES_ | |
| 26 | ${CMAKE_CURRENT_LIST_DIR}/codechal_common.cpp | |
| 27 | ) | |
| 28 | ||
| 29 | if(NOT "${Media_Reserved}" STREQUAL "yes") | |
| 30 | set(TMP_1_SOURCES_ | |
| 31 | ${TMP_1_SOURCES_} | |
| 32 | ${CMAKE_CURRENT_LIST_DIR}/codechal_setting.cpp | |
| 33 | ) | |
| 34 | endif() | |
| 35 | ||
| 36 | set(SOURCES_ | |
| 37 | ${SOURCES_} | |
| 38 | ${TMP_1_SOURCES_} | |
| 39 | ) | |
| 40 | ||
| 41 | set(HEADERS_ | |
| 42 | ${HEADERS_} | |
| 43 | ${TMP_HEADERS_} | |
| 44 | ) | |
| 45 | ||
| 46 | set(COMMON_HEADERS_ | |
| 47 | ${COMMON_HEADERS_} | |
| 48 | ${TMP_HEADERS_} | |
| 49 | ) | |
| 50 | ||
| 51 | set(COMMON_SOURCES_ | |
| 52 | ${COMMON_SOURCES_} | |
| 53 | ${TMP_1_SOURCES_} | |
| 54 | ) | |
| 55 | ||
| 56 | source_group( "CodecHal\\Common" FILES ${TMP_1_SOURCES_} ${TMP_HEADERS_} ) | |
| 57 | ||
| 58 | media_add_curr_to_include_path() | |
| 59 | ||
| 20 | 60 | media_include_subdirectory(dec) |
| 21 | 61 | media_include_subdirectory(enc) |
| 28 | 28 | #define __MHW_CMDPAR_H__ |
| 29 | 29 | |
| 30 | 30 | #include <memory> |
| 31 | #include "mhw_utilities.h" | |
| 32 | 31 | |
| 33 | 32 | // [Macro Prefixes] | [Macro Suffixes] |
| 34 | 33 | // No Prefix: for external use | _T : type |
| 28 | 28 | #define __MHW_IMPL_H__ |
| 29 | 29 | |
| 30 | 30 | #include "mhw_itf.h" |
| 31 | #include "mhw_utilities.h" | |
| 31 | 32 | |
| 32 | 33 | // [Macro Prefixes] | [Macro Suffixes] |
| 33 | 34 | // No Prefix: for external use | _T : type |
| 29 | 29 | |
| 30 | 30 | #include "mhw_itf.h" |
| 31 | 31 | #include "mhw_vdbox_vdenc_cmdpar.h" |
| 32 | #include "mhw_utilities.h" | |
| 32 | 33 | |
| 33 | 34 | #define _VDENC_CMD_DEF(DEF) \ |
| 34 | 35 | DEF(VDENC_CONTROL_STATE); \ |
| 0 | # Copyright (c) 2019, Intel Corporation | |
| 0 | # Copyright (c) 2019-2021, Intel Corporation | |
| 1 | 1 | # |
| 2 | 2 | # Permission is hereby granted, free of charge, to any person obtaining a |
| 3 | 3 | # copy of this software and associated documentation files (the "Software"), |
| 23 | 23 | media_include_subdirectory(cp) |
| 24 | 24 | media_include_subdirectory(codec) |
| 25 | 25 | media_include_subdirectory(hw) |
| 26 | media_include_subdirectory(renderhal) | |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | set(TMP_SOURCES_ | |
| 21 | ) | |
| 22 | ||
| 23 | set(TMP_HEADERS | |
| 24 | ${CMAKE_CURRENT_LIST_DIR}/renderhal_platform_interface_next.h | |
| 25 | ) | |
| 26 | ||
| 27 | ||
| 28 | set(SOURCES_ | |
| 29 | ${SOURCES_} | |
| 30 | ${TMP_SOURCES_} | |
| 31 | ) | |
| 32 | ||
| 33 | set(HEADERS_ | |
| 34 | ${HEADERS_} | |
| 35 | ${TMP_HEADERS_} | |
| 36 | ) | |
| 37 | ||
| 38 | set(COMMON_SOURCES_ | |
| 39 | ${COMMON_SOURCES_} | |
| 40 | ${TMP_SOURCES_} | |
| 41 | ) | |
| 42 | ||
| 43 | set(COMMON_HEADERS_ | |
| 44 | ${COMMON_HEADERS_} | |
| 45 | ${TMP_HEADERS_} | |
| 46 | ) | |
| 47 | ||
| 48 | source_group( "MHW\\Render Hal" FILES ${TMP_SOURCES_} ${TMP_HEADERS_} ) | |
| 49 | ||
| 50 | media_add_curr_to_include_path() |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file renderhal_platform_interface_next.h | |
| 23 | //! \brief abstract the platfrom specific APIs into one class | |
| 24 | //! | |
| 25 | //! | |
| 26 | //! \file renderhal.h | |
| 27 | //! \brief Render Engine Interfaces shared across platforms | |
| 28 | //! \details Platform Independent Hardware Interfaces | |
| 29 | //! | |
| 30 | #ifndef __RENDERHAL_PLATFORM_INTERFACE_NEXT_H__ | |
| 31 | #define __RENDERHAL_PLATFORM_INTERFACE_NEXT_H__ | |
| 32 | ||
| 33 | #include "mos_os.h" | |
| 34 | #include "renderhal.h" | |
| 35 | #include "renderhal_platform_interface.h" | |
| 36 | ||
| 37 | class XRenderHal_Platform_Interface_Next : public XRenderHal_Platform_Interface | |
| 38 | { | |
| 39 | public: | |
| 40 | XRenderHal_Platform_Interface_Next() {} | |
| 41 | virtual ~XRenderHal_Platform_Interface_Next() {} | |
| 42 | ||
| 43 | }; | |
| 44 | ||
| 45 | #endif // __RENDERHAL_PLATFORM_INTERFACE_NEXT_H__ |
| 34 | 34 | public: |
| 35 | 35 | typedef T *Type; |
| 36 | 36 | typedef Type (*Creator)(); |
| 37 | typedef Type (*PlaceCreator)(void *); | |
| 37 | 38 | typedef std::map<KeyType, Creator> Creators; |
| 39 | typedef std::map<KeyType, PlaceCreator> PlaceCreators; | |
| 40 | typedef std::map<KeyType, uint32_t> Sizes; | |
| 38 | 41 | typedef typename Creators::iterator Iterator; |
| 42 | typedef typename Sizes::iterator Iterator_Sizes; | |
| 43 | typedef typename PlaceCreators::iterator Iterator_PlaceCreators; | |
| 39 | 44 | |
| 40 | 45 | //! |
| 41 | 46 | //! \brief register one Class C with key. |
| 56 | 61 | static bool Register(KeyType key, bool forceReplace = false) |
| 57 | 62 | { |
| 58 | 63 | Creators &creators = GetCreators(); |
| 64 | Sizes &sizes = GetSizes(); | |
| 65 | PlaceCreators &placecreators = GetPlaceCreators(); | |
| 59 | 66 | Iterator creator = creators.find(key); |
| 60 | 67 | if (creator == creators.end()) |
| 61 | 68 | { |
| 62 | 69 | std::pair<Iterator, bool> result = |
| 63 | 70 | creators.insert(std::make_pair(key, Create<C>)); |
| 71 | sizes.insert(std::make_pair(key, sizeof(C))); | |
| 72 | placecreators.insert(std::make_pair(key, PlaceCreate<C>)); | |
| 64 | 73 | return result.second; |
| 65 | 74 | } |
| 66 | 75 | else |
| 100 | 109 | return nullptr; |
| 101 | 110 | } |
| 102 | 111 | |
| 112 | static Type PlaceCreate( | |
| 113 | KeyType key, void* privateData) | |
| 114 | { | |
| 115 | PlaceCreators &placecreators = GetPlaceCreators(); | |
| 116 | Iterator_PlaceCreators placecreator = placecreators.find(key); | |
| 117 | if (placecreator != placecreators.end()) | |
| 118 | { | |
| 119 | return (placecreator->second)(privateData); | |
| 120 | }; | |
| 121 | ||
| 122 | return nullptr; | |
| 123 | } | |
| 124 | ||
| 125 | static uint32_t ReturnClassSize(KeyType key) | |
| 126 | { | |
| 127 | Sizes &sizes = GetSizes(); | |
| 128 | Iterator_Sizes sizeit = sizes.find(key); | |
| 129 | if (sizeit != sizes.end()) | |
| 130 | { | |
| 131 | return sizeit->second; | |
| 132 | } | |
| 133 | ||
| 134 | return 0; | |
| 135 | } | |
| 103 | 136 | //! |
| 104 | 137 | //! \brief check object that is registered with key. |
| 105 | 138 | //! \details check object that is registered with key. And Args is passed to check the object. |
| 134 | 167 | return MOS_New(C); |
| 135 | 168 | } |
| 136 | 169 | |
| 170 | template <class C> | |
| 171 | static Type PlaceCreate(void *privateData) | |
| 172 | { | |
| 173 | // The factory only provide the method to create but not keep the pointer to the memory. | |
| 174 | // So the memory free is owned by who call the factory to create it. | |
| 175 | return new (privateData)C; | |
| 176 | } | |
| 137 | 177 | |
| 138 | 178 | //! |
| 139 | 179 | //! \brief obtain the static pair table of param@ key and callback function |
| 147 | 187 | |
| 148 | 188 | return creators; |
| 149 | 189 | } |
| 190 | ||
| 191 | static PlaceCreators &GetPlaceCreators() | |
| 192 | { | |
| 193 | static PlaceCreators placecreators; | |
| 194 | ||
| 195 | return placecreators; | |
| 196 | } | |
| 197 | ||
| 198 | static Sizes &GetSizes() | |
| 199 | { | |
| 200 | static Sizes sizes; | |
| 201 | ||
| 202 | return sizes; | |
| 203 | } | |
| 204 | ||
| 205 | ||
| 150 | 206 | }; |
| 151 | 207 | #endif |
| 119 | 119 | //!< be smaller than frame width. |
| 120 | 120 | uint32_t height; //!< Effective height of SFC input, which may |
| 121 | 121 | //!< be smaller than frame height. |
| 122 | uint32_t effectiveWidth; //!< exclude right padding area on input surface, | |
| 123 | //!< which may be smaller than Effective width. | |
| 124 | uint32_t effectiveHeight; //!< exclude bottom padding area on input surface, | |
| 125 | //!< which may be smaller than Effective height. | |
| 122 | 126 | MOS_FORMAT format; //!< Format of SFC input |
| 123 | 127 | MEDIA_CSPACE colorSpace; //!< Color Space |
| 124 | 128 | uint32_t chromaSiting; //!< ChromaSiting |
| 288 | 288 | VP_PUBLIC_CHK_NULL_RETURN(sfcParam.output.surface); |
| 289 | 289 | |
| 290 | 290 | RECT rcSrcInput = {0, 0, (int32_t)sfcParam.input.width, (int32_t)sfcParam.input.height }; |
| 291 | RECT rcEffectiveSrcInput = {0, 0, (int32_t)sfcParam.input.effectiveWidth, (int32_t)sfcParam.input.effectiveHeight }; | |
| 291 | 292 | RECT rcOutput = {0, 0, (int32_t)sfcParam.output.surface->dwWidth, (int32_t)sfcParam.output.surface->dwHeight }; |
| 292 | 293 | |
| 293 | 294 | scalingParams.type = FeatureTypeScalingOnSfc; |
| 296 | 297 | scalingParams.scalingMode = VPHAL_SCALING_AVS; |
| 297 | 298 | scalingParams.scalingPreference = VPHAL_SCALING_PREFER_SFC; //!< DDI indicate Scaling preference |
| 298 | 299 | scalingParams.bDirectionalScalar = false; //!< Vebox Directional Scalar |
| 299 | scalingParams.input.rcSrc = rcSrcInput; //!< No input crop support for VD mode. rcSrcInput must have same width/height of input image. | |
| 300 | scalingParams.input.rcSrc = rcEffectiveSrcInput; //!< rcEffectiveSrcInput exclude right/bottom padding area of SFC input. | |
| 300 | 301 | scalingParams.input.rcDst = sfcParam.output.rcDst; |
| 301 | 302 | scalingParams.input.rcMaxSrc = rcSrcInput; |
| 302 | scalingParams.input.dwWidth = sfcParam.input.width; | |
| 303 | scalingParams.input.dwWidth = sfcParam.input.width; //!< No input crop support for VD mode. Input Frame Height/Width must have same width/height of decoded frames. | |
| 303 | 304 | scalingParams.input.dwHeight = sfcParam.input.height; |
| 304 | 305 | scalingParams.output.rcSrc = rcOutput; |
| 305 | 306 | scalingParams.output.rcDst = rcOutput; |
| 120 | 120 | VP_PUBLIC_CHK_NULL_RETURN(m_scalingFilter); |
| 121 | 121 | |
| 122 | 122 | RECT rcSrcInput = {0, 0, (int32_t)sfcParam.input.width, (int32_t)sfcParam.input.height }; |
| 123 | RECT rcEffectiveSrcInput = {0, 0, (int32_t)sfcParam.input.effectiveWidth, (int32_t)sfcParam.input.effectiveHeight }; | |
| 123 | 124 | RECT rcOutput = {0, 0, (int32_t)sfcParam.output.surface->dwWidth, (int32_t)sfcParam.output.surface->dwHeight }; |
| 124 | 125 | FeatureParamScaling scalingParams = {}; |
| 125 | 126 | scalingParams.type = FeatureTypeScalingOnSfc; |
| 128 | 129 | scalingParams.scalingMode = GetScalingMode(sfcParam.scalingMode); |
| 129 | 130 | scalingParams.scalingPreference = VPHAL_SCALING_PREFER_SFC; //!< DDI indicate Scaling preference |
| 130 | 131 | scalingParams.bDirectionalScalar = false; //!< Vebox Directional Scalar |
| 131 | scalingParams.input.rcSrc = rcSrcInput; //!< No input crop support for VD mode. rcSrcInput must have same width/height of input image. | |
| 132 | scalingParams.input.rcSrc = rcEffectiveSrcInput; //!< rcEffectiveSrcInput exclude right/bottom padding area of SFC input. | |
| 132 | 133 | scalingParams.input.rcDst = sfcParam.output.rcDst; |
| 133 | 134 | scalingParams.input.rcMaxSrc = rcSrcInput; |
| 134 | scalingParams.input.dwWidth = sfcParam.input.width; | |
| 135 | scalingParams.input.dwWidth = sfcParam.input.width; //!< No input crop support for VD mode. Input Frame Height/Width must have same width/height of decoded frames. | |
| 135 | 136 | scalingParams.input.dwHeight = sfcParam.input.height; |
| 136 | 137 | scalingParams.output.rcSrc = rcOutput; |
| 137 | 138 | scalingParams.output.rcDst = rcOutput; |
| 666 | 666 | |
| 667 | 667 | MOS_ZeroMemory(&RenderHalSurface, sizeof(RenderHalSurface)); |
| 668 | 668 | |
| 669 | // not support CP yet | |
| 670 | if (m_osInterface->osCpInterface->IsHMEnabled()) | |
| 671 | { | |
| 672 | RENDER_PACKET_ASSERTMESSAGE("ERROR, need to use VpHal_CommonSetBufferSurfaceForHwAccess if under CP HM."); | |
| 673 | } | |
| 674 | ||
| 675 | 669 | // Register surfaces for rendering (GfxAddress/Allocation index) |
| 676 | 670 | // Register resource |
| 677 | 671 | RENDER_PACKET_CHK_STATUS_RETURN(m_osInterface->pfnRegisterResource( |
| 223 | 223 | //! |
| 224 | 224 | virtual MOS_STATUS CreateMediaCopy(); |
| 225 | 225 | |
| 226 | //! | |
| 227 | //! \brief media user setting | |
| 228 | //! \return MOS_STATUS | |
| 229 | //! MOS_STATUS_SUCCESS if success, else fail reason | |
| 230 | //! | |
| 231 | virtual MOS_STATUS InitUserSetting(); | |
| 232 | ||
| 226 | 233 | protected: |
| 227 | 234 | PMOS_INTERFACE m_osInterface = nullptr; //!< OS interface |
| 228 | 235 | CodechalDebugInterface *m_debugInterface = nullptr; //!< Interface used for debug dumps |
| 20 | 20 | set(TMP_SOURCES_ |
| 21 | 21 | ${TMP_SOURCES_} |
| 22 | 22 | ${CMAKE_CURRENT_LIST_DIR}/media_pipeline.cpp |
| 23 | ${CMAKE_CURRENT_LIST_DIR}/media_user_setting.cpp | |
| 23 | 24 | ) |
| 24 | 25 | |
| 25 | 26 | set(TMP_HEADERS_ |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file media_user_setting.cpp | |
| 23 | //! \brief Initialize user setting of media | |
| 24 | //! | |
| 25 | #include "media_pipeline.h" | |
| 26 | MOS_STATUS MediaPipeline::InitUserSetting() | |
| 27 | { | |
| 28 | DeclareUserSettingKey( | |
| 29 | "Lockable Resource", | |
| 30 | MediaUserSetting::Group::Sequence, | |
| 31 | (int32_t)0, | |
| 32 | false); | |
| 33 | DeclareUserSettingKey( | |
| 34 | "Enable Codec MMC", | |
| 35 | MediaUserSetting::Group::Sequence, | |
| 36 | int32_t(0), | |
| 37 | false); | |
| 38 | #if (_DEBUG || _RELEASE_INTERNAL) | |
| 39 | DeclareUserSettingKeyForDebug( | |
| 40 | "Simulation In Use", | |
| 41 | MediaUserSetting::Group::Sequence, | |
| 42 | int32_t(0), | |
| 43 | true); | |
| 44 | #endif | |
| 45 | return MOS_STATUS_SUCCESS; | |
| 46 | } |
| 210 | 210 | virtual MOS_STATUS ResetSemaphore(uint32_t syncType, uint32_t semaphoreId, PMOS_COMMAND_BUFFER cmdBuffer) = 0; |
| 211 | 211 | |
| 212 | 212 | //! |
| 213 | //! \brief Oca 1st Level BB Start | |
| 214 | //! \param [in, out] cmdBuffer | |
| 215 | //! Reference to command buffer | |
| 216 | //! \return MOS_STATUS | |
| 217 | //! MOS_STATUS_SUCCESS if success, else fail reason | |
| 218 | //! | |
| 219 | virtual MOS_STATUS Oca1stLevelBBStart(MOS_COMMAND_BUFFER &cmdBuffer) { return MOS_STATUS_SUCCESS; }; | |
| 220 | ||
| 221 | //! | |
| 222 | //! \brief Oca 1st Level BB End | |
| 223 | //! \param [in, out] cmdBuffer | |
| 224 | //! Reference to command buffer | |
| 225 | //! \return MOS_STATUS | |
| 226 | //! MOS_STATUS_SUCCESS if success, else fail reason | |
| 227 | //! | |
| 228 | virtual MOS_STATUS Oca1stLevelBBEnd(MOS_COMMAND_BUFFER &cmdBuffer) { return MOS_STATUS_SUCCESS; }; | |
| 229 | ||
| 230 | //! | |
| 213 | 231 | //! \brief Get pipe number |
| 214 | 232 | //! \return Pipe number |
| 215 | 233 | //! |
| 31 | 31 | #include "media_scalability_defs.h" |
| 32 | 32 | #include "media_scalability_singlepipe.h" |
| 33 | 33 | #include "mhw_mi.h" |
| 34 | #include "hal_oca_interface.h" | |
| 34 | 35 | |
| 35 | 36 | MediaScalabilitySinglePipe::MediaScalabilitySinglePipe(void *hwInterface, MediaContext *mediaContext, uint8_t componentType) : |
| 36 | 37 | MediaScalability(mediaContext) |
| 240 | 241 | |
| 241 | 242 | SCALABILITY_CHK_STATUS_RETURN(GetCmdBuffer(cmdBuffer)); |
| 242 | 243 | SCALABILITY_CHK_STATUS_RETURN(m_miInterface->AddMiBatchBufferEnd(cmdBuffer, nullptr)); |
| 244 | ||
| 245 | SCALABILITY_CHK_STATUS_RETURN(Oca1stLevelBBEnd(*cmdBuffer)); | |
| 246 | ||
| 243 | 247 | SCALABILITY_CHK_STATUS_RETURN(ReturnCmdBuffer(cmdBuffer)); |
| 244 | 248 | |
| 245 | 249 | if (MOS_VE_SUPPORTED(m_osInterface)) |
| 104 | 104 | |
| 105 | 105 | MEDIA_CHK_STATUS_RETURN(scalability->GetCmdBuffer(&cmdBuffer, prop.frameTrackingRequested)); |
| 106 | 106 | //Set first packet for each pipe in the first pass, used for prolog & forcewakeup insertion |
| 107 | if (scalability->GetCurrentPass() == 0 && curPipe < scalability->GetCurrentPipe()) | |
| 107 | bool isFirstPacket = scalability->GetCurrentPass() == 0 && curPipe < scalability->GetCurrentPipe(); | |
| 108 | if (isFirstPacket) | |
| 108 | 109 | { |
| 109 | 110 | packetPhase = MediaPacket::firstPacket; |
| 111 | } | |
| 112 | ||
| 113 | if (isFirstPacket || !prop.stateProperty.singleTaskPhaseSupported) | |
| 114 | { | |
| 115 | scalability->Oca1stLevelBBStart(cmdBuffer); | |
| 110 | 116 | } |
| 111 | 117 | |
| 112 | 118 | curPipe = scalability->GetCurrentPipe(); |
| 195 | 195 | if (nullptr == surface->osSurface) |
| 196 | 196 | { |
| 197 | 197 | MOS_Delete(surface); |
| 198 | MT_ERR1(MT_GRAPHIC_ALLOC_ERR, MT_CODE_LINE, __LINE__); | |
| 198 | 199 | return nullptr; |
| 199 | 200 | } |
| 200 | 201 | |
| 822 | 823 | surface = AllocateVpSurface(allocParams, zeroOnAllocate); |
| 823 | 824 | VP_PUBLIC_CHK_NULL_RETURN(surface); |
| 824 | 825 | |
| 826 | MT_LOG7(MT_VP_HAL_REALLOC_SURF, MT_NORMAL, MT_VP_INTERNAL_SURF_TYPE, surfaceName ? *((int64_t*)surfaceName) : 0, | |
| 827 | MT_SURF_WIDTH, width, MT_SURF_HEIGHT, height, MT_SURF_MOS_FORMAT, format, MT_SURF_TILE_TYPE, surface->osSurface->TileModeGMM, | |
| 828 | MT_SURF_COMP_ABLE, surface->osSurface->bCompressible, MT_SURF_COMP_MODE, surface->osSurface->CompressionMode); | |
| 829 | ||
| 825 | 830 | allocated = true; |
| 826 | 831 | return MOS_STATUS_SUCCESS; |
| 827 | 832 | } |
| 758 | 758 | // Report Compress Status |
| 759 | 759 | if (m_veboxOutput[0]->osSurface) |
| 760 | 760 | { |
| 761 | m_reporting.FFDICompressible = m_veboxOutput[0]->osSurface->bIsCompressed; | |
| 762 | m_reporting.FFDICompressMode = (uint8_t)m_veboxOutput[0]->osSurface->CompressionMode; | |
| 761 | m_reporting.GetFeatures().ffdiCompressible = m_veboxOutput[0]->osSurface->bIsCompressed; | |
| 762 | m_reporting.GetFeatures().ffdiCompressMode = (uint8_t)m_veboxOutput[0]->osSurface->CompressionMode; | |
| 763 | 763 | } |
| 764 | 764 | } |
| 765 | 765 | |
| 866 | 866 | // Report Compress Status |
| 867 | 867 | if (m_veboxDenoiseOutput[i]->osSurface) |
| 868 | 868 | { |
| 869 | m_reporting.FFDNCompressible = m_veboxDenoiseOutput[i]->osSurface->bIsCompressed; | |
| 870 | m_reporting.FFDNCompressMode = (uint8_t)m_veboxDenoiseOutput[i]->osSurface->CompressionMode; | |
| 869 | m_reporting.GetFeatures().ffdnCompressible = m_veboxDenoiseOutput[i]->osSurface->bIsCompressed; | |
| 870 | m_reporting.GetFeatures().ffdnCompressMode = (uint8_t)m_veboxDenoiseOutput[i]->osSurface->CompressionMode; | |
| 871 | 871 | } |
| 872 | 872 | } |
| 873 | 873 | else |
| 1036 | 1036 | VP_PUBLIC_CHK_STATUS_RETURN(VeboxInitSTMMHistory(m_veboxSTMMSurface[i]->osSurface)); |
| 1037 | 1037 | } |
| 1038 | 1038 | // Report Compress Status |
| 1039 | m_reporting.STMMCompressible = bSurfCompressible; | |
| 1040 | m_reporting.STMMCompressMode = (uint8_t)surfCompressionMode; | |
| 1039 | m_reporting.GetFeatures().stmmCompressible = bSurfCompressible; | |
| 1040 | m_reporting.GetFeatures().stmmCompressMode = (uint8_t)surfCompressionMode; | |
| 1041 | 1041 | } |
| 1042 | 1042 | } |
| 1043 | 1043 | return MOS_STATUS_SUCCESS; |
| 391 | 391 | if (feature->GetFilterEngineCaps().value == 0) |
| 392 | 392 | { |
| 393 | 393 | // Return success after all feature enabled and fully switched to APO path. |
| 394 | VP_PUBLIC_ASSERTMESSAGE("No engine being assigned!"); | |
| 395 | return MOS_STATUS_INVALID_PARAMETER; | |
| 396 | } | |
| 394 | VP_PUBLIC_NORMALMESSAGE("No engine being assigned for feature %d. Will bypass it.", featureType); | |
| 395 | } | |
| 396 | ||
| 397 | 397 | return MOS_STATUS_SUCCESS; |
| 398 | 398 | } |
| 399 | 399 | |
| 1018 | 1018 | } |
| 1019 | 1019 | |
| 1020 | 1020 | if (m_hwCaps.m_veboxHwEntry[inputformat].inputSupported && |
| 1021 | m_hwCaps.m_veboxHwEntry[inputformat].iecp) | |
| 1021 | m_hwCaps.m_veboxHwEntry[inputformat].iecp && | |
| 1022 | m_hwCaps.m_veboxHwEntry[inputformat].tccSupported) | |
| 1022 | 1023 | { |
| 1023 | 1024 | tccEngine.bEnabled = 1; |
| 1024 | 1025 | tccEngine.VeboxNeeded = 1; |
| 1846 | 1847 | else |
| 1847 | 1848 | { |
| 1848 | 1849 | auto *handlers = (caps.bSFC || caps.bVebox) ? &m_VeboxSfcFeatureHandlers : &m_RenderFeatureHandlers; |
| 1849 | PolicyFeatureHandler *handler = handlers->find(feature->GetFeatureType())->second; | |
| 1850 | VP_PUBLIC_CHK_STATUS_RETURN(handler->UpdateUnusedFeature(caps, *feature, featurePipe, executedFilters, isInputPipe, executePipeIndex)); | |
| 1850 | ||
| 1851 | auto processHandler = handlers->find(feature->GetFeatureType()); | |
| 1852 | ||
| 1853 | if (processHandler != handlers->end()) | |
| 1854 | { | |
| 1855 | PolicyFeatureHandler* handler = processHandler->second; | |
| 1856 | if (handler) | |
| 1857 | { | |
| 1858 | VP_PUBLIC_CHK_STATUS_RETURN(handler->UpdateUnusedFeature(caps, *feature, featurePipe, executedFilters, isInputPipe, executePipeIndex)); | |
| 1859 | } | |
| 1860 | } | |
| 1851 | 1861 | } |
| 1852 | 1862 | |
| 1853 | 1863 | if (!engineCaps->bEnabled) |
| 84 | 84 | MOS_STATUS GetScalingExecutionCaps(SwFilter* feature); |
| 85 | 85 | bool IsSfcRotationSupported(FeatureParamRotMir *rotationParams); |
| 86 | 86 | MOS_STATUS GetRotationExecutionCaps(SwFilter* feature); |
| 87 | MOS_STATUS GetDenoiseExecutionCaps(SwFilter* feature); | |
| 87 | virtual MOS_STATUS GetDenoiseExecutionCaps(SwFilter* feature); | |
| 88 | 88 | MOS_STATUS GetSteExecutionCaps(SwFilter* feature); |
| 89 | 89 | MOS_STATUS GetTccExecutionCaps(SwFilter* feature); |
| 90 | 90 | MOS_STATUS GetProcampExecutionCaps(SwFilter* feature); |
| 80 | 80 | }VP_SFC_ENTRY_REC; |
| 81 | 81 | |
| 82 | 82 | #define VP_FF_VEBOX_FORMAT(SurfaceFormat, bInput, bOutput, _MaxResolution, _MinResolution, _HorizUnit, _VertUnit, _HdrSupported, _CapturePipeSupported, \ |
| 83 | _DNSupported, _DISupported, _LACESupported, _FrontCscSupported, _BackEndCscSupported, _3DLutSupported, _IecpSupported, _bHsbMode) \ | |
| 83 | _DNSupported, _DISupported, _LACESupported, _FrontCscSupported, _BackEndCscSupported, _3DLutSupported, _IecpSupported, _bHsbMode, _TCCSupported) \ | |
| 84 | 84 | { \ |
| 85 | 85 | veboxHwEntry[SurfaceFormat].inputSupported = bInput; \ |
| 86 | 86 | veboxHwEntry[SurfaceFormat].outputSupported = bOutput; \ |
| 98 | 98 | veboxHwEntry[SurfaceFormat].b3dLutSupported = _3DLutSupported; \ |
| 99 | 99 | veboxHwEntry[SurfaceFormat].iecp = _IecpSupported; \ |
| 100 | 100 | veboxHwEntry[SurfaceFormat].hsb = _bHsbMode; \ |
| 101 | veboxHwEntry[SurfaceFormat].tccSupported = _TCCSupported; \ | |
| 101 | 102 | } \ |
| 102 | 103 | |
| 103 | 104 | typedef struct VP_VEBOX_ENTRY_REC |
| 120 | 121 | bool b3dLutSupported; |
| 121 | 122 | bool iecp;// all IECP features like procamp/STD/Gamut etc |
| 122 | 123 | bool hsb;// high speed bypass mode |
| 124 | bool tccSupported; | |
| 123 | 125 | }VP_VEBOX_ENTRY_REC; |
| 124 | 126 | |
| 125 | 127 | struct VP_POLICY_RULES |
| 355 | 355 | m_executeCaps = vpExecuteCaps; |
| 356 | 356 | |
| 357 | 357 | m_scalingParams = scalingParams; |
| 358 | m_scalingParams.input.rcMaxSrc = m_scalingParams.input.rcSrc; | |
| 358 | if (!m_bVdbox) | |
| 359 | { | |
| 360 | m_scalingParams.input.rcMaxSrc = m_scalingParams.input.rcSrc; | |
| 361 | } | |
| 359 | 362 | |
| 360 | 363 | // Set Src/Dst Surface Rect |
| 361 | 364 | VP_PUBLIC_CHK_STATUS_RETURN(SetRectSurfaceAlignment(false, m_scalingParams.input.dwWidth, |
| 437 | 440 | //Set source input offset in Horizontal/vertical |
| 438 | 441 | m_sfcScalingParams->dwSourceRegionHorizontalOffset = MOS_ALIGN_CEIL((uint32_t)m_scalingParams.input.rcSrc.left, wInputWidthAlignUnit); |
| 439 | 442 | m_sfcScalingParams->dwSourceRegionVerticalOffset = MOS_ALIGN_CEIL((uint32_t)m_scalingParams.input.rcSrc.top, wInputHeightAlignUnit); |
| 443 | ||
| 444 | // Exclude padding area of the SFC input | |
| 440 | 445 | m_sfcScalingParams->dwSourceRegionHeight = MOS_ALIGN_FLOOR( |
| 441 | 446 | MOS_MIN((uint32_t)(m_scalingParams.input.rcSrc.bottom - m_scalingParams.input.rcSrc.top), m_sfcScalingParams->dwInputFrameHeight), |
| 442 | 447 | wInputHeightAlignUnit); |
| 469 | 474 | |
| 470 | 475 | m_sfcScalingParams->dwScaledRegionHeight = MOS_MIN(m_sfcScalingParams->dwScaledRegionHeight, m_sfcScalingParams->dwOutputFrameHeight); |
| 471 | 476 | m_sfcScalingParams->dwScaledRegionWidth = MOS_MIN(m_sfcScalingParams->dwScaledRegionWidth, m_sfcScalingParams->dwOutputFrameWidth); |
| 477 | ||
| 478 | if (m_bVdbox) | |
| 479 | { | |
| 480 | // In VD-to-SFC modes, scaled region should be programmed to same value as Output Frame Resolution. | |
| 481 | // Output Frame Resolution should be updated after scaled region being calculated, or scaling ratio may be incorrect. | |
| 482 | m_sfcScalingParams->dwOutputFrameHeight = m_sfcScalingParams->dwScaledRegionHeight; | |
| 483 | m_sfcScalingParams->dwOutputFrameWidth = m_sfcScalingParams->dwScaledRegionWidth; | |
| 484 | } | |
| 472 | 485 | |
| 473 | 486 | uint32_t dstInputLeftAligned = MOS_ALIGN_FLOOR((uint32_t)m_scalingParams.input.rcDst.left, wOutputWidthAlignUnit); |
| 474 | 487 | uint32_t dstInputTopAligned = MOS_ALIGN_FLOOR((uint32_t)m_scalingParams.input.rcDst.top, wOutputHeightAlignUnit); |
| 1279 | 1279 | inputPipe = (uint8_t)curPipe; |
| 1280 | 1280 | numPipe = scalability->GetPipeNumber(); |
| 1281 | 1281 | bMultipipe = (numPipe > 1) ? true : false; |
| 1282 | pVeboxInterface->SetVeboxIndex(0, numPipe, m_IsSfcUsed); | |
| 1282 | 1283 | |
| 1283 | 1284 | bDiVarianceEnable = m_PacketCaps.bDI; |
| 1284 | 1285 |
| 21 | 21 | ${CMAKE_CURRENT_LIST_DIR}/vp_pipeline.cpp |
| 22 | 22 | ${CMAKE_CURRENT_LIST_DIR}/vp_pipeline_adapter.cpp |
| 23 | 23 | ${CMAKE_CURRENT_LIST_DIR}/vp_pipeline_adapter_base.cpp |
| 24 | ${CMAKE_CURRENT_LIST_DIR}/vp_feature_report.cpp | |
| 24 | 25 | ) |
| 25 | 26 | |
| 26 | 27 | set(TMP_HEADERS_ |
| 28 | 29 | ${CMAKE_CURRENT_LIST_DIR}/vp_pipeline_common.h |
| 29 | 30 | ${CMAKE_CURRENT_LIST_DIR}/vp_pipeline_adapter.h |
| 30 | 31 | ${CMAKE_CURRENT_LIST_DIR}/vp_pipeline_adapter_base.h |
| 32 | ${CMAKE_CURRENT_LIST_DIR}/vp_feature_report.h | |
| 31 | 33 | ) |
| 32 | 34 | |
| 33 | 35 | set(SOURCES_ |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file vp_feature_report.cpp | |
| 23 | //! \brief vp feature report | |
| 24 | //! \details vp feature report class inlcuding: | |
| 25 | //! features, functions | |
| 26 | //! | |
| 27 | #include "vp_feature_report.h" | |
| 28 | #include "vp_utils.h" | |
| 29 | #include "vp_pipeline_adapter_base.h" | |
| 30 | ||
| 31 | void VpFeatureReport::InitReportValue() | |
| 32 | { | |
| 33 | VP_FUNC_CALL(); | |
| 34 | ||
| 35 | m_features.iecp = false; | |
| 36 | m_features.ief = false; | |
| 37 | m_features.denoise = false; | |
| 38 | m_features.chromaDenoise = false; | |
| 39 | m_features.deinterlaceMode = VPHAL_DI_REPORT_PROGRESSIVE; | |
| 40 | m_features.scalingMode = VPHAL_SCALING_NEAREST; | |
| 41 | m_features.outputPipeMode = VPHAL_OUTPUT_PIPE_MODE_COMP; | |
| 42 | m_features.vpMMCInUse = false; | |
| 43 | m_features.rtCompressible = false; | |
| 44 | m_features.rtCompressMode = 0; | |
| 45 | m_features.ffdiCompressible = false; | |
| 46 | m_features.ffdiCompressMode = 0; | |
| 47 | m_features.ffdnCompressible = false; | |
| 48 | m_features.ffdnCompressMode = 0; | |
| 49 | m_features.stmmCompressible = false; | |
| 50 | m_features.stmmCompressMode = 0; | |
| 51 | m_features.scalerCompressible = false; | |
| 52 | m_features.scalerCompressMode = 0; | |
| 53 | m_features.primaryCompressible = false; | |
| 54 | m_features.primaryCompressMode = 0; | |
| 55 | m_features.compositionMode = VPHAL_NO_COMPOSITION; | |
| 56 | m_features.diScdMode = false; | |
| 57 | m_features.veFeatureInUse = false; | |
| 58 | m_features.hdrMode = VPHAL_HDR_MODE_NONE; | |
| 59 | ||
| 60 | return; | |
| 61 | } | |
| 62 | ||
| 63 | void VpFeatureReport::SetConfigValues( | |
| 64 | PVP_CONFIG configValues, | |
| 65 | uint32_t &laceInUse) | |
| 66 | { | |
| 67 | VP_FUNC_CALL(); | |
| 68 | ||
| 69 | // Report DI mode | |
| 70 | switch (m_features.deinterlaceMode) | |
| 71 | { | |
| 72 | case VPHAL_DI_REPORT_BOB: | |
| 73 | case VPHAL_DI_REPORT_ADI_BOB: | |
| 74 | configValues->dwCurrentDeinterlaceMode = VPDDI_BOB; | |
| 75 | break; | |
| 76 | case VPHAL_DI_REPORT_ADI: | |
| 77 | case VPHAL_DI_REPORT_FMD: | |
| 78 | configValues->dwCurrentDeinterlaceMode = VPDDI_ADI; | |
| 79 | break; | |
| 80 | case VPHAL_DI_REPORT_PROGRESSIVE: | |
| 81 | default: | |
| 82 | configValues->dwCurrentDeinterlaceMode = VPDDI_PROGRESSIVE; | |
| 83 | break; | |
| 84 | } | |
| 85 | ||
| 86 | // Report Scaling mode | |
| 87 | configValues->dwCurrentScalingMode = (m_features.scalingMode == VPHAL_SCALING_AVS) ? VPDDI_ADVANCEDSCALING : (m_features.scalingMode > VPHAL_SCALING_AVS) ? VPDDI_SUPERRESOLUTIONSCALING : VPDDI_SCALING; | |
| 88 | ||
| 89 | // Report Output Pipe | |
| 90 | configValues->dwCurrentOutputPipeMode = m_features.outputPipeMode; | |
| 91 | ||
| 92 | // Report VE Feature In Use | |
| 93 | configValues->dwCurrentVEFeatureInUse = m_features.veFeatureInUse; | |
| 94 | ||
| 95 | // Report MMC status | |
| 96 | configValues->dwVPMMCInUse = m_features.vpMMCInUse; | |
| 97 | configValues->dwRTCompressible = m_features.rtCompressible; | |
| 98 | configValues->dwRTCompressMode = m_features.rtCompressMode; | |
| 99 | configValues->dwFFDICompressible = m_features.ffdiCompressible; | |
| 100 | configValues->dwFFDICompressMode = m_features.ffdiCompressMode; | |
| 101 | configValues->dwFFDNCompressible = m_features.ffdnCompressible; | |
| 102 | configValues->dwFFDNCompressMode = m_features.ffdnCompressMode; | |
| 103 | configValues->dwSTMMCompressible = m_features.stmmCompressible; | |
| 104 | configValues->dwSTMMCompressMode = m_features.stmmCompressMode; | |
| 105 | configValues->dwScalerCompressible = m_features.scalerCompressible; | |
| 106 | configValues->dwScalerCompressMode = m_features.scalerCompressMode; | |
| 107 | configValues->dwPrimaryCompressible = m_features.primaryCompressible; | |
| 108 | configValues->dwPrimaryCompressMode = m_features.primaryCompressMode; | |
| 109 | ||
| 110 | // Report In Place Compositon status | |
| 111 | configValues->dwCurrentCompositionMode = m_features.compositionMode; | |
| 112 | configValues->dwCurrentScdMode = m_features.diScdMode; | |
| 113 | ||
| 114 | VP_PUBLIC_NORMALMESSAGE( | |
| 115 | "VP Feature Report: \ | |
| 116 | OutputPipeMode %d, \ | |
| 117 | VEFeatureInUse %d, \ | |
| 118 | ScalingMode %d, \ | |
| 119 | DeinterlaceMode %d, \ | |
| 120 | VPMMCInUse %d, \ | |
| 121 | RTCompressible %d, \ | |
| 122 | RTCompressMode %d, \ | |
| 123 | PrimaryCompressible %d, \ | |
| 124 | PrimaryCompressMode %d, \ | |
| 125 | CompositionMode %d", | |
| 126 | m_features.outputPipeMode, | |
| 127 | m_features.veFeatureInUse, | |
| 128 | m_features.scalingMode, | |
| 129 | m_features.deinterlaceMode, | |
| 130 | m_features.vpMMCInUse, | |
| 131 | m_features.rtCompressible, | |
| 132 | m_features.rtCompressMode, | |
| 133 | m_features.primaryCompressible, | |
| 134 | m_features.primaryCompressMode, | |
| 135 | m_features.compositionMode); | |
| 136 | ||
| 137 | return; | |
| 138 | } |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file vp_feature_report.h | |
| 23 | //! \brief vp feature report | |
| 24 | //! \details vp feature report class inlcuding: | |
| 25 | //! features, functions | |
| 26 | //! | |
| 27 | ||
| 28 | #ifndef __VP_FEATURE_REPORT_H__ | |
| 29 | #define __VP_FEATURE_REPORT_H__ | |
| 30 | ||
| 31 | #include "vphal_common.h" | |
| 32 | #include "vphal_common_tools.h" | |
| 33 | ||
| 34 | //! | |
| 35 | //! Class VphalFeatureReport | |
| 36 | //! \brief Vphal Feature Report Class | |
| 37 | //! | |
| 38 | class VpFeatureReport | |
| 39 | { | |
| 40 | public: | |
| 41 | struct VP_FEATURES | |
| 42 | { | |
| 43 | bool iecp = false; //!< IECP enable/disable | |
| 44 | bool ief = false; //!< Enhancement filter | |
| 45 | bool denoise = false; //!< Denoise | |
| 46 | bool chromaDenoise = false; //!< Chroma Denoise | |
| 47 | VPHAL_DI_REPORT_MODE deinterlaceMode = VPHAL_DI_REPORT_PROGRESSIVE; //!< Deinterlace mode | |
| 48 | VPHAL_SCALING_MODE scalingMode = VPHAL_SCALING_NEAREST; //!< Scaling mode | |
| 49 | VPHAL_OUTPUT_PIPE_MODE outputPipeMode = VPHAL_OUTPUT_PIPE_MODE_COMP; //!< Output Pipe | |
| 50 | bool vpMMCInUse = false; //!< MMC enable flag | |
| 51 | bool rtCompressible = false; //!< RT MMC Compressible flag | |
| 52 | uint8_t rtCompressMode = 0; //!< RT MMC Compression mode | |
| 53 | bool ffdiCompressible = false; //!< FFDI MMC Compressible flag | |
| 54 | uint8_t ffdiCompressMode = 0; //!< FFDI MMC Compression mode | |
| 55 | bool ffdnCompressible = false; //!< FFDN MMC Compressible flag | |
| 56 | uint8_t ffdnCompressMode = 0; //!< FFDN MMC Compression mode | |
| 57 | bool stmmCompressible = false; //!< STMM MMC Compressible flag | |
| 58 | uint8_t stmmCompressMode = 0; //!< STMM MMC Compression mode | |
| 59 | bool scalerCompressible = false; //!< Scaler MMC Compressible flag for Gen10 | |
| 60 | uint8_t scalerCompressMode = 0; //!< Scaler MMC Compression mode for Gen10 | |
| 61 | bool primaryCompressible = false; //!< Input Primary Surface Compressible flag | |
| 62 | uint8_t primaryCompressMode = 0; //!< Input Primary Surface Compression mode | |
| 63 | VPHAL_COMPOSITION_REPORT_MODE compositionMode = VPHAL_NO_COMPOSITION; //!< Inplace/Legacy Compostion flag | |
| 64 | bool veFeatureInUse = false; //!< If any VEBOX feature is in use, excluding pure bypass for SFC | |
| 65 | bool diScdMode = false; //!< Scene change detection | |
| 66 | VPHAL_HDR_MODE hdrMode = VPHAL_HDR_MODE_NONE; //!< HDR mode | |
| 67 | }; | |
| 68 | ||
| 69 | virtual ~VpFeatureReport(){}; | |
| 70 | ||
| 71 | //! | |
| 72 | //! \brief VphalFeatureReport Constructor | |
| 73 | //! \details Creates instance of VphalFeatureReport | |
| 74 | //! | |
| 75 | VpFeatureReport(void *owner = nullptr) | |
| 76 | { | |
| 77 | this->owner = owner; | |
| 78 | }; | |
| 79 | ||
| 80 | //! | |
| 81 | //! \brief initialize VphalFeatureReport value | |
| 82 | //! \details initialize VphalFeatureReport value, can use it to reset report value | |
| 83 | //! | |
| 84 | virtual void InitReportValue(); | |
| 85 | ||
| 86 | //! | |
| 87 | //! \brief set VphalFeatureReport value | |
| 88 | //! \details set VphalFeatureReport value | |
| 89 | //! | |
| 90 | virtual void SetConfigValues( | |
| 91 | PVP_CONFIG configValues, | |
| 92 | uint32_t &laceInUse); | |
| 93 | ||
| 94 | VP_FEATURES &GetFeatures() | |
| 95 | { | |
| 96 | return m_features; | |
| 97 | } | |
| 98 | ||
| 99 | void *owner = nullptr; //!< Pointer to object creating the report | |
| 100 | ||
| 101 | protected: | |
| 102 | VP_FEATURES m_features; | |
| 103 | }; | |
| 104 | #endif // __VP_FEATURE_REPORT_H__⏎ |
| 121 | 121 | |
| 122 | 122 | if (m_reporting) |
| 123 | 123 | { |
| 124 | m_reporting->OutputPipeMode = m_vpOutputPipe; | |
| 125 | m_reporting->VEFeatureInUse = m_veboxFeatureInuse; | |
| 124 | m_reporting->GetFeatures().outputPipeMode = m_vpOutputPipe; | |
| 125 | m_reporting->GetFeatures().veFeatureInUse = m_veboxFeatureInuse; | |
| 126 | 126 | |
| 127 | 127 | if (m_mmc) |
| 128 | 128 | { |
| 129 | m_reporting->VPMMCInUse = m_mmc->IsMmcEnabled(); | |
| 129 | m_reporting->GetFeatures().vpMMCInUse = m_mmc->IsMmcEnabled(); | |
| 130 | 130 | } |
| 131 | 131 | |
| 132 | 132 | if (PIPELINE_PARAM_TYPE_LEGACY == m_pvpParams.type) |
| 135 | 135 | VP_PUBLIC_CHK_NULL_RETURN(params); |
| 136 | 136 | if (params->pSrc[0] && params->pSrc[0]->bCompressible) |
| 137 | 137 | { |
| 138 | m_reporting->PrimaryCompressible = true; | |
| 139 | m_reporting->PrimaryCompressMode = (uint8_t)(params->pSrc[0]->CompressionMode); | |
| 138 | m_reporting->GetFeatures().primaryCompressible = true; | |
| 139 | m_reporting->GetFeatures().primaryCompressMode = (uint8_t)(params->pSrc[0]->CompressionMode); | |
| 140 | 140 | } |
| 141 | 141 | |
| 142 | 142 | if (params->pTarget[0]->bCompressible) |
| 143 | 143 | { |
| 144 | m_reporting->RTCompressible = true; | |
| 145 | m_reporting->RTCompressMode = (uint8_t)(params->pTarget[0]->CompressionMode); | |
| 144 | m_reporting->GetFeatures().rtCompressible = true; | |
| 145 | m_reporting->GetFeatures().rtCompressMode = (uint8_t)(params->pTarget[0]->CompressionMode); | |
| 146 | 146 | } |
| 147 | 147 | } |
| 148 | 148 | } |
| 246 | 246 | #if (LINUX || ANDROID) |
| 247 | 247 | dwGpuTag = pOsContext->GetGPUTag(m_pOsInterface, pStatusEntry->GpuContextOrdinal); |
| 248 | 248 | #else |
| 249 | dwGpuTag = pOsContext->GetGPUTag(pOsContext->GetGpuContextHandle(pStatusEntry->GpuContextOrdinal, m_pOsInterface->streamIndex)); | |
| 249 | dwGpuTag = m_pOsInterface->pfnGetGpuStatusSyncTag(m_pOsInterface, pStatusEntry->GpuContextOrdinal); | |
| 250 | 250 | #endif |
| 251 | 251 | bDoneByGpu = (dwGpuTag >= pStatusEntry->dwTag); |
| 252 | 252 | bFailedOnSubmitCmd = (pStatusEntry->dwStatus == VPREP_ERROR); |
| 308 | 308 | #endif // end (!EMUL && !ANDROID) |
| 309 | 309 | return eStatus; |
| 310 | 310 | } |
| 311 | ||
| 32 | 32 | #include "mhw_sfc.h" |
| 33 | 33 | #include "vp_utils.h" |
| 34 | 34 | #include "media_interfaces_mhw.h" |
| 35 | #include "vp_feature_report.h" | |
| 35 | 36 | |
| 36 | 37 | namespace vp |
| 37 | 38 | { |
| 72 | 73 | }; |
| 73 | 74 | |
| 74 | 75 | //! |
| 75 | //! Structure VphalFeatureReport | |
| 76 | //! \brief Vphal Feature Report Structure | |
| 77 | //! | |
| 78 | struct VpFeatureReport | |
| 79 | { | |
| 80 | //! | |
| 81 | //! \brief VphalFeatureReport Constructor | |
| 82 | //! \details Creates instance of VphalFeatureReport | |
| 83 | //! | |
| 84 | VpFeatureReport(void *owner = nullptr) | |
| 85 | { | |
| 86 | this->owner = owner; | |
| 87 | // call InitReportValue() to initialize report value | |
| 88 | InitReportValue(); | |
| 89 | }; | |
| 90 | ||
| 91 | //! | |
| 92 | //! \brief initialize VphalFeatureReport value | |
| 93 | //! \details initialize VphalFeatureReport value, can use it to reset report value | |
| 94 | //! | |
| 95 | void InitReportValue() | |
| 96 | { | |
| 97 | IECP = false; | |
| 98 | IEF = false; | |
| 99 | Denoise = false; | |
| 100 | ChromaDenoise = false; | |
| 101 | DeinterlaceMode = VPHAL_DI_REPORT_PROGRESSIVE; | |
| 102 | ScalingMode = VPHAL_SCALING_NEAREST; | |
| 103 | OutputPipeMode = VPHAL_OUTPUT_PIPE_MODE_COMP; | |
| 104 | VPMMCInUse = false; | |
| 105 | RTCompressible = false; | |
| 106 | RTCompressMode = 0; | |
| 107 | FFDICompressible = false; | |
| 108 | FFDICompressMode = 0; | |
| 109 | FFDNCompressible = false; | |
| 110 | FFDNCompressMode = 0; | |
| 111 | STMMCompressible = false; | |
| 112 | STMMCompressMode = 0; | |
| 113 | ScalerCompressible = false; | |
| 114 | ScalerCompressMode = 0; | |
| 115 | PrimaryCompressible = false; | |
| 116 | PrimaryCompressMode = 0; | |
| 117 | CompositionMode = VPHAL_NO_COMPOSITION; | |
| 118 | DiScdMode = false; | |
| 119 | VEFeatureInUse = false; | |
| 120 | HDRMode = VPHAL_HDR_MODE_NONE; | |
| 121 | } | |
| 122 | ||
| 123 | void * owner = nullptr; //!< Pointer to object creating the report | |
| 124 | bool IECP; //!< IECP enable/disable | |
| 125 | bool IEF; //!< Enhancement filter | |
| 126 | bool Denoise; //!< Denoise | |
| 127 | bool ChromaDenoise; //!< Chroma Denoise | |
| 128 | VPHAL_DI_REPORT_MODE DeinterlaceMode; //!< Deinterlace mode | |
| 129 | VPHAL_SCALING_MODE ScalingMode; //!< Scaling mode | |
| 130 | VPHAL_OUTPUT_PIPE_MODE OutputPipeMode; //!< Output Pipe | |
| 131 | bool VPMMCInUse; //!< MMC enable flag | |
| 132 | bool RTCompressible; //!< RT MMC Compressible flag | |
| 133 | uint8_t RTCompressMode; //!< RT MMC Compression mode | |
| 134 | bool FFDICompressible; //!< FFDI MMC Compressible flag | |
| 135 | uint8_t FFDICompressMode; //!< FFDI MMC Compression mode | |
| 136 | bool FFDNCompressible; //!< FFDN MMC Compressible flag | |
| 137 | uint8_t FFDNCompressMode; //!< FFDN MMC Compression mode | |
| 138 | bool STMMCompressible; //!< STMM MMC Compressible flag | |
| 139 | uint8_t STMMCompressMode; //!< STMM MMC Compression mode | |
| 140 | bool ScalerCompressible; //!< Scaler MMC Compressible flag for Gen10 | |
| 141 | uint8_t ScalerCompressMode; //!< Scaler MMC Compression mode for Gen10 | |
| 142 | bool PrimaryCompressible; //!< Input Primary Surface Compressible flag | |
| 143 | uint8_t PrimaryCompressMode; //!< Input Primary Surface Compression mode | |
| 144 | VPHAL_COMPOSITION_REPORT_MODE CompositionMode; //!< Inplace/Legacy Compostion flag | |
| 145 | bool VEFeatureInUse; //!< If any VEBOX feature is in use, excluding pure bypass for SFC | |
| 146 | bool DiScdMode; //!< Scene change detection | |
| 147 | VPHAL_HDR_MODE HDRMode; //!< HDR mode | |
| 148 | }; | |
| 76 | //! \brief Deinterlace Mode enum | |
| 77 | //! | |
| 78 | typedef enum | |
| 79 | { | |
| 80 | VPDDI_PROGRESSIVE = 0, //!< Progressive mode | |
| 81 | VPDDI_BOB = 1, //!< BOB DI mode | |
| 82 | VPDDI_ADI = 2 //!< ADI mode | |
| 83 | } DI_MODE; | |
| 84 | ||
| 85 | //! | |
| 86 | //! \brief Scaling Mode enum | |
| 87 | //! | |
| 88 | typedef enum | |
| 89 | { | |
| 90 | VPDDI_SCALING = 0, //!< Bilinear scaling | |
| 91 | VPDDI_ADVANCEDSCALING = 1, //!< AVS scaling | |
| 92 | VPDDI_SUPERRESOLUTIONSCALING = 2 //!< Super scaling | |
| 93 | } SCALING_MODE; | |
| 149 | 94 | |
| 150 | 95 | struct _VP_MHWINTERFACE |
| 151 | 96 | { |
| 21 | 21 | ${CMAKE_CURRENT_LIST_DIR}/vp_dumper.cpp |
| 22 | 22 | ${CMAKE_CURRENT_LIST_DIR}/vp_debug_interface.cpp |
| 23 | 23 | ${CMAKE_CURRENT_LIST_DIR}/vp_debug_config_manager.cpp |
| 24 | ${CMAKE_CURRENT_LIST_DIR}/vp_utils.cpp | |
| 24 | 25 | ) |
| 25 | 26 | |
| 26 | 27 | set(TMP_HEADERS_ |
| 1002 | 1002 | psPathPrefix, |
| 1003 | 1003 | iCounter, |
| 1004 | 1004 | pSurface->dwWidth, |
| 1005 | pSurface->dwHeight, | |
| 1005 | planes[0].dwHeight, | |
| 1006 | 1006 | pSurface->dwPitch, |
| 1007 | 1007 | VpDumperTool::GetFormatStr(pSurface->Format)); |
| 1008 | 1008 |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | ||
| 22 | #include "vp_utils.h" | |
| 23 | #include "vphal_common.h" | |
| 24 | ||
| 25 | MOS_SURFACE VpUtils::VpHalConvertVphalSurfaceToMosSurface(PVPHAL_SURFACE surface) | |
| 26 | { | |
| 27 | VP_FUNC_CALL(); | |
| 28 | ||
| 29 | MOS_SURFACE outSurface = {}; | |
| 30 | MOS_ZeroMemory(&outSurface, sizeof(MOS_SURFACE)); | |
| 31 | ||
| 32 | if (surface) | |
| 33 | { | |
| 34 | outSurface.OsResource = surface->OsResource; | |
| 35 | outSurface.Format = surface->Format; | |
| 36 | outSurface.dwWidth = surface->dwWidth; | |
| 37 | outSurface.dwHeight = surface->dwHeight; | |
| 38 | outSurface.TileType = surface->TileType; | |
| 39 | outSurface.TileModeGMM = surface->TileModeGMM; | |
| 40 | outSurface.bGMMTileEnabled = surface->bGMMTileEnabled; | |
| 41 | outSurface.dwDepth = surface->dwDepth; | |
| 42 | outSurface.dwPitch = surface->dwPitch; | |
| 43 | outSurface.dwSlicePitch = surface->dwSlicePitch; | |
| 44 | outSurface.dwOffset = surface->dwOffset; | |
| 45 | outSurface.bCompressible = surface->bCompressible; | |
| 46 | outSurface.bIsCompressed = surface->bIsCompressed; | |
| 47 | outSurface.CompressionMode = surface->CompressionMode; | |
| 48 | outSurface.CompressionFormat = surface->CompressionFormat; | |
| 49 | } | |
| 50 | ||
| 51 | return outSurface; | |
| 52 | } |
| 0 | 0 | /* |
| 1 | * Copyright (c) 2018-2020, Intel Corporation | |
| 1 | * Copyright (c) 2018-2021, Intel Corporation | |
| 2 | 2 | * |
| 3 | 3 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 4 | 4 | * copy of this software and associated documentation files (the "Software"), |
| 24 | 24 | #include <mutex> |
| 25 | 25 | #include "mos_util_debug.h" |
| 26 | 26 | #include "mos_os.h" |
| 27 | #include "vphal_common.h" | |
| 27 | 28 | |
| 28 | 29 | #define VP_UNUSED(param) (void)(param) |
| 29 | 30 | //------------------------------------------------------------------------------ |
| 254 | 255 | #define VP_FUNC_CALL() |
| 255 | 256 | #endif |
| 256 | 257 | |
| 258 | ||
| 259 | class VpUtils | |
| 260 | { | |
| 261 | public: | |
| 262 | // it is only be used by vpdata->pVpHalState->CopySurface, will be removed after mediaCopy ready | |
| 263 | static MOS_SURFACE VpHalConvertVphalSurfaceToMosSurface(PVPHAL_SURFACE surface); | |
| 264 | }; | |
| 265 | ||
| 257 | 266 | #endif // !__VP_UTILS_H__ |
| 0 | # add libva driver path/name exporting for intel media solution | |
| 1 | export LIBVA_DRIVERS_PATH=${LIBVA_DRIVERS_PATH} | |
| 2 | export LIBVA_DRIVER_NAME=iHD |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | set(MEDIA_COMPILER_FLAGS_COMMON | |
| 21 | # Global setting for warnings | |
| 22 | -Wall | |
| 23 | -Winit-self | |
| 24 | -Wpointer-arith | |
| 25 | -Wno-unused | |
| 26 | -Wno-unknown-pragmas | |
| 27 | -Wno-comments | |
| 28 | -Wno-sign-compare | |
| 29 | -Wno-attributes | |
| 30 | -Wno-narrowing | |
| 31 | -Wno-overflow | |
| 32 | -Wno-parentheses | |
| 33 | -Wno-delete-incomplete | |
| 34 | -Werror=address | |
| 35 | -Werror=format-security | |
| 36 | -Werror=non-virtual-dtor | |
| 37 | -Werror=return-type | |
| 38 | ||
| 39 | # General optimization options | |
| 40 | -finline-functions | |
| 41 | -funswitch-loops | |
| 42 | -fno-short-enums | |
| 43 | -Wa,--noexecstack | |
| 44 | -fno-strict-aliasing | |
| 45 | ||
| 46 | # Other common flags | |
| 47 | -fmessage-length=0 | |
| 48 | -fvisibility=hidden | |
| 49 | -fstack-protector | |
| 50 | -fdata-sections | |
| 51 | -ffunction-sections | |
| 52 | -Wl,--gc-sections | |
| 53 | ||
| 54 | # -m32 or -m64 | |
| 55 | -m${ARCH} | |
| 56 | ||
| 57 | # Global defines | |
| 58 | -DLINUX=1 | |
| 59 | -DLINUX | |
| 60 | -DNO_RTTI | |
| 61 | -DNO_EXCEPTION_HANDLING | |
| 62 | -DINTEL_NOT_PUBLIC | |
| 63 | -g | |
| 64 | ) | |
| 65 | ||
| 66 | ||
| 67 | if(${UFO_MARCH} STREQUAL "slm") | |
| 68 | set(MEDIA_COMPILER_FLAGS_COMMON | |
| 69 | ${MEDIA_COMPILER_FLAGS_COMMON} | |
| 70 | -maes | |
| 71 | # Optimizing driver for Intel | |
| 72 | -mtune=atom | |
| 73 | ) | |
| 74 | endif() | |
| 75 | ||
| 76 | if(${ARCH} STREQUAL "64") | |
| 77 | set(MEDIA_COMPILER_FLAGS_COMMON | |
| 78 | ${MEDIA_COMPILER_FLAGS_COMMON} | |
| 79 | -D_AMD64_ | |
| 80 | -D__CT__ | |
| 81 | ) | |
| 82 | endif() | |
| 83 | ||
| 84 | if(NOT ${PLATFORM} STREQUAL "android") | |
| 85 | set(MEDIA_COMPILER_FLAGS_COMMON | |
| 86 | ${MEDIA_COMPILER_FLAGS_COMMON} | |
| 87 | -D__linux__ | |
| 88 | -fno-tree-pre | |
| 89 | -fPIC | |
| 90 | -Wl,--no-as-needed | |
| 91 | ) | |
| 92 | endif() | |
| 93 | ||
| 94 | set(MEDIA_COMPILER_CXX_FLAGS_COMMON | |
| 95 | # for cpp | |
| 96 | -Wreorder | |
| 97 | -Wsign-promo | |
| 98 | -Wnon-virtual-dtor | |
| 99 | -Wno-invalid-offsetof | |
| 100 | -fvisibility-inlines-hidden | |
| 101 | -fno-use-cxa-atexit | |
| 102 | -frtti | |
| 103 | -fexceptions | |
| 104 | -fpermissive | |
| 105 | -fcheck-new | |
| 106 | ) | |
| 107 | ||
| 108 | if(NOT ${PLATFORM} STREQUAL "android") | |
| 109 | set(MEDIA_COMPILER_CXX_FLAGS_COMMON | |
| 110 | ${MEDIA_COMPILER_CXX_FLAGS_COMMON} | |
| 111 | -std=c++1y | |
| 112 | ) | |
| 113 | endif() | |
| 114 | ||
| 115 | set(MEDIA_COMPILER_FLAGS_RELEASE "") | |
| 116 | ||
| 117 | if(${UFO_VARIANT} STREQUAL "default") | |
| 118 | set(MEDIA_COMPILER_FLAGS_RELEASE | |
| 119 | ${MEDIA_COMPILER_FLAGS_RELEASE} | |
| 120 | -O2 | |
| 121 | -D_FORTIFY_SOURCE=2 | |
| 122 | -fno-omit-frame-pointer | |
| 123 | ) | |
| 124 | endif() | |
| 125 | ||
| 126 | if(NOT ${PLATFORM} STREQUAL "android") | |
| 127 | if(${UFO_VARIANT} STREQUAL "default") | |
| 128 | set(MEDIA_COMPILER_FLAGS_RELEASE | |
| 129 | ${MEDIA_COMPILER_FLAGS_RELEASE} | |
| 130 | -finline-limit=100 | |
| 131 | ) | |
| 132 | elseif(${UFO_VARIANT} STREQUAL "nano") | |
| 133 | set(MEDIA_COMPILER_FLAGS_RELEASE | |
| 134 | ${MEDIA_COMPILER_FLAGS_RELEASE} | |
| 135 | -Os | |
| 136 | -fomit-frame-pointer | |
| 137 | -fno-asynchronous-unwind-tables | |
| 138 | -flto | |
| 139 | -Wl,-flto | |
| 140 | ) | |
| 141 | endif() | |
| 142 | endif() | |
| 143 | ||
| 144 | set(MEDIA_COMPILER_FLAGS_RELEASEINTERNAL | |
| 145 | -O0 | |
| 146 | -fno-omit-frame-pointer | |
| 147 | ) | |
| 148 | ||
| 149 | if(NOT ${PLATFORM} STREQUAL "android") | |
| 150 | set(MEDIA_COMPILER_FLAGS_RELEASEINTERNAL | |
| 151 | ${MEDIA_COMPILER_FLAGS_RELEASEINTERNAL} | |
| 152 | -finline-limit=100 | |
| 153 | ) | |
| 154 | endif() | |
| 155 | ||
| 156 | if ("${CMAKE_CXX_COMPILER_ID}" STREQUAL "Clang") | |
| 157 | list(APPEND MEDIA_COMPILER_FLAGS_COMMON | |
| 158 | -Wno-deprecated | |
| 159 | -Wno-missing-braces | |
| 160 | -Wno-overloaded-virtual | |
| 161 | -Wbitfield-constant-conversion | |
| 162 | ) | |
| 163 | list(REMOVE_ITEM MEDIA_COMPILER_FLAGS_COMMON | |
| 164 | -funswitch-loops | |
| 165 | -Wl,--gc-sections | |
| 166 | -Wl,--no-as-needed | |
| 167 | -fno-tree-pre | |
| 168 | ) | |
| 169 | list(REMOVE_ITEM MEDIA_COMPILER_FLAGS_RELEASE | |
| 170 | -finline-limit=100 | |
| 171 | ) | |
| 172 | list(REMOVE_ITEM MEDIA_COMPILER_FLAGS_RELEASEINTERNAL | |
| 173 | -finline-limit=100 | |
| 174 | ) | |
| 175 | endif() | |
| 176 | ||
| 177 | set(MEDIA_COMPILER_FLAGS_DEBUG | |
| 178 | -O0 | |
| 179 | -DINSTR_GTUNE_EXT | |
| 180 | ) | |
| 181 | ||
| 182 | if(X11_FOUND) | |
| 183 | add_definitions(-DX11_FOUND) | |
| 184 | endif() | |
| 185 | ||
| 186 | include(${MEDIA_SOFTLET_EXT_CMAKE}/linux/media_compile_flags_linux_ext.cmake OPTIONAL) | |
| 187 | ||
| 188 | if(${PLATFORM} STREQUAL "linux") | |
| 189 | #set predefined compiler flags set | |
| 190 | add_compile_options("${MEDIA_COMPILER_FLAGS_COMMON}") | |
| 191 | add_compile_options("$<$<CONFIG:Debug>:${MEDIA_COMPILER_FLAGS_DEBUG}>") | |
| 192 | add_compile_options("$<$<CONFIG:Release>:${MEDIA_COMPILER_FLAGS_RELEASE}>") | |
| 193 | add_compile_options("$<$<CONFIG:ReleaseInternal>:${MEDIA_COMPILER_FLAGS_RELEASEINTERNAL}>") | |
| 194 | ||
| 195 | foreach (flag ${MEDIA_COMPILER_CXX_FLAGS_COMMON}) | |
| 196 | SET (CMAKE_CXX_FLAGS "${CMAKE_CXX_FLAGS} ${flag}") | |
| 197 | endforeach() | |
| 198 | endif() | |
| 199 | ||
| 200 | if (NOT DEFINED GIT_COMMIT) | |
| 201 | execute_process( | |
| 202 | COMMAND git rev-parse --short HEAD | |
| 203 | OUTPUT_VARIABLE GIT_COMMIT | |
| 204 | OUTPUT_STRIP_TRAILING_WHITESPACE | |
| 205 | WORKING_DIRECTORY ${CMAKE_SOURCE_DIR} | |
| 206 | ) | |
| 207 | endif() | |
| 208 | ||
| 209 | add_definitions(-DMEDIA_VERSION="${MEDIA_VERSION}") | |
| 210 | add_definitions(-DMEDIA_VERSION_DETAILS="${GIT_COMMIT}") |
| 0 | # Copyright (c) 2017, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | # global flag for encode AVC_VME/HEVC_VME/MPEG2/VP8 | |
| 21 | bs_set_if_undefined(Encode_VME_Supported "yes") | |
| 22 | # global flag for encode AVC_VDENC/HEVC_VDENC/VP9_VDENC/JPEG | |
| 23 | bs_set_if_undefined(Encode_VDEnc_Supported "yes") | |
| 24 | ||
| 25 | # Some features can't be supported if shaders (kernels) are not | |
| 26 | # available. So, we switch such features off explicitly. That's | |
| 27 | # possible either if user requested a build entirely without | |
| 28 | # shaders or a build with free only shaders. The list of switched | |
| 29 | # off features correspnds to the free kernels case, but we can | |
| 30 | # reuse the full list for enable kernels as well. | |
| 31 | if(NOT ENABLE_KERNELS OR NOT ENABLE_NONFREE_KERNELS) | |
| 32 | # full-open-source | |
| 33 | bs_set_if_undefined(AVC_Encode_VME_Supported "no") | |
| 34 | bs_set_if_undefined(HEVC_Encode_VME_Supported "no") | |
| 35 | bs_set_if_undefined(MPEG2_Encode_VME_Supported "no") | |
| 36 | bs_set_if_undefined(CMRT_HEVC_ENC_FEI_Supported "no") | |
| 37 | bs_set_if_undefined(MMC_Supported "no") | |
| 38 | bs_set_if_undefined(VC1_Decode_Supported "no") | |
| 39 | bs_set_if_undefined(Decode_Processing_Supported "no") | |
| 40 | bs_set_if_undefined(Kernel_Auto_Denoise_Supported "no") | |
| 41 | bs_set_if_undefined(VP8_Encode_Supported "no") | |
| 42 | else() | |
| 43 | # full-feature | |
| 44 | bs_set_if_undefined(AVC_Encode_VME_Supported "${Encode_VME_Supported}") | |
| 45 | bs_set_if_undefined(HEVC_Encode_VME_Supported "${Encode_VME_Supported}") | |
| 46 | bs_set_if_undefined(MPEG2_Encode_VME_Supported "${Encode_VME_Supported}") | |
| 47 | bs_set_if_undefined(CMRT_HEVC_ENC_FEI_Supported "yes") | |
| 48 | bs_set_if_undefined(MMC_Supported "yes") | |
| 49 | bs_set_if_undefined(VC1_Decode_Supported "yes") | |
| 50 | bs_set_if_undefined(Decode_Processing_Supported "yes") | |
| 51 | bs_set_if_undefined(Kernel_Auto_Denoise_Supported "yes") | |
| 52 | bs_set_if_undefined(VP8_Encode_Supported "${Encode_VME_Supported}") | |
| 53 | endif() | |
| 54 | ||
| 55 | # features are always able to open | |
| 56 | bs_set_if_undefined(AV1_Decode_Supported "yes") | |
| 57 | bs_set_if_undefined(AVC_Decode_Supported "yes") | |
| 58 | bs_set_if_undefined(HEVC_Decode_Supported "yes") | |
| 59 | bs_set_if_undefined(JPEG_Decode_Supported "yes") | |
| 60 | bs_set_if_undefined(MPEG2_Decode_Supported "yes") | |
| 61 | bs_set_if_undefined(VP8_Decode_Supported "yes") | |
| 62 | bs_set_if_undefined(VP9_Decode_Supported "yes") | |
| 63 | bs_set_if_undefined(VP_SFC_Supported "yes") | |
| 64 | bs_set_if_undefined(Common_Encode_Supported "yes") | |
| 65 | bs_set_if_undefined(Media_Scalability_Supported "yes") | |
| 66 | ||
| 67 | # features controlled by global flag Encode_VDEnc_Supported | |
| 68 | bs_set_if_undefined(AVC_Encode_VDEnc_Supported "${Encode_VDEnc_Supported}") | |
| 69 | bs_set_if_undefined(HEVC_Encode_VDEnc_Supported "${Encode_VDEnc_Supported}") | |
| 70 | bs_set_if_undefined(VP9_Encode_VDEnc_Supported "${Encode_VDEnc_Supported}") | |
| 71 | bs_set_if_undefined(JPEG_Encode_Supported "${Encode_VDEnc_Supported}") | |
| 72 | ||
| 73 | if(${Common_Encode_Supported} STREQUAL "yes") | |
| 74 | add_definitions(-D_COMMON_ENCODE_SUPPORTED) | |
| 75 | endif() | |
| 76 | ||
| 77 | if(${AVC_Encode_VME_Supported} STREQUAL "yes") | |
| 78 | add_definitions(-D_AVC_ENCODE_VME_SUPPORTED) | |
| 79 | endif() | |
| 80 | ||
| 81 | if(${AVC_Encode_VDEnc_Supported} STREQUAL "yes") | |
| 82 | add_definitions(-D_AVC_ENCODE_VDENC_SUPPORTED) | |
| 83 | endif() | |
| 84 | ||
| 85 | if(${AVC_Decode_Supported} STREQUAL "yes") | |
| 86 | add_definitions(-D_AVC_DECODE_SUPPORTED) | |
| 87 | endif() | |
| 88 | ||
| 89 | if (${HEVC_Encode_VME_Supported} STREQUAL "yes") | |
| 90 | add_definitions (-D_HEVC_ENCODE_VME_SUPPORTED) | |
| 91 | endif() | |
| 92 | ||
| 93 | if (${HEVC_Encode_VDEnc_Supported} STREQUAL "yes") | |
| 94 | add_definitions(-D_HEVC_ENCODE_VDENC_SUPPORTED) | |
| 95 | endif () | |
| 96 | ||
| 97 | if(${HEVC_Decode_Supported} STREQUAL "yes") | |
| 98 | add_definitions(-D_HEVC_DECODE_SUPPORTED) | |
| 99 | endif() | |
| 100 | ||
| 101 | if(${JPEG_Encode_Supported} STREQUAL "yes") | |
| 102 | add_definitions(-D_JPEG_ENCODE_SUPPORTED) | |
| 103 | endif() | |
| 104 | ||
| 105 | if(${JPEG_Decode_Supported} STREQUAL "yes") | |
| 106 | add_definitions(-D_JPEG_DECODE_SUPPORTED) | |
| 107 | endif() | |
| 108 | ||
| 109 | if(${MPEG2_Encode_VME_Supported} STREQUAL "yes") | |
| 110 | add_definitions(-D_MPEG2_ENCODE_VME_SUPPORTED) | |
| 111 | endif() | |
| 112 | ||
| 113 | if(${MPEG2_Decode_Supported} STREQUAL "yes") | |
| 114 | add_definitions(-D_MPEG2_DECODE_SUPPORTED) | |
| 115 | endif() | |
| 116 | ||
| 117 | if(${VC1_Decode_Supported} STREQUAL "yes") | |
| 118 | add_definitions(-D_VC1_DECODE_SUPPORTED) | |
| 119 | endif() | |
| 120 | ||
| 121 | if(${VP8_Decode_Supported} STREQUAL "yes") | |
| 122 | add_definitions(-D_VP8_DECODE_SUPPORTED) | |
| 123 | endif() | |
| 124 | ||
| 125 | if(${VP8_Encode_Supported} STREQUAL "yes") | |
| 126 | add_definitions(-D_VP8_ENCODE_SUPPORTED) | |
| 127 | endif() | |
| 128 | ||
| 129 | if(${VP9_Encode_VDEnc_Supported} STREQUAL "yes") | |
| 130 | add_definitions(-D_VP9_ENCODE_VDENC_SUPPORTED) | |
| 131 | endif() | |
| 132 | ||
| 133 | if(${VP9_Decode_Supported} STREQUAL "yes") | |
| 134 | add_definitions(-D_VP9_DECODE_SUPPORTED) | |
| 135 | endif() | |
| 136 | ||
| 137 | if(${AV1_Decode_Supported} STREQUAL "yes") | |
| 138 | add_definitions(-D_AV1_DECODE_SUPPORTED) | |
| 139 | endif() | |
| 140 | ||
| 141 | if(${CMRT_HEVC_ENC_FEI_Supported} STREQUAL "yes") | |
| 142 | add_definitions(-DHEVC_FEI_ENABLE_CMRT) | |
| 143 | endif() | |
| 144 | ||
| 145 | if(${Decode_Processing_Supported} STREQUAL "yes") | |
| 146 | add_definitions(-D_DECODE_PROCESSING_SUPPORTED) | |
| 147 | endif() | |
| 148 | ||
| 149 | if(${MMC_Supported} STREQUAL "yes") | |
| 150 | add_definitions(-D_MMC_SUPPORTED) | |
| 151 | endif() | |
| 152 | ||
| 153 | if(${Kernel_Auto_Denoise_Supported} STREQUAL "yes") | |
| 154 | add_definitions(-DVEBOX_AUTO_DENOISE_SUPPORTED=1) | |
| 155 | else() | |
| 156 | add_definitions(-DVEBOX_AUTO_DENOISE_SUPPORTED=0) | |
| 157 | endif() | |
| 158 | ||
| 159 | if(${VP_SFC_Supported} STREQUAL "yes") | |
| 160 | add_definitions(-D__VPHAL_SFC_SUPPORTED=1) | |
| 161 | else() | |
| 162 | add_definitions(-D__VPHAL_SFC_SUPPORTED=0) | |
| 163 | endif() | |
| 164 | ||
| 165 | if(ENABLE_KERNELS) | |
| 166 | add_definitions(-DENABLE_KERNELS) | |
| 167 | endif() | |
| 168 | ||
| 169 | if(NOT ENABLE_NONFREE_KERNELS) | |
| 170 | add_definitions(-D_FULL_OPEN_SOURCE) | |
| 171 | endif() | |
| 172 | ||
| 173 | include(${MEDIA_SOFTLET_EXT_CMAKE}/linux/media_feature_flags_linux_ext.cmake OPTIONAL) |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | include(${MEDIA_SOFTLET_EXT_CMAKE}/linux/media_gen_flags_linux_ext.cmake OPTIONAL) |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | include_directories(${BS_DIR_SKUWA}/linux) | |
| 21 | ||
| 22 | if(NOT "${LIBVA_INSTALL_PATH}" STREQUAL "") | |
| 23 | include_directories(BEFORE ${LIBVA_INSTALL_PATH}) | |
| 24 | elseif(DEFINED ENV{LIBVA_INSTALL_PATH} AND NOT "$ENV{LIBVA_INSTALL_PATH}" STREQUAL "") | |
| 25 | include_directories(BEFORE $ENV{LIBVA_INSTALL_PATH}) | |
| 26 | else() | |
| 27 | include(FindPkgConfig) | |
| 28 | pkg_check_modules(LIBVA REQUIRED libva>=1.8.0) | |
| 29 | if(LIBVA_FOUND) | |
| 30 | include_directories(BEFORE ${LIBVA_INCLUDE_DIRS}) | |
| 31 | if("${LIBVA_DRIVERS_PATH}" STREQUAL "") | |
| 32 | pkg_get_variable(LIBVA_DRIVERS_PATH libva driverdir) | |
| 33 | set(LIBVA_DRIVERS_PATH ${LIBVA_DRIVERS_PATH} PARENT_SCOPE) | |
| 34 | endif() | |
| 35 | endif() | |
| 36 | endif() | |
| 37 | ||
| 38 | include(${MEDIA_SOFTLET_EXT_CMAKE}/linux/media_include_paths_linux_ext.cmake OPTIONAL) |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | if(${PLATFORM} STREQUAL "linux") | |
| 21 | include(${MEDIA_SOFTLET_CMAKE}/linux/media_compile_flags_linux.cmake) | |
| 22 | else() | |
| 23 | include(${MEDIA_SOFTLET_EXT_CMAKE}/media_compile_flags_ext.cmake OPTIONAL) | |
| 24 | endif() | |
| 25 |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | bs_set_if_undefined(PLATFORM "linux") | |
| 21 | bs_set_if_undefined(ARCH "64") | |
| 22 | bs_set_if_undefined(UFO_MARCH "corei7") | |
| 23 | bs_set_if_undefined(CMAKE_BUILD_TYPE "Release") | |
| 24 | # UFO_VARIANT=default --> default build | |
| 25 | # UFO_VARIANT=nano --> build optimized for size, a loss of performance is allowed | |
| 26 | bs_set_if_undefined(UFO_VARIANT "default") | |
| 27 | ||
| 28 | bs_set_if_undefined(MEDIA_SOFTLET "${BS_DIR_MEDIA}/media_softlet") | |
| 29 | bs_set_if_undefined(MEDIA_SOFTLET_CMAKE "${MEDIA_SOFTLET}/cmake") | |
| 30 | bs_set_if_undefined(MEDIA_SOFTLET_AGNOSTIC "${MEDIA_SOFTLET}/agnostic") | |
| 31 | bs_set_if_undefined(MEDIA_SOFTLET_LINUX "${MEDIA_SOFTLET}/linux") | |
| 32 | ||
| 33 | bs_set_if_undefined(MEDIA_COMMON "${BS_DIR_MEDIA}/media_common") | |
| 34 | ||
| 35 | include( ${MEDIA_SOFTLET_EXT_CMAKE}/media_defs_ext.cmake OPTIONAL ) | |
| 36 | include( ${MEDIA_COMMON_EXT_CMAKE}/media_defs_ext.cmake OPTIONAL ) |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | ||
| 21 | if(${PLATFORM} STREQUAL "linux") | |
| 22 | include(${MEDIA_SOFTLET_CMAKE}/linux/media_feature_flags_linux.cmake) | |
| 23 | else() | |
| 24 | include(${MEDIA_SOFTLET_EXT_CMAKE}/media_feature_flags_ext.cmake OPTIONAL) | |
| 25 | endif() |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | if(${PLATFORM} STREQUAL "linux") | |
| 21 | include(${MEDIA_SOFTLET_CMAKE}/linux/media_gen_flags_linux.cmake) | |
| 22 | else() | |
| 23 | include(${MEDIA_SOFTLET_EXT_CMAKE}/media_gen_flags_ext.cmake OPTIONAL) | |
| 24 | endif() |
| 0 | # Copyright (c) 2021, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | # external dependency | |
| 21 | # Common path we need to include for now. | |
| 22 | include_directories(${BS_DIR_INC}) | |
| 23 | include_directories(${BS_DIR_INC}/common) | |
| 24 | include_directories(${BS_DIR_INC}/platform/iAlm) | |
| 25 | include_directories(${BS_DIR_INC}/umKmInc) | |
| 26 | ||
| 27 | # external components' header path which media depends on now | |
| 28 | include_directories(${BS_DIR_SKUWA}) | |
| 29 | include_directories(${BS_DIR_GMMLIB}/inc) | |
| 30 | include_directories(${BS_DIR_SOURCE}/huc/inc) | |
| 31 | ||
| 32 | if(${PLATFORM} STREQUAL "linux") | |
| 33 | include(${MEDIA_SOFTLET_CMAKE}/linux/media_include_paths_linux.cmake) | |
| 34 | else() | |
| 35 | include(${MEDIA_SOFTLET_EXT_CMAKE}/media_include_paths_ext.cmake OPTIONAL) | |
| 36 | endif() |
| 0 | # Copyright (c) 2017-2020, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | # Only can include subdirectory which has a media_srcs.cmake | |
| 21 | # the effect is like include(${CMAKE_CURRENT_LIST_DIR}/<subd>/media_srcs.cmake) | |
| 22 | ||
| 23 | macro(media_include_subdirectory subd) | |
| 24 | if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/${subd}/media_srcs.cmake) | |
| 25 | include(${CMAKE_CURRENT_LIST_DIR}/${subd}/media_srcs.cmake) | |
| 26 | else() | |
| 27 | message("-- ${CMAKE_CURRENT_LIST_DIR}/${subd}/media_srcs.cmake doesn't exist, macro(media_include_subdirectory) just does nothing") | |
| 28 | endif() | |
| 29 | endmacro() | |
| 30 | ||
| 31 | # add current path to include path | |
| 32 | macro(media_add_curr_to_include_path) | |
| 33 | if(${PLATFORM} STREQUAL "linux") | |
| 34 | include_directories(${CMAKE_CURRENT_LIST_DIR}) | |
| 35 | else() | |
| 36 | media_add_curr_to_include_path_ext(${CMAKE_CURRENT_LIST_DIR}) | |
| 37 | endif() | |
| 38 | endmacro() | |
| 39 | ||
| 40 | # MediaSetLinkerFlags: apply linker flags for given configuration | |
| 41 | # linkerFlags: linker specific options | |
| 42 | # linkerTarget: optional parameter - apply linker flags for specfied target | |
| 43 | macro (MediaSetLinkerFlags linkerFlags linkerTarget) | |
| 44 | foreach (opt ${linkerFlags}) | |
| 45 | if ("${linkerTarget}" STREQUAL "") | |
| 46 | set (CMAKE_SHARED_LINKER_FLAGS "${CMAKE_SHARED_LINKER_FLAGS} ${opt}") | |
| 47 | set (CMAKE_EXE_LINKER_FLAGS "${CMAKE_EXE_LINKER_FLAGS} ${opt}") | |
| 48 | else() | |
| 49 | set (CMAKE_SHARED_LINKER_FLAGS_${linkerTarget} "${CMAKE_SHARED_LINKER_FLAGS_${linkerTarget}} ${opt}") | |
| 50 | set (CMAKE_EXE_LINKER_FLAGS_${linkerTarget} "${CMAKE_EXE_LINKER_FLAGS_${linkerTarget}} ${opt}") | |
| 51 | endif() | |
| 52 | endforeach() | |
| 53 | endmacro() | |
| 54 | ||
| 55 | # common defines | |
| 56 | macro (MediaAddCommonTargetDefines target) | |
| 57 | if (TARGET ${target}) | |
| 58 | set_property(TARGET ${target} APPEND PROPERTY COMPILE_DEFINITIONS | |
| 59 | $<$<CONFIG:Release>:_RELEASE> | |
| 60 | $<$<CONFIG:ReleaseInternal>: _RELEASE_INTERNAL> | |
| 61 | $<$<CONFIG:Debug>: _DEBUG DEBUG> | |
| 62 | MEDIA_SOFTLET | |
| 63 | ) | |
| 64 | endif() | |
| 65 | endmacro() | |
| 66 | ||
| 67 | include( ${MEDIA_SOFTLET_EXT_CMAKE}/media_utils_ext.cmake OPTIONAL) |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file caps_register_specific.h | |
| 23 | //! \brief This file register all caps data | |
| 24 | //! | |
| 25 | ||
| 26 | #ifndef __CAPS_REGISTER_SPECIFIC_H__ | |
| 27 | #define __CAPS_REGISTER_SPECIFIC_H__ | |
| 28 | ||
| 29 | #include "capstable_data_m12_0_r0_specific.h" | |
| 30 | ||
| 31 | template<> typename MediaCapsTable<CapsData>::OsCapsTable MediaCapsTable<CapsData>::m_pltCaps = {}; | |
| 32 | ||
| 33 | static bool capsTableM12_0Registered = MediaCapsTable<CapsData>::RegisterCaps(plt_M12_0_r0, capsDataM12_0_r0); | |
| 34 | ||
| 35 | #endif //__CAPS_REGISTER_SPECIFIC_H__⏎ |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file capstable_data_hevc_vdenc_m12_0_r0_specific.h | |
| 23 | //! \brief This file defines the data for hevc vdenc m12.0 r0 | |
| 24 | //! | |
| 25 | ||
| 26 | #ifndef __CAPSTABLE_DATA_HEVC_VDENC_M12_0_R0_SPECIFIC_H__ | |
| 27 | #define __CAPSTABLE_DATA_HEVC_VDENC_M12_0_R0_SPECIFIC_H__ | |
| 28 | ||
| 29 | #include "media_capstable_specific.h" | |
| 30 | ||
| 31 | static ConfigDataList configDataList_VAProfileHEVCMain_VAEntrypointEncSliceLP_M12_0_r0 = | |
| 32 | { | |
| 33 | {VA_RC_CQP, 0}, | |
| 34 | {VA_RC_CBR, 0}, | |
| 35 | {VA_RC_VBR, 0}, | |
| 36 | {VA_RC_ICQ, 0}, | |
| 37 | {VA_RC_VCM, 0}, | |
| 38 | {VA_RC_QVBR, 0}, | |
| 39 | {VA_RC_AVBR, 0}, | |
| 40 | {VA_RC_TCBRC, 0}, | |
| 41 | {VA_RC_CBR | VA_RC_PARALLEL, 0}, | |
| 42 | {VA_RC_VBR | VA_RC_PARALLEL, 0}, | |
| 43 | {VA_RC_ICQ | VA_RC_PARALLEL, 0}, | |
| 44 | {VA_RC_VCM | VA_RC_PARALLEL, 0}, | |
| 45 | {VA_RC_QVBR | VA_RC_PARALLEL, 0}, | |
| 46 | {VA_RC_AVBR | VA_RC_PARALLEL, 0}, | |
| 47 | {VA_RC_TCBRC | VA_RC_PARALLEL, 0}, | |
| 48 | }; | |
| 49 | ||
| 50 | static VAConfigAttribValEncROI HEVCCommon_VAEntrypointEncSliceLP_encROI_M12_0_r0 | |
| 51 | { | |
| 52 | {CODECHAL_ENCODE_HEVC_MAX_NUM_ROI,0,1,0} | |
| 53 | }; | |
| 54 | ||
| 55 | static AttribList VAConfigAttribList_VAProfileHEVCMain_VAEntrypointEncSliceLP_M12_0_r0 = | |
| 56 | { | |
| 57 | {VAConfigAttribRTFormat, VA_RT_FORMAT_YUV420 | VA_RT_FORMAT_YUV422 | VA_RT_FORMAT_RGB32}, | |
| 58 | {VAConfigAttribRateControl, VA_RC_CBR | VA_RC_VBR | VA_RC_QVBR | VA_RC_MB | VA_RC_VCM}, | |
| 59 | {VAConfigAttribEncParallelRateControl, 0}, | |
| 60 | {VAConfigAttribEncPackedHeaders, VA_ENC_PACKED_HEADER_PICTURE | VA_ENC_PACKED_HEADER_SEQUENCE | VA_ENC_PACKED_HEADER_SLICE | VA_ENC_PACKED_HEADER_RAW_DATA | VA_ENC_PACKED_HEADER_MISC}, | |
| 61 | {VAConfigAttribEncInterlaced, 0}, | |
| 62 | {VAConfigAttribEncMaxRefFrames, DDI_CODEC_VDENC_MAX_L0_REF_FRAMES | (DDI_CODEC_VDENC_MAX_L1_REF_FRAMES << DDI_CODEC_LEFT_SHIFT_FOR_REFLIST1)}, | |
| 63 | {VAConfigAttribEncMaxSlices, ENCODE_HEVC_VDENC_NUM_MAX_SLICES}, | |
| 64 | {VAConfigAttribEncSliceStructure, VA_ENC_SLICE_STRUCTURE_EQUAL_ROWS | VA_ENC_SLICE_STRUCTURE_MAX_SLICE_SIZE | VA_ENC_SLICE_STRUCTURE_ARBITRARY_ROWS}, | |
| 65 | {VAConfigAttribMaxPictureWidth, CODEC_16K_MAX_PIC_WIDTH}, | |
| 66 | {VAConfigAttribMaxPictureHeight, CODEC_12K_MAX_PIC_HEIGHT}, | |
| 67 | {VAConfigAttribEncQualityRange, NUM_TARGET_USAGE_MODES - 1}, | |
| 68 | {VAConfigAttribEncIntraRefresh, VA_ENC_INTRA_REFRESH_ROLLING_COLUMN | VA_ENC_INTRA_REFRESH_ROLLING_ROW}, | |
| 69 | {VAConfigAttribEncROI, HEVCCommon_VAEntrypointEncSliceLP_encROI_M12_0_r0.value}, | |
| 70 | {VAConfigAttribProcessingRate, VA_PROCESSING_RATE_ENCODE}, | |
| 71 | {VAConfigAttribEncDirtyRect, 16}, | |
| 72 | {VAConfigAttribEncTileSupport, 1}, | |
| 73 | {VAConfigAttribFrameSizeToleranceSupport, 1}, | |
| 74 | {VAConfigAttribCustomRoundingControl, 0}, | |
| 75 | }; | |
| 76 | ||
| 77 | static ProfileSurfaceAttribInfo surfaceAttribInfo_VAEntrypointEncSliceLP_VAProfileHEVCMain_M12_0_r0 | |
| 78 | { | |
| 79 | {VASurfaceAttribPixelFormat, VAGenericValueTypeInteger, VA_SURFACE_ATTRIB_GETTABLE | VA_SURFACE_ATTRIB_SETTABLE, VA_FOURCC_P010}, | |
| 80 | {VASurfaceAttribMaxWidth, VAGenericValueTypeInteger, VA_SURFACE_ATTRIB_GETTABLE, 16384}, | |
| 81 | {VASurfaceAttribMaxHeight, VAGenericValueTypeInteger, VA_SURFACE_ATTRIB_GETTABLE, 12288}, | |
| 82 | {VASurfaceAttribMinWidth, VAGenericValueTypeInteger, VA_SURFACE_ATTRIB_GETTABLE, 128}, | |
| 83 | {VASurfaceAttribMinHeight, VAGenericValueTypeInteger, VA_SURFACE_ATTRIB_GETTABLE, 128}, | |
| 84 | }; | |
| 85 | ||
| 86 | //! | |
| 87 | //! \brief Definion for EntrypointMap | |
| 88 | //! | |
| 89 | static EntrypointData entrypointMap_VAProfileHEVCMain_Data_M12_0_r0 | |
| 90 | { | |
| 91 | &VAConfigAttribList_VAProfileHEVCMain_VAEntrypointEncSliceLP_M12_0_r0, | |
| 92 | &configDataList_VAProfileHEVCMain_VAEntrypointEncSliceLP_M12_0_r0, | |
| 93 | &surfaceAttribInfo_VAEntrypointEncSliceLP_VAProfileHEVCMain_M12_0_r0, | |
| 94 | }; | |
| 95 | ||
| 96 | static EntrypointMap entrypointMap_VAProfileHEVCMain_M12_0_r0 | |
| 97 | { | |
| 98 | {VAEntrypointEncSliceLP, &entrypointMap_VAProfileHEVCMain_Data_M12_0_r0}, | |
| 99 | }; | |
| 100 | ||
| 101 | #endif //__CAPSTABLE_DATA_HEVC_VDENC_M12_0_R0_SPECIFIC_H__⏎ |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file capstable_data_image_format_definition.h | |
| 23 | //! \brief This file defines all image format definition | |
| 24 | //! | |
| 25 | ||
| 26 | #ifndef __CAPSTABLE_DATA_IMAGE_FORMAT_DEFINITION_H__ | |
| 27 | #define __CAPSTABLE_DATA_IMAGE_FORMAT_DEFINITION_H__ | |
| 28 | ||
| 29 | #include "va/va.h" | |
| 30 | ||
| 31 | VAImageFormat formatBGRA = {VA_FOURCC_BGRA, VA_LSB_FIRST, 32, 32, 0x0000ff00, 0x00ff0000, 0xff000000, 0x000000ff }; /* [31:0] B:G:R:A 8:8:8:8 little endian */ | |
| 32 | VAImageFormat formatARGB = {VA_FOURCC_ARGB, VA_LSB_FIRST, 32, 32, 0x00ff0000, 0x0000ff00, 0x000000ff, 0xff000000 }; /* [31:0] A:R:G:B 8:8:8:8 little endian */ | |
| 33 | VAImageFormat formatRGBA = {VA_FOURCC_RGBA, VA_LSB_FIRST, 32, 32, 0xff000000, 0x00ff0000, 0x0000ff00, 0x000000ff }; /* [31:0] R:G:B:A 8:8:8:8 little endian */ | |
| 34 | VAImageFormat formatABGR = {VA_FOURCC_ABGR, VA_LSB_FIRST, 32, 32, 0x000000ff, 0x0000ff00, 0x00ff0000, 0xff000000 }; /* [31:0] A:B:G:R 8:8:8:8 little endian */ | |
| 35 | VAImageFormat formatBGRX = {VA_FOURCC_BGRX, VA_LSB_FIRST, 32, 24, 0x0000ff00, 0x00ff0000, 0xff000000, 0 }; /* [31:0] B:G:R:x 8:8:8:8 little endian */ | |
| 36 | VAImageFormat formatXRGB = {VA_FOURCC_XRGB, VA_LSB_FIRST, 32, 24, 0x00ff0000, 0x0000ff00, 0x000000ff, 0 }; /* [31:0] x:R:G:B 8:8:8:8 little endian */ | |
| 37 | VAImageFormat formatRGBX = {VA_FOURCC_RGBX, VA_LSB_FIRST, 32, 24, 0xff000000, 0x00ff0000, 0x0000ff00, 0 }; /* [31:0] R:G:B:x 8:8:8:8 little endian */ | |
| 38 | VAImageFormat formatXBGR = {VA_FOURCC_XBGR, VA_LSB_FIRST, 32, 24, 0x000000ff, 0x0000ff00, 0x00ff0000, 0 }; /* [31:0] x:B:G:R 8:8:8:8 little endian */ | |
| 39 | VAImageFormat formatA2R10G10B10 = {VA_FOURCC_A2R10G10B10, VA_LSB_FIRST, 32, 30, 0x3ff00000, 0x000ffc00, 0x000003ff, 0x30000000 }; /* [31:0] A:R:G:B 2:10:10:10 little endian */ | |
| 40 | VAImageFormat formatA2B10G10R10 = {VA_FOURCC_A2B10G10R10, VA_LSB_FIRST, 32, 30, 0x000003ff, 0x000ffc00, 0x3ff00000, 0x30000000 }; /* [31:0] A:B:G:R 2:10:10:10 little endian */ | |
| 41 | VAImageFormat formatX2R10G10B10 = {VA_FOURCC_X2R10G10B10, VA_LSB_FIRST, 32, 30, 0x3ff00000, 0x000ffc00, 0x000003ff, 0 }; /* [31:0] X:R:G:B 2:10:10:10 little endian */ | |
| 42 | VAImageFormat formatX2B10G10R10 = {VA_FOURCC_X2B10G10R10, VA_LSB_FIRST, 32, 30, 0x000003ff, 0x000ffc00, 0x3ff00000, 0 }; /* [31:0] X:B:G:R 2:10:10:10 little endian */ | |
| 43 | VAImageFormat formatRGB565 = {VA_FOURCC_RGB565, VA_LSB_FIRST, 16, 16, 0xf800, 0x07e0, 0x001f, 0 }; /* [15:0] R:G:B 5:6:5 little endian */ | |
| 44 | VAImageFormat formatAYUV = {VA_FOURCC_AYUV, VA_LSB_FIRST, 32, 0,0,0,0,0 }; | |
| 45 | #if VA_CHECK_VERSION(1, 13, 0) | |
| 46 | VAImageFormat formatXYUV = {VA_FOURCC_XYUV, VA_LSB_FIRST, 32, 0,0,0,0,0 }; | |
| 47 | #endif | |
| 48 | VAImageFormat formatY800 = {VA_FOURCC_Y800, VA_LSB_FIRST, 8, 0,0,0,0,0 }; | |
| 49 | VAImageFormat formatNV12 = {VA_FOURCC_NV12, VA_LSB_FIRST, 12, 0,0,0,0,0 }; | |
| 50 | VAImageFormat formatNV21 = {VA_FOURCC_NV21, VA_LSB_FIRST, 12, 0,0,0,0,0 }; | |
| 51 | VAImageFormat formatYUY2 = {VA_FOURCC_YUY2, VA_LSB_FIRST, 16, 0,0,0,0,0 }; | |
| 52 | VAImageFormat formatUYVY = {VA_FOURCC_UYVY, VA_LSB_FIRST, 16, 0,0,0,0,0 }; | |
| 53 | VAImageFormat formatYV12 = {VA_FOURCC_YV12, VA_LSB_FIRST, 12, 0,0,0,0,0 }; | |
| 54 | VAImageFormat formatI420 = {VA_FOURCC_I420, VA_LSB_FIRST, 12, 0,0,0,0,0 }; | |
| 55 | VAImageFormat format411P = {VA_FOURCC_411P, VA_LSB_FIRST, 12, 0,0,0,0,0 }; | |
| 56 | VAImageFormat format422H = {VA_FOURCC_422H, VA_LSB_FIRST, 16, 0,0,0,0,0 }; | |
| 57 | VAImageFormat format422V = {VA_FOURCC_422V, VA_LSB_FIRST, 16, 0,0,0,0,0 }; | |
| 58 | VAImageFormat format444P = {VA_FOURCC_444P, VA_LSB_FIRST, 24, 0,0,0,0,0 }; | |
| 59 | VAImageFormat formatIMC3 = {VA_FOURCC_IMC3, VA_LSB_FIRST, 16, 0,0,0,0,0 }; | |
| 60 | VAImageFormat formatP010 = {VA_FOURCC_P010, VA_LSB_FIRST, 24, 0,0,0,0,0 }; | |
| 61 | VAImageFormat formatP012 = {VA_FOURCC_P012, VA_LSB_FIRST, 24, 0,0,0,0,0 }; | |
| 62 | VAImageFormat formatP016 = {VA_FOURCC_P016, VA_LSB_FIRST, 24, 0,0,0,0,0 }; | |
| 63 | VAImageFormat formatY210 = {VA_FOURCC_Y210, VA_LSB_FIRST, 32, 0,0,0,0,0 }; | |
| 64 | VAImageFormat formatY212 = {VA_FOURCC_Y212, VA_LSB_FIRST, 32, 0,0,0,0,0 }; | |
| 65 | VAImageFormat formatY216 = {VA_FOURCC_Y216, VA_LSB_FIRST, 32, 0,0,0,0,0 }; | |
| 66 | VAImageFormat formatY410 = {VA_FOURCC_Y410, VA_LSB_FIRST, 32, 0,0,0,0,0 }; | |
| 67 | VAImageFormat formatY412 = {VA_FOURCC_Y412, VA_LSB_FIRST, 64, 0,0,0,0,0 }; | |
| 68 | VAImageFormat formatY416 = {VA_FOURCC_Y416, VA_LSB_FIRST, 64, 0,0,0,0,0 }; | |
| 69 | VAImageFormat formatRGBP = {VA_FOURCC_RGBP, VA_LSB_FIRST, 24, 24,0,0,0,0}; | |
| 70 | VAImageFormat formatBGRP = {VA_FOURCC_BGRP, VA_LSB_FIRST, 24, 24,0,0,0,0}; | |
| 71 | ||
| 72 | #endif //__CAPSTABLE_DATA_IMAGE_FORMAT_DEFINITION_H__⏎ |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file capstable_data_hevc_vdenc_m12_0_r0_specific.h | |
| 23 | //! \brief This file defines the data for hevc vdenc m12.0 r0 | |
| 24 | //! | |
| 25 | ||
| 26 | #ifndef __CAPSTABLE_DATA_M12_0_R0_SPECIFIC_H__ | |
| 27 | #define __CAPSTABLE_DATA_M12_0_R0_SPECIFIC_H__ | |
| 28 | ||
| 29 | #include "capstable_data_hevc_vdenc_m12_0_r0_specific.h" | |
| 30 | #include "capstable_data_image_format_definition.h" | |
| 31 | ||
| 32 | #define IP_VERSION_M12_0 0x1200 | |
| 33 | const PlatformInfo plt_M12_0_r0 = {IP_VERSION_M12_0, 0}; | |
| 34 | ||
| 35 | static std::map<uint32_t, VAImageFormat*> imgtbl_M12_0_r0 | |
| 36 | { | |
| 37 | {VA_FOURCC_BGRA, &formatBGRA}, | |
| 38 | {VA_FOURCC_ARGB, &formatARGB}, | |
| 39 | {VA_FOURCC_RGBA, &formatRGBA}, | |
| 40 | {VA_FOURCC_ABGR, &formatABGR}, | |
| 41 | {VA_FOURCC_BGRX, &formatBGRX}, | |
| 42 | {VA_FOURCC_XRGB, &formatXRGB}, | |
| 43 | {VA_FOURCC_RGBX, &formatRGBX}, | |
| 44 | {VA_FOURCC_XBGR, &formatXBGR}, | |
| 45 | {VA_FOURCC_A2R10G10B10, &formatA2R10G10B10}, | |
| 46 | {VA_FOURCC_A2B10G10R10, &formatA2B10G10R10}, | |
| 47 | {VA_FOURCC_X2R10G10B10, &formatX2R10G10B10}, | |
| 48 | {VA_FOURCC_X2B10G10R10, &formatX2B10G10R10}, | |
| 49 | {VA_FOURCC_RGB565, &formatRGB565}, | |
| 50 | {VA_FOURCC_AYUV, &formatAYUV}, | |
| 51 | #if VA_CHECK_VERSION(1, 13, 0) | |
| 52 | {VA_FOURCC_XYUV, &formatXYUV}, | |
| 53 | #endif | |
| 54 | {VA_FOURCC_Y800, &formatY800}, | |
| 55 | {VA_FOURCC_NV12, &formatNV12}, | |
| 56 | {VA_FOURCC_NV21, &formatNV21}, | |
| 57 | {VA_FOURCC_YUY2, &formatYUY2}, | |
| 58 | {VA_FOURCC_UYVY, &formatUYVY}, | |
| 59 | {VA_FOURCC_YV12, &formatYV12}, | |
| 60 | {VA_FOURCC_I420, &formatI420}, | |
| 61 | {VA_FOURCC_411P, &format411P}, | |
| 62 | {VA_FOURCC_422H, &format422H}, | |
| 63 | {VA_FOURCC_422V, &format422V}, | |
| 64 | {VA_FOURCC_444P, &format444P}, | |
| 65 | {VA_FOURCC_IMC3, &formatIMC3}, | |
| 66 | {VA_FOURCC_P010, &formatP010}, | |
| 67 | {VA_FOURCC_P012, &formatP012}, | |
| 68 | {VA_FOURCC_P016, &formatP016}, | |
| 69 | {VA_FOURCC_Y210, &formatY210}, | |
| 70 | {VA_FOURCC_Y212, &formatY212}, | |
| 71 | {VA_FOURCC_Y216, &formatY216}, | |
| 72 | {VA_FOURCC_Y410, &formatY410}, | |
| 73 | {VA_FOURCC_Y412, &formatY412}, | |
| 74 | {VA_FOURCC_Y416, &formatY416}, | |
| 75 | {VA_FOURCC_RGBP, &formatRGBP}, | |
| 76 | {VA_FOURCC_BGRP, &formatBGRP}, | |
| 77 | }; | |
| 78 | ||
| 79 | static ProfileMap profileMap_M12_0_r0 | |
| 80 | { | |
| 81 | {VAProfileHEVCMain, &entrypointMap_VAProfileHEVCMain_M12_0_r0}, | |
| 82 | }; | |
| 83 | ||
| 84 | static CapsData capsDataM12_0_r0 | |
| 85 | { | |
| 86 | &profileMap_M12_0_r0, | |
| 87 | &imgtbl_M12_0_r0 | |
| 88 | }; | |
| 89 | ||
| 90 | #endif //__CAPSTABLE_DATA_M12_0_R0_SPECIFIC_H__⏎ |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | ||
| 22 | //! | |
| 23 | //! \file media_capstable_linux.cpp | |
| 24 | //! \brief implemantation of media caps table class on linux | |
| 25 | //! | |
| 26 | ||
| 27 | #include "media_capstable_linux.h" | |
| 28 | #include "media_libva_common.h" | |
| 29 | #include "media_libva_util.h" | |
| 30 | #include "media_libva.h" | |
| 31 | #include "hwinfo_linux.h" | |
| 32 | #include "linux_system_info.h" | |
| 33 | #include "media_libva_caps_factory.h" | |
| 34 | ||
| 35 | template<> typename MediaCapsTable<CapsData>::OsCapsTable MediaCapsTable<CapsData>::m_pltCaps = {}; | |
| 36 | ||
| 37 | MediaCapsTableSpecific::MediaCapsTableSpecific(HwDeviceInfo &deviceInfo) | |
| 38 | { | |
| 39 | m_plt.ipVersion = deviceInfo.ipVersion; | |
| 40 | m_plt.usRevId = deviceInfo.usRevId; | |
| 41 | ||
| 42 | MediaCapsTable::Iterator capsIter; | |
| 43 | if(GetCapsTablePlatform(m_plt, capsIter)) | |
| 44 | { | |
| 45 | m_profileMap = capsIter->second.profileMap; | |
| 46 | m_imgTbl = capsIter->second.imgTbl; | |
| 47 | } | |
| 48 | else | |
| 49 | { | |
| 50 | DDI_ASSERTMESSAGE("unknown platform with usRevId=%d, ipVersion=%d\n", (int)m_plt.usRevId, (int)m_plt.ipVersion); | |
| 51 | } | |
| 52 | } | |
| 53 | ||
| 54 | VAStatus MediaCapsTableSpecific::Init() | |
| 55 | { | |
| 56 | DDI_FUNCTION_ENTER(); | |
| 57 | ||
| 58 | for (auto profileMapIter: *m_profileMap) | |
| 59 | { | |
| 60 | auto profile = profileMapIter.first; | |
| 61 | for(auto entrypointMapIter: *profileMapIter.second) | |
| 62 | { | |
| 63 | auto entrypoint = entrypointMapIter.first; | |
| 64 | auto entrypointData = entrypointMapIter.second; | |
| 65 | auto attriblist = entrypointData->attribList; | |
| 66 | auto componentData = entrypointData->configDataList; | |
| 67 | int32_t numAttribList = attriblist->size(); | |
| 68 | ||
| 69 | for(int i = 0; i < componentData->size(); i++) | |
| 70 | { | |
| 71 | auto configData = componentData->at(i); | |
| 72 | m_configList.emplace_back(profile, entrypoint, attriblist->data(), numAttribList, configData); | |
| 73 | } | |
| 74 | } | |
| 75 | } | |
| 76 | ||
| 77 | return VA_STATUS_SUCCESS; | |
| 78 | } | |
| 79 | ||
| 80 | VAStatus MediaCapsTableSpecific::QueryConfigProfiles( | |
| 81 | VAProfile *profileList, | |
| 82 | int32_t *profilesNum) | |
| 83 | { | |
| 84 | DDI_FUNCTION_ENTER(); | |
| 85 | ||
| 86 | DDI_CHK_NULL(profileList, "Null pointer", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 87 | DDI_CHK_NULL(profilesNum, "Null pointer", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 88 | ||
| 89 | int i = 0; | |
| 90 | ||
| 91 | if(m_profileMap->size() <= 0) | |
| 92 | { | |
| 93 | return VA_STATUS_ERROR_INVALID_CONFIG; | |
| 94 | } | |
| 95 | ||
| 96 | for (auto it = m_profileMap->begin(); it!=m_profileMap->end(); ++it) | |
| 97 | { | |
| 98 | profileList[i++] = (VAProfile)(it->first); | |
| 99 | } | |
| 100 | *profilesNum = m_profileMap->size(); | |
| 101 | return VA_STATUS_SUCCESS; | |
| 102 | } | |
| 103 | ||
| 104 | EntrypointMap* MediaCapsTableSpecific::QueryConfigEntrypointsMap( | |
| 105 | VAProfile profile) | |
| 106 | { | |
| 107 | DDI_FUNCTION_ENTER(); | |
| 108 | ||
| 109 | int i = 0; | |
| 110 | ||
| 111 | if(m_profileMap->find(profile) == m_profileMap->end()) | |
| 112 | { | |
| 113 | return nullptr; | |
| 114 | } | |
| 115 | ||
| 116 | return m_profileMap->at(profile); | |
| 117 | } | |
| 118 | ||
| 119 | AttribList* MediaCapsTableSpecific::QuerySupportedAttrib( | |
| 120 | VAProfile profile, | |
| 121 | VAEntrypoint entrypoint) | |
| 122 | { | |
| 123 | DDI_FUNCTION_ENTER(); | |
| 124 | ||
| 125 | if(m_profileMap->find(profile) == m_profileMap->end() || | |
| 126 | m_profileMap->at(profile)->find(entrypoint) == m_profileMap->at(profile)->end()) | |
| 127 | { | |
| 128 | return nullptr; | |
| 129 | } | |
| 130 | ||
| 131 | return m_profileMap->at(profile)->at(entrypoint)->attribList; | |
| 132 | } | |
| 133 | ||
| 134 | std::vector<ConfigLinux>* MediaCapsTableSpecific::GetConfigList() | |
| 135 | { | |
| 136 | DDI_FUNCTION_ENTER(); | |
| 137 | ||
| 138 | return &m_configList; | |
| 139 | } | |
| 140 | ||
| 141 | ConfigLinux* MediaCapsTableSpecific::QueryConfigItemFromIndex( | |
| 142 | VAConfigID configId) | |
| 143 | { | |
| 144 | DDI_FUNCTION_ENTER(); | |
| 145 | ||
| 146 | if (configId >= m_configList.size()) | |
| 147 | { | |
| 148 | return nullptr; | |
| 149 | } | |
| 150 | ||
| 151 | return &m_configList[configId]; | |
| 152 | } | |
| 153 | ||
| 154 | VAStatus MediaCapsTableSpecific::CreateConfig( | |
| 155 | VAProfile profile, | |
| 156 | VAEntrypoint entrypoint, | |
| 157 | VAConfigAttrib *attribList, | |
| 158 | int32_t numAttribs, | |
| 159 | VAConfigID *configId) | |
| 160 | { | |
| 161 | DDI_FUNCTION_ENTER(); | |
| 162 | ||
| 163 | DDI_CHK_NULL(attribList, "Null pointer", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 164 | DDI_CHK_NULL(configId, "Null pointer", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 165 | ||
| 166 | bool sameConfig = false; | |
| 167 | for (auto configItem : m_configList) | |
| 168 | { | |
| 169 | // check profile, entrypoint here, check attribute in caps_next | |
| 170 | // check component specific and return configId in component function | |
| 171 | if (configItem.profile == profile && | |
| 172 | configItem.entrypoint == entrypoint) | |
| 173 | { | |
| 174 | sameConfig = true; | |
| 175 | break; | |
| 176 | } | |
| 177 | } | |
| 178 | ||
| 179 | return sameConfig ? VA_STATUS_SUCCESS : VA_STATUS_ERROR_INVALID_VALUE; | |
| 180 | } | |
| 181 | ||
| 182 | VAStatus MediaCapsTableSpecific::DestroyConfig(VAConfigID configId) | |
| 183 | { | |
| 184 | DDI_FUNCTION_ENTER(); | |
| 185 | ||
| 186 | if(configId < m_configList.size()) | |
| 187 | { | |
| 188 | return VA_STATUS_SUCCESS; | |
| 189 | } | |
| 190 | ||
| 191 | return VA_STATUS_ERROR_INVALID_CONFIG; | |
| 192 | } | |
| 193 | ||
| 194 | ImgTable* MediaCapsTableSpecific::GetImgTable() | |
| 195 | { | |
| 196 | DDI_FUNCTION_ENTER(); | |
| 197 | ||
| 198 | return m_imgTbl; | |
| 199 | } | |
| 200 | ||
| 201 | uint32_t MediaCapsTableSpecific::GetImageFormatsMaxNum() | |
| 202 | { | |
| 203 | DDI_FUNCTION_ENTER(); | |
| 204 | ||
| 205 | return m_imgTbl->size(); | |
| 206 | } | |
| 207 | ||
| 208 | ProfileSurfaceAttribInfo* MediaCapsTableSpecific::QuerySurfaceAttributesFromConfigId( | |
| 209 | VAConfigID configId) | |
| 210 | { | |
| 211 | DDI_FUNCTION_ENTER(); | |
| 212 | ||
| 213 | ConfigLinux* configItem = nullptr; | |
| 214 | configItem = QueryConfigItemFromIndex(configId); | |
| 215 | DDI_CHK_NULL(configItem, "Invalid config id!", nullptr); | |
| 216 | ||
| 217 | VAProfile profile = configItem->profile; | |
| 218 | VAEntrypoint entrypoint = configItem->entrypoint; | |
| 219 | ||
| 220 | uint32_t i = 0; | |
| 221 | ||
| 222 | if (m_profileMap->find(profile) == m_profileMap->end() || | |
| 223 | m_profileMap->at(profile)->find(entrypoint) == m_profileMap->at(profile)->end()) | |
| 224 | { | |
| 225 | return nullptr; | |
| 226 | } | |
| 227 | ||
| 228 | return m_profileMap->at(profile)->at(entrypoint)->surfaceAttrib; | |
| 229 | } |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file media_capstable_linux.h | |
| 23 | //! \brief Header file of media caps table class on linux | |
| 24 | //! | |
| 25 | ||
| 26 | #ifndef __MEDIA_CAPSTABLE_LINUX_H__ | |
| 27 | #define __MEDIA_CAPSTABLE_LINUX_H__ | |
| 28 | ||
| 29 | #include <vector> | |
| 30 | #include <map> | |
| 31 | #include <set> | |
| 32 | ||
| 33 | #include "va/va.h" | |
| 34 | #include "media_libva_common.h" | |
| 35 | #include "capstable_data_linux_definition.h" | |
| 36 | #include "media_capstable.h" | |
| 37 | ||
| 38 | //! | |
| 39 | //! \class ConfigLinux | |
| 40 | //! \brief Config for Linux caps | |
| 41 | //! | |
| 42 | struct ConfigLinux | |
| 43 | { | |
| 44 | VAProfile profile = VAProfileNone; | |
| 45 | VAEntrypoint entrypoint = VAEntrypointVLD; | |
| 46 | VAConfigAttrib *attribList = nullptr; | |
| 47 | int32_t numAttribs = 0; | |
| 48 | ComponentData componentData = {}; | |
| 49 | ||
| 50 | ConfigLinux( | |
| 51 | VAProfile p, | |
| 52 | VAEntrypoint e, | |
| 53 | VAConfigAttrib *a, | |
| 54 | int32_t n, | |
| 55 | ComponentData c) : profile(p), entrypoint(e), attribList(a), numAttribs(n), componentData(c){} | |
| 56 | ConfigLinux(){} | |
| 57 | }; | |
| 58 | ||
| 59 | #define CONFIG_ATTRIB_NONE 0x00000000 | |
| 60 | ||
| 61 | //! | |
| 62 | //! \class MediaLibvaCaps | |
| 63 | //! \brief Media libva caps | |
| 64 | //! | |
| 65 | class MediaCapsTableSpecific : public MediaCapsTable<CapsData> | |
| 66 | { | |
| 67 | private: | |
| 68 | PlatformInfo m_plt; | |
| 69 | ProfileMap *m_profileMap = nullptr; | |
| 70 | ImgTable *m_imgTbl = nullptr; | |
| 71 | ||
| 72 | public: | |
| 73 | //! | |
| 74 | //! \brief Store config | |
| 75 | //! | |
| 76 | std::vector<ConfigLinux> m_configList = {}; | |
| 77 | ||
| 78 | //! | |
| 79 | //! \brief Constructor | |
| 80 | //! | |
| 81 | MediaCapsTableSpecific(HwDeviceInfo &deviceInfo); | |
| 82 | ||
| 83 | //! | |
| 84 | //! \brief Destructor | |
| 85 | //! | |
| 86 | ~MediaCapsTableSpecific() {}; | |
| 87 | ||
| 88 | //! | |
| 89 | //! \brief Init configlist | |
| 90 | //! | |
| 91 | VAStatus Init(); | |
| 92 | ||
| 93 | //! | |
| 94 | //! \brief Get configlist, this is for component createConfig | |
| 95 | //! | |
| 96 | std::vector<ConfigLinux>* GetConfigList(); | |
| 97 | ||
| 98 | //! | |
| 99 | //! \brief Get Image Table | |
| 100 | //! | |
| 101 | //! \return ImgTable | |
| 102 | //! | |
| 103 | ImgTable* GetImgTable(); | |
| 104 | ||
| 105 | //! | |
| 106 | //! \brief Get Supported Attrib Value | |
| 107 | //! | |
| 108 | //! \param [in] profile | |
| 109 | //! VA profile | |
| 110 | //! | |
| 111 | //! \param [in] entrypoint | |
| 112 | //! VA entrypoint | |
| 113 | //! | |
| 114 | //! \return AttribList* | |
| 115 | //! nullptr if query failed | |
| 116 | //! | |
| 117 | AttribList* QuerySupportedAttrib( | |
| 118 | VAProfile profile, | |
| 119 | VAEntrypoint entrypoint); | |
| 120 | ||
| 121 | //! | |
| 122 | //! \brief Get specific config item | |
| 123 | //! | |
| 124 | //! \param [in] configId | |
| 125 | //! config list index | |
| 126 | //! | |
| 127 | //! \return ConfigLinux | |
| 128 | //! nullptr if invalid index | |
| 129 | //! | |
| 130 | ConfigLinux* QueryConfigItemFromIndex( | |
| 131 | VAConfigID configId); | |
| 132 | ||
| 133 | //! | |
| 134 | //! \brief Create a configuration | |
| 135 | //! \details It passes in the attribute list that specifies the attributes it | |
| 136 | //! cares about, with the rest taking default values. | |
| 137 | //! | |
| 138 | //! \param [in] profile | |
| 139 | //! VA profile | |
| 140 | //! | |
| 141 | //! \param [in] entrypoint | |
| 142 | //! VA entrypoint | |
| 143 | //! | |
| 144 | //! \param [in] attribList | |
| 145 | //! Pointer to VAConfigAttrib array that specifies the attributes | |
| 146 | //! | |
| 147 | //! \param [in] numAttribs | |
| 148 | //! Number of VAConfigAttrib in the array attribList | |
| 149 | //! | |
| 150 | //! \param [out] configId | |
| 151 | //! Pointer to returned VAConfigID if success | |
| 152 | //! | |
| 153 | //! \return VAStatus | |
| 154 | //! VA_STATUS_SUCCESS if success | |
| 155 | //! | |
| 156 | VAStatus CreateConfig( | |
| 157 | VAProfile profile, | |
| 158 | VAEntrypoint entrypoint, | |
| 159 | VAConfigAttrib *attribList, | |
| 160 | int32_t numAttribs, | |
| 161 | VAConfigID *configId); | |
| 162 | ||
| 163 | //! | |
| 164 | //! \brief Destory the VAConfigID | |
| 165 | //! | |
| 166 | //! \param [in] configId | |
| 167 | //! Specify the VAConfigID | |
| 168 | //! | |
| 169 | //! \return VAStatus | |
| 170 | //! VA_STATUS_SUCCESS if succeed | |
| 171 | //! VA_STATUS_ERROR_INVALID_CONFIG if the conifgId is invalid | |
| 172 | //! | |
| 173 | VAStatus DestroyConfig(VAConfigID configId); | |
| 174 | ||
| 175 | //! | |
| 176 | //! \brief Query EntrypointsMap | |
| 177 | //! | |
| 178 | //! \param [in] configId | |
| 179 | //! | |
| 180 | //! \return EntrypointMap* | |
| 181 | //! nullptr if invalid profile | |
| 182 | //! | |
| 183 | EntrypointMap* QueryConfigEntrypointsMap( | |
| 184 | VAProfile profile); | |
| 185 | ||
| 186 | //! | |
| 187 | //! \brief Query supported profiles | |
| 188 | //! | |
| 189 | //! \param [in] profileList | |
| 190 | //! Pointer to VAProfile array that can hold at least vaMaxNumProfile() entries | |
| 191 | //! | |
| 192 | //! \param [out] numProfiles | |
| 193 | //! Pointer to int32_t. It returns the actual number of supported profiles. | |
| 194 | //! | |
| 195 | //! \return VAStatus | |
| 196 | //! VA_STATUS_SUCCESS if success | |
| 197 | //! | |
| 198 | VAStatus QueryConfigProfiles( | |
| 199 | VAProfile *profileList, | |
| 200 | int32_t *profilesNum); | |
| 201 | ||
| 202 | //! | |
| 203 | //! \brief Query SurfaceAttributes From ConfigId | |
| 204 | //! | |
| 205 | //! \param [in] configId | |
| 206 | //! Supported surface attrib | |
| 207 | //! | |
| 208 | //! \return ProfileSurfaceAttribInfo* | |
| 209 | //! nullptr if invalid configid | |
| 210 | //! | |
| 211 | ProfileSurfaceAttribInfo* QuerySurfaceAttributesFromConfigId( | |
| 212 | VAConfigID configId); | |
| 213 | ||
| 214 | //! | |
| 215 | //! \brief Return the maxinum number of supported image formats for current platform ipVersion | |
| 216 | //! | |
| 217 | //! \return The maxinum number of supported image formats for current platform ipVersion | |
| 218 | //! | |
| 219 | uint32_t GetImageFormatsMaxNum(); | |
| 220 | }; | |
| 221 | ||
| 222 | #endif //__MEDIA_CAPSTABLE_LINUX_H__ |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | ||
| 22 | //! | |
| 23 | //! \file media_capstable_specific.cpp | |
| 24 | //! \brief implemantation of media caps table class on specific os | |
| 25 | //! | |
| 26 | ||
| 27 | #include "media_capstable_specific.h" | |
| 28 | #include "media_libva_common.h" | |
| 29 | #include "media_libva_util.h" | |
| 30 | #include "media_libva.h" | |
| 31 | #include "hwinfo_linux.h" | |
| 32 | #include "linux_system_info.h" | |
| 33 | #include "media_libva_caps_factory.h" | |
| 34 | #include "caps_register_specific.h" | |
| 35 | ||
| 36 | MediaCapsTableSpecific::MediaCapsTableSpecific(HwDeviceInfo &deviceInfo) | |
| 37 | { | |
| 38 | m_plt.ipVersion = deviceInfo.ipVersion; | |
| 39 | m_plt.usRevId = deviceInfo.usRevId; | |
| 40 | ||
| 41 | MediaCapsTable::Iterator capsIter; | |
| 42 | if(GetCapsTablePlatform(m_plt, capsIter)) | |
| 43 | { | |
| 44 | m_profileMap = capsIter->second.profileMap; | |
| 45 | m_imgTbl = capsIter->second.imgTbl; | |
| 46 | } | |
| 47 | else | |
| 48 | { | |
| 49 | DDI_ASSERTMESSAGE("unknown platform with usRevId=%d, ipVersion=%d\n", (int)m_plt.usRevId, (int)m_plt.ipVersion); | |
| 50 | } | |
| 51 | } | |
| 52 | ||
| 53 | VAStatus MediaCapsTableSpecific::Init() | |
| 54 | { | |
| 55 | DDI_FUNCTION_ENTER(); | |
| 56 | ||
| 57 | for (auto profileMapIter: *m_profileMap) | |
| 58 | { | |
| 59 | auto profile = profileMapIter.first; | |
| 60 | for(auto entrypointMapIter: *profileMapIter.second) | |
| 61 | { | |
| 62 | auto entrypoint = entrypointMapIter.first; | |
| 63 | auto entrypointData = entrypointMapIter.second; | |
| 64 | auto attriblist = entrypointData->attribList; | |
| 65 | auto componentData = entrypointData->configDataList; | |
| 66 | int32_t numAttribList = attriblist->size(); | |
| 67 | ||
| 68 | for(int i = 0; i < componentData->size(); i++) | |
| 69 | { | |
| 70 | auto configData = componentData->at(i); | |
| 71 | m_configList.emplace_back(profile, entrypoint, attriblist->data(), numAttribList, configData); | |
| 72 | } | |
| 73 | } | |
| 74 | } | |
| 75 | ||
| 76 | return VA_STATUS_SUCCESS; | |
| 77 | } | |
| 78 | ||
| 79 | VAStatus MediaCapsTableSpecific::QueryConfigProfiles( | |
| 80 | VAProfile *profileList, | |
| 81 | int32_t *profilesNum) | |
| 82 | { | |
| 83 | DDI_FUNCTION_ENTER(); | |
| 84 | ||
| 85 | DDI_CHK_NULL(profileList, "Null pointer", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 86 | DDI_CHK_NULL(profilesNum, "Null pointer", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 87 | ||
| 88 | int i = 0; | |
| 89 | ||
| 90 | if(m_profileMap->size() <= 0) | |
| 91 | { | |
| 92 | return VA_STATUS_ERROR_INVALID_CONFIG; | |
| 93 | } | |
| 94 | ||
| 95 | for (auto it = m_profileMap->begin(); it!=m_profileMap->end(); ++it) | |
| 96 | { | |
| 97 | profileList[i++] = (VAProfile)(it->first); | |
| 98 | } | |
| 99 | *profilesNum = m_profileMap->size(); | |
| 100 | return VA_STATUS_SUCCESS; | |
| 101 | } | |
| 102 | ||
| 103 | EntrypointMap* MediaCapsTableSpecific::QueryConfigEntrypointsMap( | |
| 104 | VAProfile profile) | |
| 105 | { | |
| 106 | DDI_FUNCTION_ENTER(); | |
| 107 | ||
| 108 | int i = 0; | |
| 109 | ||
| 110 | if(m_profileMap->find(profile) == m_profileMap->end()) | |
| 111 | { | |
| 112 | return nullptr; | |
| 113 | } | |
| 114 | ||
| 115 | return m_profileMap->at(profile); | |
| 116 | } | |
| 117 | ||
| 118 | AttribList* MediaCapsTableSpecific::QuerySupportedAttrib( | |
| 119 | VAProfile profile, | |
| 120 | VAEntrypoint entrypoint) | |
| 121 | { | |
| 122 | DDI_FUNCTION_ENTER(); | |
| 123 | ||
| 124 | if(m_profileMap->find(profile) == m_profileMap->end() || | |
| 125 | m_profileMap->at(profile)->find(entrypoint) == m_profileMap->at(profile)->end()) | |
| 126 | { | |
| 127 | return nullptr; | |
| 128 | } | |
| 129 | ||
| 130 | return m_profileMap->at(profile)->at(entrypoint)->attribList; | |
| 131 | } | |
| 132 | ||
| 133 | ConfigList* MediaCapsTableSpecific::GetConfigList() | |
| 134 | { | |
| 135 | DDI_FUNCTION_ENTER(); | |
| 136 | ||
| 137 | return &m_configList; | |
| 138 | } | |
| 139 | ||
| 140 | ConfigLinux* MediaCapsTableSpecific::QueryConfigItemFromIndex( | |
| 141 | VAConfigID configId) | |
| 142 | { | |
| 143 | DDI_FUNCTION_ENTER(); | |
| 144 | ||
| 145 | if (configId >= m_configList.size()) | |
| 146 | { | |
| 147 | return nullptr; | |
| 148 | } | |
| 149 | ||
| 150 | return &m_configList[configId]; | |
| 151 | } | |
| 152 | ||
| 153 | VAStatus MediaCapsTableSpecific::CreateConfig( | |
| 154 | VAProfile profile, | |
| 155 | VAEntrypoint entrypoint, | |
| 156 | VAConfigAttrib *attribList, | |
| 157 | int32_t numAttribs, | |
| 158 | VAConfigID *configId) | |
| 159 | { | |
| 160 | DDI_FUNCTION_ENTER(); | |
| 161 | ||
| 162 | DDI_CHK_NULL(attribList, "Null pointer", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 163 | DDI_CHK_NULL(configId, "Null pointer", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 164 | ||
| 165 | bool sameConfig = false; | |
| 166 | for (auto configItem : m_configList) | |
| 167 | { | |
| 168 | // check profile, entrypoint here, check attribute in caps_next | |
| 169 | // check component specific and return configId in component function | |
| 170 | if (configItem.profile == profile && | |
| 171 | configItem.entrypoint == entrypoint) | |
| 172 | { | |
| 173 | sameConfig = true; | |
| 174 | break; | |
| 175 | } | |
| 176 | } | |
| 177 | ||
| 178 | return sameConfig ? VA_STATUS_SUCCESS : VA_STATUS_ERROR_INVALID_VALUE; | |
| 179 | } | |
| 180 | ||
| 181 | VAStatus MediaCapsTableSpecific::DestroyConfig(VAConfigID configId) | |
| 182 | { | |
| 183 | DDI_FUNCTION_ENTER(); | |
| 184 | ||
| 185 | if(configId < m_configList.size()) | |
| 186 | { | |
| 187 | return VA_STATUS_SUCCESS; | |
| 188 | } | |
| 189 | ||
| 190 | return VA_STATUS_ERROR_INVALID_CONFIG; | |
| 191 | } | |
| 192 | ||
| 193 | ImgTable* MediaCapsTableSpecific::GetImgTable() | |
| 194 | { | |
| 195 | DDI_FUNCTION_ENTER(); | |
| 196 | ||
| 197 | return m_imgTbl; | |
| 198 | } | |
| 199 | ||
| 200 | uint32_t MediaCapsTableSpecific::GetImageFormatsMaxNum() | |
| 201 | { | |
| 202 | DDI_FUNCTION_ENTER(); | |
| 203 | ||
| 204 | return m_imgTbl->size(); | |
| 205 | } | |
| 206 | ||
| 207 | ProfileSurfaceAttribInfo* MediaCapsTableSpecific::QuerySurfaceAttributesFromConfigId( | |
| 208 | VAConfigID configId) | |
| 209 | { | |
| 210 | DDI_FUNCTION_ENTER(); | |
| 211 | ||
| 212 | ConfigLinux* configItem = nullptr; | |
| 213 | configItem = QueryConfigItemFromIndex(configId); | |
| 214 | DDI_CHK_NULL(configItem, "Invalid config id!", nullptr); | |
| 215 | ||
| 216 | VAProfile profile = configItem->profile; | |
| 217 | VAEntrypoint entrypoint = configItem->entrypoint; | |
| 218 | ||
| 219 | uint32_t i = 0; | |
| 220 | ||
| 221 | if (m_profileMap->find(profile) == m_profileMap->end() || | |
| 222 | m_profileMap->at(profile)->find(entrypoint) == m_profileMap->at(profile)->end()) | |
| 223 | { | |
| 224 | return nullptr; | |
| 225 | } | |
| 226 | ||
| 227 | return m_profileMap->at(profile)->at(entrypoint)->surfaceAttrib; | |
| 228 | } |
| 0 | /* | |
| 1 | * Copyright (c) 2021, Intel Corporation | |
| 2 | * | |
| 3 | * Permission is hereby granted, free of charge, to any person obtaining a | |
| 4 | * copy of this software and associated documentation files (the "Software"), | |
| 5 | * to deal in the Software without restriction, including without limitation | |
| 6 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 7 | * and/or sell copies of the Software, and to permit persons to whom the | |
| 8 | * Software is furnished to do so, subject to the following conditions: | |
| 9 | * | |
| 10 | * The above copyright notice and this permission notice shall be included | |
| 11 | * in all copies or substantial portions of the Software. | |
| 12 | * | |
| 13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 14 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 15 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 16 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 17 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 18 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 19 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 20 | */ | |
| 21 | //! | |
| 22 | //! \file media_capstable_specific.h | |
| 23 | //! \brief Header file of media caps table class on specific os | |
| 24 | //! | |
| 25 | ||
| 26 | #ifndef __MEDIA_CAPSTABLE_LINUX_H__ | |
| 27 | #define __MEDIA_CAPSTABLE_LINUX_H__ | |
| 28 | ||
| 29 | #include <vector> | |
| 30 | #include <map> | |
| 31 | #include <set> | |
| 32 | ||
| 33 | #include "va/va.h" | |
| 34 | #include "media_libva_common.h" | |
| 35 | #include "capstable_data_linux_definition.h" | |
| 36 | #include "media_capstable.h" | |
| 37 | ||
| 38 | //! | |
| 39 | //! \class ConfigLinux | |
| 40 | //! \brief Config for Linux caps | |
| 41 | //! | |
| 42 | struct ConfigLinux | |
| 43 | { | |
| 44 | VAProfile profile = VAProfileNone; | |
| 45 | VAEntrypoint entrypoint = VAEntrypointVLD; | |
| 46 | VAConfigAttrib *attribList = nullptr; | |
| 47 | int32_t numAttribs = 0; | |
| 48 | ComponentData componentData = {}; | |
| 49 | ||
| 50 | ConfigLinux( | |
| 51 | VAProfile p, | |
| 52 | VAEntrypoint e, | |
| 53 | VAConfigAttrib *a, | |
| 54 | int32_t n, | |
| 55 | ComponentData c) : profile(p), entrypoint(e), attribList(a), numAttribs(n), componentData(c){} | |
| 56 | ConfigLinux(){} | |
| 57 | }; | |
| 58 | ||
| 59 | typedef std::vector<ConfigLinux> ConfigList; | |
| 60 | ||
| 61 | #define CONFIG_ATTRIB_NONE 0x00000000 | |
| 62 | ||
| 63 | //! | |
| 64 | //! \class MediaLibvaCaps | |
| 65 | //! \brief Media libva caps | |
| 66 | //! | |
| 67 | class MediaCapsTableSpecific : public MediaCapsTable<CapsData> | |
| 68 | { | |
| 69 | private: | |
| 70 | PlatformInfo m_plt; | |
| 71 | ProfileMap *m_profileMap = nullptr; | |
| 72 | ImgTable *m_imgTbl = nullptr; | |
| 73 | ||
| 74 | public: | |
| 75 | //! | |
| 76 | //! \brief Store config | |
| 77 | //! | |
| 78 | ConfigList m_configList = {}; | |
| 79 | ||
| 80 | //! | |
| 81 | //! \brief Constructor | |
| 82 | //! | |
| 83 | MediaCapsTableSpecific(HwDeviceInfo &deviceInfo); | |
| 84 | ||
| 85 | //! | |
| 86 | //! \brief Destructor | |
| 87 | //! | |
| 88 | ~MediaCapsTableSpecific() {}; | |
| 89 | ||
| 90 | //! | |
| 91 | //! \brief Init configlist | |
| 92 | //! | |
| 93 | VAStatus Init(); | |
| 94 | ||
| 95 | //! | |
| 96 | //! \brief Get configlist, this is for component createConfig | |
| 97 | //! | |
| 98 | ConfigList* GetConfigList(); | |
| 99 | ||
| 100 | //! | |
| 101 | //! \brief Get Image Table | |
| 102 | //! | |
| 103 | //! \return ImgTable | |
| 104 | //! | |
| 105 | ImgTable* GetImgTable(); | |
| 106 | ||
| 107 | //! | |
| 108 | //! \brief Get Supported Attrib Value | |
| 109 | //! | |
| 110 | //! \param [in] profile | |
| 111 | //! VA profile | |
| 112 | //! | |
| 113 | //! \param [in] entrypoint | |
| 114 | //! VA entrypoint | |
| 115 | //! | |
| 116 | //! \return AttribList* | |
| 117 | //! nullptr if query failed | |
| 118 | //! | |
| 119 | AttribList* QuerySupportedAttrib( | |
| 120 | VAProfile profile, | |
| 121 | VAEntrypoint entrypoint); | |
| 122 | ||
| 123 | //! | |
| 124 | //! \brief Get specific config item | |
| 125 | //! | |
| 126 | //! \param [in] configId | |
| 127 | //! config list index | |
| 128 | //! | |
| 129 | //! \return ConfigLinux | |
| 130 | //! nullptr if invalid index | |
| 131 | //! | |
| 132 | ConfigLinux* QueryConfigItemFromIndex( | |
| 133 | VAConfigID configId); | |
| 134 | ||
| 135 | //! | |
| 136 | //! \brief Create a configuration | |
| 137 | //! \details It passes in the attribute list that specifies the attributes it | |
| 138 | //! cares about, with the rest taking default values. | |
| 139 | //! | |
| 140 | //! \param [in] profile | |
| 141 | //! VA profile | |
| 142 | //! | |
| 143 | //! \param [in] entrypoint | |
| 144 | //! VA entrypoint | |
| 145 | //! | |
| 146 | //! \param [in] attribList | |
| 147 | //! Pointer to VAConfigAttrib array that specifies the attributes | |
| 148 | //! | |
| 149 | //! \param [in] numAttribs | |
| 150 | //! Number of VAConfigAttrib in the array attribList | |
| 151 | //! | |
| 152 | //! \param [out] configId | |
| 153 | //! Pointer to returned VAConfigID if success | |
| 154 | //! | |
| 155 | //! \return VAStatus | |
| 156 | //! VA_STATUS_SUCCESS if success | |
| 157 | //! | |
| 158 | VAStatus CreateConfig( | |
| 159 | VAProfile profile, | |
| 160 | VAEntrypoint entrypoint, | |
| 161 | VAConfigAttrib *attribList, | |
| 162 | int32_t numAttribs, | |
| 163 | VAConfigID *configId); | |
| 164 | ||
| 165 | //! | |
| 166 | //! \brief Destory the VAConfigID | |
| 167 | //! | |
| 168 | //! \param [in] configId | |
| 169 | //! Specify the VAConfigID | |
| 170 | //! | |
| 171 | //! \return VAStatus | |
| 172 | //! VA_STATUS_SUCCESS if succeed | |
| 173 | //! VA_STATUS_ERROR_INVALID_CONFIG if the conifgId is invalid | |
| 174 | //! | |
| 175 | VAStatus DestroyConfig(VAConfigID configId); | |
| 176 | ||
| 177 | //! | |
| 178 | //! \brief Query EntrypointsMap | |
| 179 | //! | |
| 180 | //! \param [in] configId | |
| 181 | //! | |
| 182 | //! \return EntrypointMap* | |
| 183 | //! nullptr if invalid profile | |
| 184 | //! | |
| 185 | EntrypointMap* QueryConfigEntrypointsMap( | |
| 186 | VAProfile profile); | |
| 187 | ||
| 188 | //! | |
| 189 | //! \brief Query supported profiles | |
| 190 | //! | |
| 191 | //! \param [in] profileList | |
| 192 | //! Pointer to VAProfile array that can hold at least vaMaxNumProfile() entries | |
| 193 | //! | |
| 194 | //! \param [out] numProfiles | |
| 195 | //! Pointer to int32_t. It returns the actual number of supported profiles. | |
| 196 | //! | |
| 197 | //! \return VAStatus | |
| 198 | //! VA_STATUS_SUCCESS if success | |
| 199 | //! | |
| 200 | VAStatus QueryConfigProfiles( | |
| 201 | VAProfile *profileList, | |
| 202 | int32_t *profilesNum); | |
| 203 | ||
| 204 | //! | |
| 205 | //! \brief Query SurfaceAttributes From ConfigId | |
| 206 | //! | |
| 207 | //! \param [in] configId | |
| 208 | //! Supported surface attrib | |
| 209 | //! | |
| 210 | //! \return ProfileSurfaceAttribInfo* | |
| 211 | //! nullptr if invalid configid | |
| 212 | //! | |
| 213 | ProfileSurfaceAttribInfo* QuerySurfaceAttributesFromConfigId( | |
| 214 | VAConfigID configId); | |
| 215 | ||
| 216 | //! | |
| 217 | //! \brief Return the maxinum number of supported image formats for current platform ipVersion | |
| 218 | //! | |
| 219 | //! \return The maxinum number of supported image formats for current platform ipVersion | |
| 220 | //! | |
| 221 | uint32_t GetImageFormatsMaxNum(); | |
| 222 | }; | |
| 223 | ||
| 224 | #endif //__MEDIA_CAPSTABLE_LINUX_H__ |
| 57 | 57 | } |
| 58 | 58 | } |
| 59 | 59 | |
| 60 | std::vector<ConfigLinux>* MediaLibvaCapsNext::GetConfigList() | |
| 60 | ConfigList* MediaLibvaCapsNext::GetConfigList() | |
| 61 | 61 | { |
| 62 | 62 | return m_capsTable->GetConfigList(); |
| 63 | 63 | } |
| 26 | 26 | #ifndef __MEDIA_LIBVA_CAPS_NEXT_H__ |
| 27 | 27 | #define __MEDIA_LIBVA_CAPS_NEXT_H__ |
| 28 | 28 | |
| 29 | #include "media_capstable_linux.h" | |
| 29 | #include "media_capstable_specific.h" | |
| 30 | 30 | #include "media_libva_common_next.h" |
| 31 | 31 | |
| 32 | 32 | class MediaLibvaCapsNext |
| 46 | 46 | //! |
| 47 | 47 | //! \brief Get configlist for create configs |
| 48 | 48 | //! |
| 49 | //! \return std::vector<ConfigLinux>* | |
| 50 | //! | |
| 51 | std::vector<ConfigLinux>* GetConfigList(); | |
| 49 | //! \return All supported ConfigLinuxList | |
| 50 | //! | |
| 51 | ConfigList* GetConfigList(); | |
| 52 | 52 | |
| 53 | 53 | //! |
| 54 | 54 | //! \brief Get Attrib Value |
| 142 | 142 | bool outputCompressed); |
| 143 | 143 | |
| 144 | 144 | PLATFORM platform = {}; |
| 145 | ||
| 146 | MediaLibvaCaps *m_caps = false; | |
| 147 | ||
| 145 | MediaLibvaCapsNext *m_capsNext = nullptr; | |
| 148 | 146 | GMM_CLIENT_CONTEXT *pGmmClientContext = nullptr; |
| 149 | ||
| 150 | GmmExportEntries GmmFuncs = {}; | |
| 147 | GmmExportEntries GmmFuncs = {}; | |
| 151 | 148 | |
| 152 | 149 | // Aux Table Manager |
| 153 | 150 | AuxTableMgr *m_auxTableMgr = nullptr; |
| 154 | ||
| 155 | 151 | bool m_useSwSwizzling = false; |
| 156 | 152 | bool m_tileYFlag = false; |
| 157 | 153 |
| 33 | 33 | #include "media_libva.h" |
| 34 | 34 | #include "mos_utilities.h" |
| 35 | 35 | #include "media_interfaces_mmd.h" |
| 36 | #include "media_libva_caps.h" | |
| 36 | #include "media_libva_caps_next.h" | |
| 37 | 37 | #include "media_ddi_prot.h" |
| 38 | 38 | #include "media_interfaces_hwinfo_device.h" |
| 39 | 39 | #include "mos_oca_interface_specific.h" |
| 317 | 317 | VAStatus MediaLibvaInterfaceNext::Initialize ( |
| 318 | 318 | VADriverContextP ctx, |
| 319 | 319 | int32_t devicefd, |
| 320 | int32_t *major_version, | |
| 321 | int32_t *minor_version | |
| 320 | int32_t *major_version, | |
| 321 | int32_t *minor_version | |
| 322 | 322 | ) |
| 323 | 323 | { |
| 324 | 324 | DDI_FUNCTION_ENTER(); |
| 423 | 423 | return VA_STATUS_ERROR_ALLOCATION_FAILED; |
| 424 | 424 | } |
| 425 | 425 | |
| 426 | //Caps need platform and sku table, especially in MediaLibvaCapsCp::IsDecEncryptionSupported | |
| 427 | mediaCtx->m_caps = MediaLibvaCaps::CreateMediaLibvaCaps(mediaCtx); | |
| 428 | if (!mediaCtx->m_caps) | |
| 426 | mediaCtx->m_hwInfo = MediaInterfacesHwInfoDevice::CreateFactory(mediaCtx->platform); | |
| 427 | mediaCtx->m_capsNext = MediaLibvaCapsNext::CreateCaps(mediaCtx); | |
| 428 | if (!mediaCtx->m_capsNext) | |
| 429 | 429 | { |
| 430 | 430 | DDI_ASSERTMESSAGE("Caps create failed. Not supported GFX device."); |
| 431 | 431 | DestroyMediaContextMutex(mediaCtx); |
| 433 | 433 | return VA_STATUS_ERROR_ALLOCATION_FAILED; |
| 434 | 434 | } |
| 435 | 435 | |
| 436 | if (mediaCtx->m_caps->Init() != VA_STATUS_SUCCESS) | |
| 437 | { | |
| 438 | DDI_ASSERTMESSAGE("Caps init failed. Not supported GFX device."); | |
| 439 | MOS_Delete(mediaCtx->m_caps); | |
| 440 | mediaCtx->m_caps = nullptr; | |
| 441 | DestroyMediaContextMutex(mediaCtx); | |
| 442 | FreeForMediaContext(mediaCtx); | |
| 443 | return VA_STATUS_ERROR_ALLOCATION_FAILED; | |
| 444 | } | |
| 445 | ctx->max_image_formats = mediaCtx->m_caps->GetImageFormatsMaxNum(); | |
| 436 | ctx->max_image_formats = mediaCtx->m_capsNext->GetImageFormatsMaxNum(); | |
| 446 | 437 | |
| 447 | 438 | #if !defined(ANDROID) && defined(X11_FOUND) |
| 448 | 439 | DdiMediaUtil_InitMutex(&mediaCtx->PutSurfaceRenderMutex); |
| 469 | 460 | if (InitCompList(mediaCtx) != VA_STATUS_SUCCESS) |
| 470 | 461 | { |
| 471 | 462 | DDI_ASSERTMESSAGE("Caps init failed. Not supported GFX device."); |
| 472 | MOS_Delete(mediaCtx->m_caps); | |
| 473 | mediaCtx->m_caps = nullptr; | |
| 463 | MOS_Delete(mediaCtx->m_capsNext); | |
| 464 | mediaCtx->m_capsNext = nullptr; | |
| 474 | 465 | DestroyMediaContextMutex(mediaCtx); |
| 475 | 466 | ReleaseCompList(mediaCtx); |
| 476 | 467 | FreeForMediaContext(mediaCtx); |
| 477 | 468 | return VA_STATUS_ERROR_ALLOCATION_FAILED; |
| 478 | 469 | } |
| 479 | ||
| 480 | mediaCtx->m_hwInfo = MediaInterfacesHwInfoDevice::CreateFactory(mediaCtx->platform, &mediaCtx->WaTable); | |
| 481 | 470 | |
| 482 | 471 | DdiMediaUtil_UnLockMutex(&m_GlobalMutex); |
| 483 | 472 | |
| 766 | 755 | DdiMediaUtil_DestroyMutex(&mediaCtx->PutSurfaceRenderMutex); |
| 767 | 756 | DdiMediaUtil_DestroyMutex(&mediaCtx->PutSurfaceSwapBufferMutex); |
| 768 | 757 | |
| 769 | if (mediaCtx->m_caps) | |
| 758 | if (mediaCtx->m_capsNext) | |
| 770 | 759 | { |
| 771 | 760 | if (mediaCtx->dri_output != nullptr) |
| 772 | 761 | { |
| 781 | 770 | } |
| 782 | 771 | #endif |
| 783 | 772 | |
| 784 | if (mediaCtx->m_caps) | |
| 785 | { | |
| 786 | MOS_Delete(mediaCtx->m_caps); | |
| 787 | mediaCtx->m_caps = nullptr; | |
| 773 | if (mediaCtx->m_capsNext) | |
| 774 | { | |
| 775 | MOS_Delete(mediaCtx->m_capsNext); | |
| 776 | mediaCtx->m_capsNext = nullptr; | |
| 788 | 777 | } |
| 789 | 778 | //destory resources |
| 790 | 779 | FreeSurfaceHeapElements(mediaCtx); |
| 972 | 961 | bool MediaLibvaInterfaceNext::DsoGetSymbols( |
| 973 | 962 | struct dso_handle *h, |
| 974 | 963 | void *vtable, |
| 975 | uint32_t vtable_length, | |
| 964 | uint32_t vtable_length, | |
| 976 | 965 | const struct dso_symbol *symbols |
| 977 | 966 | ) |
| 978 | 967 | { |
| 1051 | 1040 | ctx->str_vendor = DDI_CODEC_GEN_STR_VENDOR; |
| 1052 | 1041 | ctx->vtable_tpi = nullptr; |
| 1053 | 1042 | |
| 1043 | pVTable->vaTerminate = Terminate; | |
| 1044 | ||
| 1045 | pVTable->vaQueryConfigEntrypoints = QueryConfigEntrypoints; | |
| 1046 | pVTable->vaQueryConfigProfiles = QueryConfigProfiles; | |
| 1047 | pVTable->vaQueryConfigAttributes = QueryConfigAttributes; | |
| 1048 | pVTable->vaCreateConfig = CreateConfig; | |
| 1049 | pVTable->vaDestroyConfig = DestroyConfig; | |
| 1050 | pVTable->vaGetConfigAttributes = GetConfigAttributes; | |
| 1051 | pVTable->vaQuerySurfaceAttributes = QuerySurfaceAttributes; | |
| 1052 | pVTable->vaQueryImageFormats = QueryImageFormats; | |
| 1053 | ||
| 1054 | 1054 | pVTable->vaCreateConfig = CreateConfig; |
| 1055 | 1055 | pVTable->vaCreateContext = CreateContext; |
| 1056 | 1056 | pVTable->vaDestroyContext = DestroyContext; |
| 1264 | 1264 | return vaStatus; |
| 1265 | 1265 | } |
| 1266 | 1266 | |
| 1267 | VAStatus MediaLibvaInterfaceNext::CreateConfig ( | |
| 1267 | VAStatus MediaLibvaInterfaceNext::QueryConfigEntrypoints( | |
| 1268 | VADriverContextP ctx, | |
| 1269 | VAProfile profile, | |
| 1270 | VAEntrypoint *entrypointList, | |
| 1271 | int32_t *entrypointsNum) | |
| 1272 | { | |
| 1273 | DDI_FUNCTION_ENTER(); | |
| 1274 | ||
| 1275 | PERF_UTILITY_START_ONCE("First Frame Time", PERF_MOS, PERF_LEVEL_DDI); | |
| 1276 | ||
| 1277 | DDI_CHK_NULL(ctx, "nullptr Ctx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1278 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1279 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1280 | DDI_CHK_NULL(mediaCtx->m_capsNext, "nullptr m_caps", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1281 | ||
| 1282 | DDI_CHK_NULL(entrypointList, "nullptr entrypointList", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1283 | DDI_CHK_NULL(entrypointsNum, "nullptr entrypointsNum", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1284 | ||
| 1285 | return mediaCtx->m_capsNext->QueryConfigEntrypoints(profile, entrypointList, entrypointsNum); | |
| 1286 | } | |
| 1287 | ||
| 1288 | VAStatus MediaLibvaInterfaceNext::QueryConfigProfiles( | |
| 1289 | VADriverContextP ctx, | |
| 1290 | VAProfile *profileList, | |
| 1291 | int32_t *profilesNum) | |
| 1292 | { | |
| 1293 | DDI_FUNCTION_ENTER(); | |
| 1294 | ||
| 1295 | DDI_CHK_NULL(ctx, "nullptr Ctx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1296 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1297 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1298 | DDI_CHK_NULL(mediaCtx->m_capsNext, "nullptr m_caps", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1299 | ||
| 1300 | DDI_CHK_NULL(profileList, "nullptr profileList", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1301 | DDI_CHK_NULL(profilesNum, "nullptr profilesNum", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1302 | ||
| 1303 | return mediaCtx->m_capsNext->QueryConfigProfiles(profileList, profilesNum); | |
| 1304 | } | |
| 1305 | ||
| 1306 | VAStatus MediaLibvaInterfaceNext::QueryConfigAttributes( | |
| 1307 | VADriverContextP ctx, | |
| 1308 | VAConfigID configId, | |
| 1309 | VAProfile *profile, | |
| 1310 | VAEntrypoint *entrypoint, | |
| 1311 | VAConfigAttrib *attribList, | |
| 1312 | int32_t *attribsNum) | |
| 1313 | { | |
| 1314 | DDI_FUNCTION_ENTER(); | |
| 1315 | ||
| 1316 | DDI_CHK_NULL(profile, "nullptr profile", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1317 | DDI_CHK_NULL(entrypoint, "nullptr entrypoint", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1318 | DDI_CHK_NULL(ctx, "nullptr ctx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1319 | DDI_CHK_NULL(attribList, "nullptr attribList", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1320 | DDI_CHK_NULL(attribsNum, "nullptr attribsNum", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1321 | ||
| 1322 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1323 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1324 | DDI_CHK_NULL(mediaCtx->m_capsNext, "nullptr m_caps", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1325 | ||
| 1326 | return mediaCtx->m_capsNext->QueryConfigAttributes( | |
| 1327 | configId, profile, entrypoint, attribList, attribsNum); | |
| 1328 | } | |
| 1329 | ||
| 1330 | VAStatus MediaLibvaInterfaceNext::CreateConfig( | |
| 1268 | 1331 | VADriverContextP ctx, |
| 1269 | 1332 | VAProfile profile, |
| 1270 | 1333 | VAEntrypoint entrypoint, |
| 1278 | 1341 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); |
| 1279 | 1342 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1280 | 1343 | |
| 1281 | return VA_STATUS_ERROR_UNIMPLEMENTED; | |
| 1344 | CompType componentIndex = MapCompTypeFromEntrypoint(entrypoint); | |
| 1345 | DDI_CHK_NULL(mediaCtx->m_compList[componentIndex], "nullptr complist", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1346 | ||
| 1347 | return mediaCtx->m_compList[componentIndex]->CreateConfig( | |
| 1348 | ctx, profile, entrypoint, attribList, attribsNum, configId); | |
| 1349 | } | |
| 1350 | ||
| 1351 | VAStatus MediaLibvaInterfaceNext::DestroyConfig( | |
| 1352 | VADriverContextP ctx, | |
| 1353 | VAConfigID configId) | |
| 1354 | { | |
| 1355 | DDI_FUNCTION_ENTER(); | |
| 1356 | ||
| 1357 | DDI_CHK_NULL(ctx, "nullptr ctx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1358 | ||
| 1359 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1360 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1361 | DDI_CHK_NULL(mediaCtx->m_capsNext, "nullptr m_caps", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1362 | ||
| 1363 | return mediaCtx->m_capsNext->DestroyConfig(configId); | |
| 1364 | } | |
| 1365 | ||
| 1366 | VAStatus MediaLibvaInterfaceNext::GetConfigAttributes( | |
| 1367 | VADriverContextP ctx, | |
| 1368 | VAProfile profile, | |
| 1369 | VAEntrypoint entrypoint, | |
| 1370 | VAConfigAttrib *attribList, | |
| 1371 | int32_t attribsNum) | |
| 1372 | { | |
| 1373 | DDI_FUNCTION_ENTER(); | |
| 1374 | ||
| 1375 | DDI_CHK_NULL(ctx, "nullptr ctx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1376 | DDI_CHK_NULL(attribList, "nullptr attribList", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1377 | ||
| 1378 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1379 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1380 | DDI_CHK_NULL(mediaCtx->m_capsNext, "nullptr m_caps", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1381 | ||
| 1382 | return mediaCtx->m_capsNext->GetConfigAttributes(profile, entrypoint, attribList, attribsNum); | |
| 1383 | } | |
| 1384 | ||
| 1385 | VAStatus MediaLibvaInterfaceNext::QuerySurfaceAttributes( | |
| 1386 | VADriverContextP ctx, | |
| 1387 | VAConfigID configId, | |
| 1388 | VASurfaceAttrib *attribList, | |
| 1389 | uint32_t *attribsNum) | |
| 1390 | { | |
| 1391 | DDI_FUNCTION_ENTER(); | |
| 1392 | ||
| 1393 | DDI_CHK_NULL(ctx, "nullptr ctx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1394 | DDI_CHK_NULL(attribsNum, "nullptr attribsNum", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1395 | DDI_CHK_NULL(attribList, "nullptr attribList", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1396 | ||
| 1397 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1398 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1399 | DDI_CHK_NULL(mediaCtx->m_capsNext, "nullptr m_caps", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1400 | ||
| 1401 | return mediaCtx->m_capsNext->QuerySurfaceAttributes(configId, attribList, attribsNum); | |
| 1402 | } | |
| 1403 | ||
| 1404 | VAStatus MediaLibvaInterfaceNext::QueryImageFormats( | |
| 1405 | VADriverContextP ctx, | |
| 1406 | VAImageFormat *formatList, | |
| 1407 | int32_t *formatsNum) | |
| 1408 | { | |
| 1409 | DDI_FUNCTION_ENTER(); | |
| 1410 | ||
| 1411 | DDI_CHK_NULL(ctx, "nullptr ctx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1412 | DDI_CHK_NULL(formatList, "nullptr formatList", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1413 | DDI_CHK_NULL(formatsNum, "nullptr formatsNum", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1414 | ||
| 1415 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1416 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 1417 | DDI_CHK_NULL(mediaCtx->m_capsNext, "nullptr caps", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 1418 | ||
| 1419 | return mediaCtx->m_capsNext->QueryImageFormats(formatList, formatsNum); | |
| 1420 | } | |
| 1421 | ||
| 1422 | CompType MediaLibvaInterfaceNext::MapCompTypeFromEntrypoint(VAEntrypoint entrypoint) | |
| 1423 | { | |
| 1424 | DDI_FUNCTION_ENTER(); | |
| 1425 | ||
| 1426 | switch(entrypoint) | |
| 1427 | { | |
| 1428 | case VAEntrypointEncSlice: | |
| 1429 | case VAEntrypointEncSliceLP: | |
| 1430 | case VAEntrypointEncPicture: | |
| 1431 | case VAEntrypointFEI: | |
| 1432 | case VAEntrypointStats: | |
| 1433 | return CompEncode; | |
| 1434 | case VAEntrypointVLD: | |
| 1435 | return CompDecode; | |
| 1436 | case VAEntrypointVideoProc: | |
| 1437 | return CompVp; | |
| 1438 | case VAEntrypointProtectedContent: | |
| 1439 | case VAEntrypointProtectedTEEComm: | |
| 1440 | return CompCp; | |
| 1441 | default: | |
| 1442 | return CompCommon; | |
| 1443 | } | |
| 1282 | 1444 | } |
| 1283 | 1445 | |
| 1284 | 1446 | VAStatus MediaLibvaInterfaceNext::QueryVideoProcFilters( |
| 1337 | 1499 | { |
| 1338 | 1500 | DDI_FUNCTION_ENTER(); |
| 1339 | 1501 | DDI_CHK_NULL(ctx, "nullptr ctx", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1340 | PDDI_MEDIA_CONTEXT mediaCtx = DdiMedia_GetMediaContext(ctx); | |
| 1502 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1341 | 1503 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1342 | 1504 | DDI_CHK_NULL(mediaCtx->m_compList[CompCp], "nullptr complist", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1343 | 1505 | |
| 1350 | 1512 | { |
| 1351 | 1513 | DDI_FUNCTION_ENTER(); |
| 1352 | 1514 | DDI_CHK_NULL(ctx, "nullptr ctx", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1353 | PDDI_MEDIA_CONTEXT mediaCtx = DdiMedia_GetMediaContext(ctx); | |
| 1515 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1354 | 1516 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1355 | 1517 | DDI_CHK_NULL(mediaCtx->m_compList[CompCp], "nullptr complist", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1356 | 1518 | |
| 1364 | 1526 | { |
| 1365 | 1527 | DDI_FUNCTION_ENTER(); |
| 1366 | 1528 | DDI_CHK_NULL(ctx, "nullptr ctx", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1367 | PDDI_MEDIA_CONTEXT mediaCtx = DdiMedia_GetMediaContext(ctx); | |
| 1529 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1368 | 1530 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1369 | 1531 | DDI_CHK_NULL(mediaCtx->m_compList[CompCp], "nullptr complist", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1370 | 1532 | |
| 1377 | 1539 | { |
| 1378 | 1540 | DDI_FUNCTION_ENTER(); |
| 1379 | 1541 | DDI_CHK_NULL(ctx, "nullptr ctx", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1380 | PDDI_MEDIA_CONTEXT mediaCtx = DdiMedia_GetMediaContext(ctx); | |
| 1542 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1381 | 1543 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1382 | 1544 | DDI_CHK_NULL(mediaCtx->m_compList[CompCp], "nullptr complist", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1383 | 1545 | |
| 1391 | 1553 | { |
| 1392 | 1554 | DDI_FUNCTION_ENTER(); |
| 1393 | 1555 | DDI_CHK_NULL(ctx, "nullptr ctx", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1394 | PDDI_MEDIA_CONTEXT mediaCtx = DdiMedia_GetMediaContext(ctx); | |
| 1556 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 1395 | 1557 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1396 | 1558 | DDI_CHK_NULL(mediaCtx->m_compList[CompCp], "nullptr complist", VA_STATUS_ERROR_INVALID_CONTEXT); |
| 1397 | 1559 | |
| 51 | 51 | static VAStatus Initialize ( |
| 52 | 52 | VADriverContextP ctx, |
| 53 | 53 | int32_t devicefd, |
| 54 | int32_t *major_version, /* out */ | |
| 55 | int32_t *minor_version /* out */ | |
| 54 | int32_t *major_version, /* out */ | |
| 55 | int32_t *minor_version /* out */ | |
| 56 | 56 | ); |
| 57 | 57 | |
| 58 | 58 | //! |
| 207 | 207 | ); |
| 208 | 208 | |
| 209 | 209 | //! |
| 210 | //! \brief Create a configuration for the encode/decode/vp pipeline | |
| 211 | //! \details it passes in the attribute list that specifies the attributes it cares | |
| 212 | //! about, with the rest taking default values. | |
| 213 | //! | |
| 214 | //! \param [in] ctx | |
| 215 | //! Pointer to VA driver context | |
| 216 | //! \param [in] profile | |
| 217 | //! VA profile of configuration | |
| 218 | //! \param [in] entrypoint | |
| 219 | //! VA entrypoint of configuration | |
| 220 | //! \param [out] attribList | |
| 221 | //! VA attrib list | |
| 222 | //! \param [out] attribsNum | |
| 223 | //! Number of attribs | |
| 224 | //! \param [out] configId | |
| 225 | //! VA config id | |
| 226 | //! | |
| 227 | //! \return VAStatus | |
| 228 | //! VA_STATUS_SUCCESS if success, else fail reason | |
| 229 | //! | |
| 230 | static VAStatus CreateConfig ( | |
| 210 | //! \brief Query supported entrypoints for a given profile | |
| 211 | //! | |
| 212 | //! \param [in] ctx | |
| 213 | //! Pointer to VA driver context | |
| 214 | //! \param [in] profile | |
| 215 | //! VA profile | |
| 216 | //! \param [in] entrypointList | |
| 217 | //! Pointer to VAEntrypoint array that can hold at least vaMaxNumEntrypoints() entries | |
| 218 | //! \param [out] numEntryPoints | |
| 219 | //! It returns the actual number of supported VAEntrypoints. | |
| 220 | //! | |
| 221 | //! \return VAStatus | |
| 222 | //! VA_STATUS_SUCCESS if success | |
| 223 | //! | |
| 224 | static VAStatus QueryConfigEntrypoints( | |
| 225 | VADriverContextP ctx, | |
| 226 | VAProfile profile, | |
| 227 | VAEntrypoint *entrypointList, | |
| 228 | int32_t *entrypointsNum); | |
| 229 | ||
| 230 | //! | |
| 231 | //! \brief Query supported profiles | |
| 232 | //! | |
| 233 | //! \param [in] ctx | |
| 234 | //! Pointer to VA driver context | |
| 235 | //! \param [in] profileList | |
| 236 | //! Pointer to VAProfile array that can hold at least vaMaxNumProfile() entries | |
| 237 | //! \param [out] numProfiles | |
| 238 | //! Pointer to int32_t. It returns the actual number of supported profiles. | |
| 239 | //! | |
| 240 | //! \return VAStatus | |
| 241 | //! VA_STATUS_SUCCESS if success | |
| 242 | //! | |
| 243 | static VAStatus QueryConfigProfiles( | |
| 244 | VADriverContextP ctx, | |
| 245 | VAProfile *profile_list, | |
| 246 | int32_t *num_profiles); | |
| 247 | ||
| 248 | //! | |
| 249 | //! \brief Query all attributes for a given configuration | |
| 250 | //! | |
| 251 | //! \param [in] ctx | |
| 252 | //! Pointer to VA driver context | |
| 253 | //! \param [in] configId | |
| 254 | //! VA configuration | |
| 255 | //! \param [in,out] profile | |
| 256 | //! Pointer to VAProfile of the configuration | |
| 257 | //! \param [in,out] entrypoint | |
| 258 | //! Pointer to VAEntrypoint of the configuration | |
| 259 | //! \param [in,out] attribList | |
| 260 | //! Pointer to VAConfigAttrib array that can hold at least | |
| 261 | //! vaMaxNumConfigAttributes() entries. | |
| 262 | //! \param [in,out] numAttribs | |
| 263 | //! The actual number of VAConfigAttrib returned in the array attribList | |
| 264 | //! | |
| 265 | //! \return VAStatus | |
| 266 | //! VA_STATUS_SUCCESS if success | |
| 267 | //! | |
| 268 | static VAStatus QueryConfigAttributes( | |
| 269 | VADriverContextP ctx, | |
| 270 | VAConfigID configId, | |
| 271 | VAProfile *profile, | |
| 272 | VAEntrypoint *entrypoint, | |
| 273 | VAConfigAttrib *attribList, | |
| 274 | int32_t *numAttribs); | |
| 275 | ||
| 276 | //! | |
| 277 | //! \brief Create a configuration | |
| 278 | //! \details It passes in the attribute list that specifies the attributes it | |
| 279 | //! cares about, with the rest taking default values. | |
| 280 | //! | |
| 281 | //! \param [in] ctx | |
| 282 | //! Pointer to VA driver context | |
| 283 | //! \param [in] profile | |
| 284 | //! VA profile | |
| 285 | //! \param [in] entrypoint | |
| 286 | //! VA entrypoint | |
| 287 | //! \param [in] attribList | |
| 288 | //! Pointer to VAConfigAttrib array that specifies the attributes | |
| 289 | //! \param [in] numAttribs | |
| 290 | //! Number of VAConfigAttrib in the array attribList | |
| 291 | //! \param [out] configId | |
| 292 | //! Pointer to returned VAConfigID if success | |
| 293 | //! | |
| 294 | //! \return VAStatus | |
| 295 | //! VA_STATUS_SUCCESS if success | |
| 296 | //! | |
| 297 | static VAStatus CreateConfig( | |
| 231 | 298 | VADriverContextP ctx, |
| 232 | 299 | VAProfile profile, |
| 233 | 300 | VAEntrypoint entrypoint, |
| 234 | 301 | VAConfigAttrib *attribList, |
| 235 | int32_t attribsNum, | |
| 236 | VAConfigID *configId | |
| 237 | ); | |
| 302 | int32_t numAttribs, | |
| 303 | VAConfigID *configId); | |
| 304 | ||
| 305 | //! | |
| 306 | //! \brief Destory the VAConfigID | |
| 307 | //! | |
| 308 | //! \param [in] ctx | |
| 309 | //! Pointer to VA driver context | |
| 310 | //! \param [in] configId | |
| 311 | //! Specify the VAConfigID | |
| 312 | //! | |
| 313 | //! \return VAStatus | |
| 314 | //! VA_STATUS_SUCCESS if succeed | |
| 315 | //! VA_STATUS_ERROR_INVALID_CONFIG if the conifgId is invalid | |
| 316 | //! | |
| 317 | static VAStatus DestroyConfig( | |
| 318 | VADriverContextP ctx, | |
| 319 | VAConfigID configId); | |
| 320 | ||
| 321 | //! | |
| 322 | //! \brief Get attributes for a given profile/entrypoint pair | |
| 323 | //! \details The caller must provide an "attribList" with all attributes to be | |
| 324 | //! retrieved. Upon return, the attributes in "attribList" have been | |
| 325 | //! updated with their value. Unknown attributes or attributes that are | |
| 326 | //! not supported for the given profile/entrypoint pair will have their | |
| 327 | //! value set to VA_ATTRIB_NOT_SUPPORTED. | |
| 328 | //! | |
| 329 | //! \param [in] ctx | |
| 330 | //! Pointer to VA driver context | |
| 331 | //! \param [in] profile | |
| 332 | //! VA profile | |
| 333 | //! \param [in] entrypoint | |
| 334 | //! VA entrypoint | |
| 335 | //! \param [in,out] attribList | |
| 336 | //! Pointer to VAConfigAttrib array. The attribute type is set by caller and | |
| 337 | //! attribute value is set by this function. | |
| 338 | //! \param [in] numAttribs | |
| 339 | //! Number of VAConfigAttrib in the array attribList | |
| 340 | //! | |
| 341 | //! \return VAStatus | |
| 342 | //! VA_STATUS_SUCCESS if success | |
| 343 | //! | |
| 344 | static VAStatus GetConfigAttributes( | |
| 345 | VADriverContextP ctx, | |
| 346 | VAProfile profile, | |
| 347 | VAEntrypoint entrypoint, | |
| 348 | VAConfigAttrib *attribList, | |
| 349 | int32_t numAttribs); | |
| 350 | ||
| 351 | //! | |
| 352 | //! \brief Get surface attributes for a given config ID | |
| 353 | //! | |
| 354 | //! \param [in] ctx | |
| 355 | //! Pointer to VA driver context | |
| 356 | //! \param [in] configId | |
| 357 | //! VA configuration | |
| 358 | //! \param [in,out] attribList | |
| 359 | //! Pointer to VASurfaceAttrib array. It returns | |
| 360 | //! the supported surface attributes | |
| 361 | //! \param [in,out] numAttribs | |
| 362 | //! The number of elements allocated on input | |
| 363 | //! Return the number of elements actually filled in output | |
| 364 | //! | |
| 365 | //! \return VAStatus | |
| 366 | //! VA_STATUS_SUCCESS if success | |
| 367 | //! VA_STATUS_ERROR_MAX_NUM_EXCEEDED if size of attribList is too small | |
| 368 | //! | |
| 369 | static VAStatus QuerySurfaceAttributes( | |
| 370 | VADriverContextP ctx, | |
| 371 | VAConfigID configId, | |
| 372 | VASurfaceAttrib *attribList, | |
| 373 | uint32_t *numAttribs); | |
| 374 | ||
| 375 | //! | |
| 376 | //! \brief Query the suppported image formats | |
| 377 | //! | |
| 378 | //! \param [in] ctx | |
| 379 | //! Pointer to VA driver context | |
| 380 | //! \param [in,out] formatList | |
| 381 | //! Pointer to a VAImageFormat array. The array size shouldn't be less than vaMaxNumImageFormats | |
| 382 | //! It will return the supported image formats. | |
| 383 | //! \param [in,out] num_formats | |
| 384 | //! Pointer to a integer that will return the real size of formatList. | |
| 385 | //! | |
| 386 | //! \return VAStatus | |
| 387 | //! VA_STATUS_SUCCESS if succeed | |
| 388 | //! | |
| 389 | static VAStatus QueryImageFormats( | |
| 390 | VADriverContextP ctx, | |
| 391 | VAImageFormat *formatList, | |
| 392 | int32_t *numFormats); | |
| 393 | ||
| 394 | //! | |
| 395 | //! \brief Get process rate for a given config ID | |
| 396 | //! | |
| 397 | //! \param [in] ctx | |
| 398 | //! Pointer to VA driver context | |
| 399 | //! \param [in] configId | |
| 400 | //! VA configuration | |
| 401 | //! \param [in,out] procBuf | |
| 402 | //! Pointer to VAProcessingRateParameter | |
| 403 | //! \param [in,out] processingRate | |
| 404 | //! Return the process rate | |
| 405 | //! | |
| 406 | //! \return VAStatus | |
| 407 | //! VA_STATUS_SUCCESS if success | |
| 408 | //! | |
| 409 | static VAStatus QueryProcessingRate( | |
| 410 | VADriverContextP ctx, | |
| 411 | VAConfigID configId, | |
| 412 | VAProcessingRateParameter *procBuf, | |
| 413 | uint32_t *processingRate); | |
| 238 | 414 | |
| 239 | 415 | //! |
| 240 | 416 | //! \brief Query video proc filters |
| 403 | 579 | #endif |
| 404 | 580 | |
| 405 | 581 | private: |
| 582 | //! | |
| 583 | //! \brief Map CompType from entrypoint | |
| 584 | //! | |
| 585 | //! \param [in] entrypoint | |
| 586 | //! VAEntrypoint | |
| 587 | //! | |
| 588 | //! \return CompType | |
| 589 | //! | |
| 590 | static CompType MapCompTypeFromEntrypoint(VAEntrypoint entrypoint); | |
| 591 | ||
| 406 | 592 | //! |
| 407 | 593 | //! \brief Map CompType from CtxType |
| 408 | 594 | //! |
| 622 | 808 | static bool DsoGetSymbols( |
| 623 | 809 | struct dso_handle *h, |
| 624 | 810 | void *vtable, |
| 625 | uint32_t vtable_length, | |
| 811 | uint32_t vtable_length, | |
| 626 | 812 | const struct dso_symbol *symbols); |
| 627 | 813 | |
| 628 | 814 | //! |
| 20 | 20 | set(TMP_SOURCES_ |
| 21 | 21 | ${CMAKE_CURRENT_LIST_DIR}/media_libva_interface_next.cpp |
| 22 | 22 | ${CMAKE_CURRENT_LIST_DIR}/ddi_media_functions.cpp |
| 23 | ${CMAKE_CURRENT_LIST_DIR}/media_capstable_linux.cpp | |
| 23 | ${CMAKE_CURRENT_LIST_DIR}/media_capstable_specific.cpp | |
| 24 | 24 | ${CMAKE_CURRENT_LIST_DIR}/media_libva_caps_next.cpp |
| 25 | 25 | ) |
| 26 | 26 | |
| 29 | 29 | ${CMAKE_CURRENT_LIST_DIR}/media_libva_register.h |
| 30 | 30 | ${CMAKE_CURRENT_LIST_DIR}/ddi_media_functions.h |
| 31 | 31 | ${CMAKE_CURRENT_LIST_DIR}/media_libva_common_next.h |
| 32 | ${CMAKE_CURRENT_LIST_DIR}/media_capstable_linux.h | |
| 32 | ${CMAKE_CURRENT_LIST_DIR}/media_capstable_specific.h | |
| 33 | 33 | ${CMAKE_CURRENT_LIST_DIR}/capstable_data_linux_definition.h |
| 34 | 34 | ${CMAKE_CURRENT_LIST_DIR}/media_libva_caps_next.h |
| 35 | ${CMAKE_CURRENT_LIST_DIR}/capstable_data_hevc_vdenc_m12_0_r0_specific.h | |
| 36 | ${CMAKE_CURRENT_LIST_DIR}/capstable_data_m12_0_r0_specific.h.h | |
| 37 | ${CMAKE_CURRENT_LIST_DIR}/capstable_data_image_format_definition.h | |
| 38 | ${CMAKE_CURRENT_LIST_DIR}/caps_register_specific.h | |
| 35 | 39 | ) |
| 36 | 40 | |
| 37 | 41 | set(SOURCES_ |
| 23 | 23 | //! \brief ddi encode functions implementaion. |
| 24 | 24 | //! |
| 25 | 25 | #include "ddi_encode_functions.h" |
| 26 | #include "media_libva_util.h" | |
| 27 | #include "media_libva_common_next.h" | |
| 28 | ||
| 29 | VAStatus DdiEncodeFunctions::CreateConfig ( | |
| 30 | VADriverContextP ctx, | |
| 31 | VAProfile profile, | |
| 32 | VAEntrypoint entrypoint, | |
| 33 | VAConfigAttrib *attribList, | |
| 34 | int32_t numAttribs, | |
| 35 | VAConfigID *configId) | |
| 36 | { | |
| 37 | VAStatus status = VA_STATUS_SUCCESS; | |
| 38 | DDI_CHK_NULL(configId, "nullptr configId", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 39 | DDI_CHK_NULL(attribList, "nullptr attribList", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 40 | ||
| 41 | PDDI_MEDIA_CONTEXT mediaCtx = GetMediaContext(ctx); | |
| 42 | DDI_CHK_NULL(mediaCtx, "nullptr mediaCtx", VA_STATUS_ERROR_INVALID_CONTEXT); | |
| 43 | DDI_CHK_NULL(mediaCtx->m_capsNext, "nullptr m_caps", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 44 | ||
| 45 | status = mediaCtx->m_capsNext->CreateConfig(profile, entrypoint, attribList, numAttribs, configId); | |
| 46 | DDI_CHK_RET(status, "Create common config failed"); | |
| 47 | ||
| 48 | uint32_t rcMode = 0; | |
| 49 | uint32_t feiFunction = 0; | |
| 50 | ||
| 51 | for(int i = 0; i < numAttribs; i++) | |
| 52 | { | |
| 53 | if(attribList[i].type == VAConfigAttribFEIFunctionType) | |
| 54 | { | |
| 55 | feiFunction = attribList[i].value; | |
| 56 | } | |
| 57 | ||
| 58 | if(attribList[i].type == VAConfigAttribRateControl) | |
| 59 | { | |
| 60 | rcMode = attribList[i].value; | |
| 61 | } | |
| 62 | } | |
| 63 | ||
| 64 | auto configList = mediaCtx->m_capsNext->GetConfigList(); | |
| 65 | DDI_CHK_NULL(configList, "Get configList failed", VA_STATUS_ERROR_INVALID_PARAMETER); | |
| 66 | ||
| 67 | for(int i = 0; i < configList->size(); i++) | |
| 68 | { | |
| 69 | if((configList->at(i).profile == profile) && | |
| 70 | (configList->at(i).entrypoint == entrypoint)) | |
| 71 | { | |
| 72 | if((rcMode == configList->at(i).componentData.data.rcMode) && | |
| 73 | (feiFunction == configList->at(i).componentData.data.feiFunction)) | |
| 74 | { | |
| 75 | *configId = i; | |
| 76 | return VA_STATUS_SUCCESS; | |
| 77 | } | |
| 78 | } | |
| 79 | } | |
| 80 | ||
| 81 | *configId = 0xFFFFFFFF; | |
| 82 | return VA_STATUS_ERROR_ATTR_NOT_SUPPORTED; | |
| 83 | } | |
| 26 | 84 | |
| 27 | 85 | VAStatus DdiEncodeFunctions::CreateContext ( |
| 28 | 86 | VADriverContextP ctx, |
| 27 | 27 | #define __DDI_ENCODE_FUNCTIONS_H__ |
| 28 | 28 | |
| 29 | 29 | #include "ddi_media_functions.h" |
| 30 | #include "media_libva_caps_next.h" | |
| 30 | 31 | |
| 31 | 32 | class DdiEncodeFunctions :public DdiMediaFunctions |
| 32 | 33 | { |
| 33 | 34 | public: |
| 34 | 35 | |
| 35 | 36 | virtual ~DdiEncodeFunctions() override{}; |
| 37 | ||
| 38 | //! | |
| 39 | //! \brief Create a configuration | |
| 40 | //! \details It passes in the attribute list that specifies the attributes it | |
| 41 | //! cares about, with the rest taking default values. | |
| 42 | //! | |
| 43 | //! \param [in] ctx | |
| 44 | //! Pointer to VA driver context | |
| 45 | //! \param [in] profile | |
| 46 | //! VA profile | |
| 47 | //! \param [in] entrypoint | |
| 48 | //! VA entrypoint | |
| 49 | //! \param [in] attribList | |
| 50 | //! Pointer to VAConfigAttrib array that specifies the attributes | |
| 51 | //! \param [in] numAttribs | |
| 52 | //! Number of VAConfigAttrib in the array attribList | |
| 53 | //! \param [out] configId | |
| 54 | //! Pointer to returned VAConfigID if success | |
| 55 | //! | |
| 56 | //! \return VAStatus | |
| 57 | //! VA_STATUS_SUCCESS if success | |
| 58 | //! | |
| 59 | virtual VAStatus CreateConfig( | |
| 60 | VADriverContextP ctx, | |
| 61 | VAProfile profile, | |
| 62 | VAEntrypoint entrypoint, | |
| 63 | VAConfigAttrib *attribList, | |
| 64 | int32_t numAttribs, | |
| 65 | VAConfigID *configId | |
| 66 | ) override; | |
| 67 | ||
| 36 | 68 | //! |
| 37 | 69 | //! \brief Create context |
| 38 | 70 | //! |
| 0 | # Copyright (c) 2017, Intel Corporation | |
| 1 | # | |
| 2 | # Permission is hereby granted, free of charge, to any person obtaining a | |
| 3 | # copy of this software and associated documentation files (the "Software"), | |
| 4 | # to deal in the Software without restriction, including without limitation | |
| 5 | # the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
| 6 | # and/or sell copies of the Software, and to permit persons to whom the | |
| 7 | # Software is furnished to do so, subject to the following conditions: | |
| 8 | # | |
| 9 | # The above copyright notice and this permission notice shall be included | |
| 10 | # in all copies or substantial portions of the Software. | |
| 11 | # | |
| 12 | # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
| 13 | # OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
| 14 | # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
| 15 | # THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
| 16 | # OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
| 17 | # ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 18 | # OTHER DEALINGS IN THE SOFTWARE. | |
| 19 | ||
| 20 | project( media ) | |
| 21 | ||
| 22 | find_package(PkgConfig) | |
| 23 | find_package(X11) | |
| 24 | ||
| 25 | bs_set_if_undefined(LIB_NAME iHD_drv_video) | |
| 26 | ||
| 27 | option (MEDIA_RUN_TEST_SUITE "run google test module after install" ON) | |
| 28 | include(${MEDIA_SOFTLET_CMAKE}/media_gen_flags.cmake) | |
| 29 | include(${MEDIA_SOFTLET_CMAKE}/media_feature_flags.cmake) | |
| 30 | ||
| 31 | ||
| 32 | if(NOT DEFINED SKIP_GMM_CHECK) | |
| 33 | # checking dependencies | |
| 34 | pkg_check_modules(LIBGMM igdgmm) | |
| 35 | ||
| 36 | if(LIBGMM_FOUND) | |
| 37 | include_directories(BEFORE ${LIBGMM_INCLUDE_DIRS}) | |
| 38 | # link_directories() should appear before add_library and the like | |
| 39 | # otherwise it will not take effect | |
| 40 | link_directories(${LIBGMM_LIBRARY_DIRS}) | |
| 41 | endif() | |
| 42 | endif(NOT DEFINED SKIP_GMM_CHECK) | |
| 43 | ||
| 44 | message("-- media -- PLATFORM = ${PLATFORM}") | |
| 45 | message("-- media -- ARCH = ${ARCH}") | |
| 46 | message("-- media -- CMAKE_CURRENT_LIST_DIR = ${CMAKE_CURRENT_LIST_DIR}") | |
| 47 | message("-- media -- INCLUDED_LIBS = ${INCLUDED_LIBS}") | |
| 48 | message("-- media -- LIB_NAME = ${LIB_NAME}") | |
| 49 | message("-- media -- OUTPUT_NAME = ${OUTPUT_NAME}") | |
| 50 | message("-- media -- BUILD_TYPE/UFO_BUILD_TYPE/CMAKE_BUILD_TYPE = ${BUILD_TYPE}/${UFO_BUILD_TYPE}/${CMAKE_BUILD_TYPE}") | |
| 51 | message("-- media -- LIBVA_INSTALL_PATH = ${LIBVA_INSTALL_PATH}") | |
| 52 | message("-- media -- MEDIA_VERSION = ${MEDIA_VERSION}") | |
| 53 | if(X11_FOUND) | |
| 54 | message("-- media -- X11 Found") | |
| 55 | endif() | |
| 56 | ||
| 57 | set(LIB_NAME_OBJ "${LIB_NAME}_OBJ") | |
| 58 | set(LIB_NAME_STATIC "${LIB_NAME}_STATIC") | |
| 59 | set(SOURCES_ "") | |
| 60 | ||
| 61 | # add source | |
| 62 | media_include_subdirectory(agnostic) | |
| 63 | media_include_subdirectory(linux) | |
| 64 | media_include_subdirectory(../media_common/agnostic) | |
| 65 | media_include_subdirectory(../media_common/linux) | |
| 66 | ||
| 67 | include(${MEDIA_SOFTLET_EXT}/media_srcs_ext.cmake OPTIONAL) | |
| 68 | include(${MEDIA_COMMON_EXT}/media_srcs_ext.cmake OPTIONAL) | |
| 69 | ||
| 70 | include(${MEDIA_SOFTLET_CMAKE}/media_include_paths.cmake) | |
| 71 | ||
| 72 | include(${MEDIA_SOFTLET_CMAKE}/media_compile_flags.cmake) | |
| 73 | ||
| 74 | # | |
| 75 | # set platform specific defines | |
| 76 | # | |
| 77 | bs_set_defines() | |
| 78 | ||
| 79 | ||
| 80 | set_source_files_properties(${SOURCES_} PROPERTIES LANGUAGE "CXX") | |
| 81 | ||
| 82 | add_library(${LIB_NAME_OBJ} OBJECT ${SOURCES_}) | |
| 83 | set_property(TARGET ${LIB_NAME_OBJ} PROPERTY POSITION_INDEPENDENT_CODE 1) | |
| 84 | ||
| 85 | add_library(${LIB_NAME} SHARED | |
| 86 | $<TARGET_OBJECTS:${LIB_NAME_OBJ}>) | |
| 87 | ||
| 88 | add_library(${LIB_NAME_STATIC} STATIC | |
| 89 | $<TARGET_OBJECTS:${LIB_NAME_OBJ}>) | |
| 90 | ||
| 91 | set_target_properties(${LIB_NAME_STATIC} PROPERTIES OUTPUT_NAME ${LIB_NAME}) | |
| 92 | ||
| 93 | option(MEDIA_BUILD_FATAL_WARNINGS "Turn compiler warnings into fatal errors" ON) | |
| 94 | if(MEDIA_BUILD_FATAL_WARNINGS) | |
| 95 | set_target_properties(${LIB_NAME_OBJ} PROPERTIES COMPILE_FLAGS "-Werror") | |
| 96 | endif() | |
| 97 | ||
| 98 | set_target_properties(${LIB_NAME} PROPERTIES LINK_FLAGS "-Wl,--no-as-needed -Wl,--gc-sections -z relro -z now -fstack-protector -fPIC") | |
| 99 | set_target_properties(${LIB_NAME} PROPERTIES PREFIX "") | |
| 100 | set_target_properties(${LIB_NAME_STATIC} PROPERTIES PREFIX "") | |
| 101 | ||
| 102 | MediaAddCommonTargetDefines(${LIB_NAME_OBJ}) | |
| 103 | ||
| 104 | bs_ufo_link_libraries_noBsymbolic( | |
| 105 | ${LIB_NAME} | |
| 106 | "${INCLUDED_LIBS}" | |
| 107 | "${PKG_PCIACCESS_LIBRARIES} m pthread dl" | |
| 108 | ) | |
| 109 | ||
| 110 | if (NOT DEFINED INCLUDED_LIBS OR "${INCLUDED_LIBS}" STREQUAL "") | |
| 111 | # dep libs (gmmlib for now) can be passed through INCLUDED_LIBS, but if not, we need try to setup dep through including dep projects | |
| 112 | if(NOT LIBGMM_FOUND) | |
| 113 | # If we failed to setup dependency from gmmlib via pkg-config we will try to | |
| 114 | # add gmmlib as a target from sources. We need to do this here, after | |
| 115 | # add_library() for iHD driver since gmmlib needs this information. | |
| 116 | if (NOT TARGET igfx_gmmumd_dll) | |
| 117 | add_subdirectory("${BS_DIR_GMMLIB}" "${CMAKE_BINARY_DIR}/gmmlib") | |
| 118 | endif() | |
| 119 | if (NOT TARGET igfx_gmmumd_dll) | |
| 120 | message(FATAL_ERROR "gmm library not found on the system") | |
| 121 | endif() | |
| 122 | set(LIBGMM_CFLAGS_OTHER -DGMM_LIB_DLL) | |
| 123 | set(LIBGMM_LIBRARIES igfx_gmmumd_dll) | |
| 124 | endif() | |
| 125 | ||
| 126 | target_compile_options( ${LIB_NAME} PUBLIC ${LIBGMM_CFLAGS_OTHER}) | |
| 127 | target_link_libraries ( ${LIB_NAME} ${LIBGMM_LIBRARIES}) | |
| 128 | ||
| 129 | target_compile_definitions(${LIB_NAME} PUBLIC GMM_LIB_DLL) | |
| 130 | include(${MEDIA_SOFTLET_EXT_CMAKE}/media_feature_include_ext.cmake OPTIONAL) | |
| 131 | ||
| 132 | endif(NOT DEFINED INCLUDED_LIBS OR "${INCLUDED_LIBS}" STREQUAL "") | |
| 133 | ||
| 134 | # post target attributes | |
| 135 | bs_set_post_target() | |
| 136 | ||
| 137 | if(MEDIA_RUN_TEST_SUITE AND ENABLE_KERNELS AND ENABLE_NONFREE_KERNELS) | |
| 138 | ||
| 139 | endif() |