vhdl code library ieee;
vhdl code use ieee.std_logic_1164.all;
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vhdl code entity tb is
vhdl code end tb;
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vhdl code architecture behav of tb is
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vhdl comment -- toggle period
vhdl code constant period_c : time := 1 ms;
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vhdl comment -- we'll be poking on this signal
vhdl code signal toggle_s : std_logic_vector(1 downto 0) := "01";
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vhdl code begin
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vhdl comment -----------------------------------------------------------------------------
vhdl comment -- Process toggle
vhdl comment --
vhdl comment -- Purpose:
vhdl comment -- Flip the toggle_s signal periodically.
vhdl comment --
vhdl code toggle: process
vhdl code begin
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vhdl code wait for period_c/2;
vhdl code toggle_s <= not toggle_s;
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vhdl code end process toggle;
vhdl comment --
vhdl comment -----------------------------------------------------------------------------
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vhdl code end behav;
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vhdl code configuration tb_behav_c0 of tb is
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vhdl code for behav
vhdl code end for;
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vhdl code end tb_behav_c0;