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;  Copyright(c) 2011-2016 Intel Corporation All rights reserved.
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;  modification, are permitted provided that the following conditions
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;      distribution.
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default rel
[bits 64]

%ifidn __OUTPUT_FORMAT__, elf64
%define WRT_OPT         wrt ..plt
%else
%define WRT_OPT
%endif

%include "reg_sizes.asm"

extern isal_deflate_body_stateless_base
extern isal_deflate_body_stateless_01
extern isal_deflate_body_stateless_04

extern isal_deflate_body_base
extern isal_deflate_body_01
extern isal_deflate_body_04
extern isal_deflate_finish_base
extern isal_deflate_finish_01

extern get_crc_base
extern get_crc_01

extern isal_deflate_init_base
extern isal_deflate_init_01

section .text

%include "multibinary.asm"

mbin_interface		isal_deflate_init
mbin_dispatch_init5	isal_deflate_init, isal_deflate_init_base, isal_deflate_init_01, isal_deflate_init_01, isal_deflate_init_01

mbin_interface		isal_deflate_body_stateless
mbin_dispatch_init5	isal_deflate_body_stateless, isal_deflate_body_stateless_base, isal_deflate_body_stateless_01, isal_deflate_body_stateless_01, isal_deflate_body_stateless_04

mbin_interface		isal_deflate_body
mbin_dispatch_init5	isal_deflate_body, isal_deflate_body_base, isal_deflate_body_01, isal_deflate_body_01, isal_deflate_body_04
mbin_interface		isal_deflate_finish
mbin_dispatch_init5	isal_deflate_finish, isal_deflate_finish_base, isal_deflate_finish_01, isal_deflate_finish_01, isal_deflate_finish_01

mbin_interface		get_crc
mbin_dispatch_init5	get_crc, get_crc_base, get_crc_01, get_crc_01, get_crc_01